1//===----------------------------------------------------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9//===----------------------------------------------------------------------===// 10 11// tag : C2_cmpeq 12class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix, 13 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 14 : Hexagon_Intrinsic<GCCIntSuffix, 15 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], 16 intr_properties>; 17 18// tag : C2_cmpeqp 19class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix, 20 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 21 : Hexagon_Intrinsic<GCCIntSuffix, 22 [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], 23 intr_properties>; 24 25// tag : C2_not 26class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix, 27 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 28 : Hexagon_Intrinsic<GCCIntSuffix, 29 [llvm_i32_ty], [llvm_i32_ty], 30 intr_properties>; 31 32// tag : C4_and_and 33class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix, 34 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 35 : Hexagon_Intrinsic<GCCIntSuffix, 36 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 37 intr_properties>; 38 39// tag : C2_vmux 40class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix, 41 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 42 : Hexagon_Intrinsic<GCCIntSuffix, 43 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty], 44 intr_properties>; 45 46// tag : C2_mask 47class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix, 48 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 49 : Hexagon_Intrinsic<GCCIntSuffix, 50 [llvm_i64_ty], [llvm_i32_ty], 51 intr_properties>; 52 53// tag : A4_vcmpbeqi 54class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, 55 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 56 : Hexagon_Intrinsic<GCCIntSuffix, 57 [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty], 58 intr_properties>; 59 60// tag : A4_boundscheck 61class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix, 62 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty], 65 intr_properties>; 66 67// tag : M2_mpyd_acc_hh_s0 68class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, 69 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 70 : Hexagon_Intrinsic<GCCIntSuffix, 71 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 72 intr_properties>; 73 74// tag : M2_mpyd_hh_s0 75class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, 76 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 77 : Hexagon_Intrinsic<GCCIntSuffix, 78 [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], 79 intr_properties>; 80 81// tag : M2_vmpy2es_s0 82class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix, 83 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 84 : Hexagon_Intrinsic<GCCIntSuffix, 85 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], 86 intr_properties>; 87 88// tag : M2_vmac2es_s0 89class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix, 90 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 91 : Hexagon_Intrinsic<GCCIntSuffix, 92 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], 93 intr_properties>; 94 95// tag : M2_vrcmpys_s1 96class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix, 97 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 98 : Hexagon_Intrinsic<GCCIntSuffix, 99 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], 100 intr_properties>; 101 102// tag : M2_vrcmpys_acc_s1 103class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix, 104 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 105 : Hexagon_Intrinsic<GCCIntSuffix, 106 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], 107 intr_properties>; 108 109// tag : S4_vrcrotate_acc 110class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix, 111 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 112 : Hexagon_Intrinsic<GCCIntSuffix, 113 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 114 intr_properties>; 115 116// tag : A2_addsp 117class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix, 118 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 119 : Hexagon_Intrinsic<GCCIntSuffix, 120 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty], 121 intr_properties>; 122 123// tag : A2_vconj 124class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix, 125 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 126 : Hexagon_Intrinsic<GCCIntSuffix, 127 [llvm_i64_ty], [llvm_i64_ty], 128 intr_properties>; 129 130// tag : A2_sat 131class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix, 132 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 133 : Hexagon_Intrinsic<GCCIntSuffix, 134 [llvm_i32_ty], [llvm_i64_ty], 135 intr_properties>; 136 137// tag : F2_sfadd 138class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix, 139 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 140 : Hexagon_Intrinsic<GCCIntSuffix, 141 [llvm_float_ty], [llvm_float_ty,llvm_float_ty], 142 intr_properties>; 143 144// tag : F2_sffma 145class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix, 146 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 147 : Hexagon_Intrinsic<GCCIntSuffix, 148 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty], 149 intr_properties>; 150 151// tag : F2_sffma_sc 152class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix, 153 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 154 : Hexagon_Intrinsic<GCCIntSuffix, 155 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty], 156 intr_properties>; 157 158// tag : F2_sfcmpeq 159class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix, 160 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 161 : Hexagon_Intrinsic<GCCIntSuffix, 162 [llvm_i32_ty], [llvm_float_ty,llvm_float_ty], 163 intr_properties>; 164 165// tag : F2_sfclass 166class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix, 167 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 168 : Hexagon_Intrinsic<GCCIntSuffix, 169 [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty], 170 intr_properties>; 171 172// tag : F2_sfimm_p 173class Hexagon_float_i32_Intrinsic<string GCCIntSuffix, 174 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 175 : Hexagon_Intrinsic<GCCIntSuffix, 176 [llvm_float_ty], [llvm_i32_ty], 177 intr_properties>; 178 179// tag : F2_sffixupr 180class Hexagon_float_float_Intrinsic<string GCCIntSuffix, 181 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 182 : Hexagon_Intrinsic<GCCIntSuffix, 183 [llvm_float_ty], [llvm_float_ty], 184 intr_properties>; 185 186// tag : F2_dfadd 187class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix, 188 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 189 : Hexagon_Intrinsic<GCCIntSuffix, 190 [llvm_double_ty], [llvm_double_ty,llvm_double_ty], 191 intr_properties>; 192 193// tag : F2_dfmpylh 194class Hexagon_double_doubledoubledouble_Intrinsic<string GCCIntSuffix, 195 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 196 : Hexagon_Intrinsic<GCCIntSuffix, 197 [llvm_double_ty], [llvm_double_ty,llvm_double_ty,llvm_double_ty], 198 intr_properties>; 199 200// tag : F2_dfcmpeq 201class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix, 202 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 203 : Hexagon_Intrinsic<GCCIntSuffix, 204 [llvm_i32_ty], [llvm_double_ty,llvm_double_ty], 205 intr_properties>; 206 207// tag : F2_dfclass 208class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix, 209 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 210 : Hexagon_Intrinsic<GCCIntSuffix, 211 [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty], 212 intr_properties>; 213 214// tag : F2_dfimm_p 215class Hexagon_double_i32_Intrinsic<string GCCIntSuffix, 216 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 217 : Hexagon_Intrinsic<GCCIntSuffix, 218 [llvm_double_ty], [llvm_i32_ty], 219 intr_properties>; 220 221// tag : F2_conv_sf2df 222class Hexagon_double_float_Intrinsic<string GCCIntSuffix, 223 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 224 : Hexagon_Intrinsic<GCCIntSuffix, 225 [llvm_double_ty], [llvm_float_ty], 226 intr_properties>; 227 228// tag : F2_conv_df2sf 229class Hexagon_float_double_Intrinsic<string GCCIntSuffix, 230 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 231 : Hexagon_Intrinsic<GCCIntSuffix, 232 [llvm_float_ty], [llvm_double_ty], 233 intr_properties>; 234 235// tag : F2_conv_ud2sf 236class Hexagon_float_i64_Intrinsic<string GCCIntSuffix, 237 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 238 : Hexagon_Intrinsic<GCCIntSuffix, 239 [llvm_float_ty], [llvm_i64_ty], 240 intr_properties>; 241 242// tag : F2_conv_ud2df 243class Hexagon_double_i64_Intrinsic<string GCCIntSuffix, 244 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 245 : Hexagon_Intrinsic<GCCIntSuffix, 246 [llvm_double_ty], [llvm_i64_ty], 247 intr_properties>; 248 249// tag : F2_conv_sf2uw 250class Hexagon_i32_float_Intrinsic<string GCCIntSuffix, 251 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 252 : Hexagon_Intrinsic<GCCIntSuffix, 253 [llvm_i32_ty], [llvm_float_ty], 254 intr_properties>; 255 256// tag : F2_conv_sf2ud 257class Hexagon_i64_float_Intrinsic<string GCCIntSuffix, 258 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 259 : Hexagon_Intrinsic<GCCIntSuffix, 260 [llvm_i64_ty], [llvm_float_ty], 261 intr_properties>; 262 263// tag : F2_conv_df2uw 264class Hexagon_i32_double_Intrinsic<string GCCIntSuffix, 265 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 266 : Hexagon_Intrinsic<GCCIntSuffix, 267 [llvm_i32_ty], [llvm_double_ty], 268 intr_properties>; 269 270// tag : F2_conv_df2ud 271class Hexagon_i64_double_Intrinsic<string GCCIntSuffix, 272 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 273 : Hexagon_Intrinsic<GCCIntSuffix, 274 [llvm_i64_ty], [llvm_double_ty], 275 intr_properties>; 276 277// tag : S2_insert 278class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix, 279 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 280 : Hexagon_Intrinsic<GCCIntSuffix, 281 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 282 intr_properties>; 283 284// tag : S2_insert_rp 285class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix, 286 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 287 : Hexagon_Intrinsic<GCCIntSuffix, 288 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty], 289 intr_properties>; 290 291// tag : Y2_dcfetch 292class Hexagon__ptr_Intrinsic<string GCCIntSuffix, 293 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 294 : Hexagon_Intrinsic<GCCIntSuffix, 295 [], [llvm_ptr_ty], 296 intr_properties>; 297 298// tag : Y4_l2fetch 299class Hexagon__ptri32_Intrinsic<string GCCIntSuffix, 300 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 301 : Hexagon_Intrinsic<GCCIntSuffix, 302 [], [llvm_ptr_ty,llvm_i32_ty], 303 intr_properties>; 304 305// tag : Y5_l2fetch 306class Hexagon__ptri64_Intrinsic<string GCCIntSuffix, 307 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 308 : Hexagon_Intrinsic<GCCIntSuffix, 309 [], [llvm_ptr_ty,llvm_i64_ty], 310 intr_properties>; 311 312// tag : 313class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix, 314 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 315 : Hexagon_Intrinsic<GCCIntSuffix, 316 [llvm_v32i32_ty], [llvm_v32i32_ty], 317 intr_properties>; 318 319// tag : 320class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix, 321 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 322 : Hexagon_Intrinsic<GCCIntSuffix, 323 [llvm_v64i32_ty], [llvm_v64i32_ty], 324 intr_properties>; 325 326// tag : 327class Hexagon_v32i32__Intrinsic<string GCCIntSuffix, 328 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 329 : Hexagon_Intrinsic<GCCIntSuffix, 330 [llvm_v32i32_ty], [], 331 intr_properties>; 332 333// tag : 334class Hexagon_v64i32__Intrinsic<string GCCIntSuffix, 335 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 336 : Hexagon_Intrinsic<GCCIntSuffix, 337 [llvm_v64i32_ty], [], 338 intr_properties>; 339 340// tag : 341class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix, 342 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 343 : Hexagon_Intrinsic<GCCIntSuffix, 344 [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 345 intr_properties>; 346 347// tag : 348class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix, 349 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 350 : Hexagon_Intrinsic<GCCIntSuffix, 351 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 352 intr_properties>; 353 354// tag : 355class Hexagon_i64_v32i32i32_Intrinsic<string GCCIntSuffix, 356 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 357 : Hexagon_Intrinsic<GCCIntSuffix, 358 [llvm_i64_ty], [llvm_v32i32_ty,llvm_i32_ty], 359 intr_properties>; 360 361// tag : 362class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 363 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 364 : Hexagon_Intrinsic<GCCIntSuffix, 365 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 366 intr_properties>; 367 368// tag : 369class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix, 370 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 371 : Hexagon_Intrinsic<GCCIntSuffix, 372 [llvm_v32i32_ty], [llvm_i32_ty], 373 intr_properties>; 374 375// tag : 376class Hexagon_v64i32_i32_Intrinsic<string GCCIntSuffix, 377 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 378 : Hexagon_Intrinsic<GCCIntSuffix, 379 [llvm_v64i32_ty], [llvm_i32_ty], 380 intr_properties>; 381 382// tag : 383class Hexagon_v64i32_i64_Intrinsic<string GCCIntSuffix, 384 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 385 : Hexagon_Intrinsic<GCCIntSuffix, 386 [llvm_v64i32_ty], [llvm_i64_ty], 387 intr_properties>; 388 389// tag : 390class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 391 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 392 : Hexagon_Intrinsic<GCCIntSuffix, 393 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 394 intr_properties>; 395 396// tag : 397class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix, 398 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 399 : Hexagon_Intrinsic<GCCIntSuffix, 400 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 401 intr_properties>; 402 403// tag : 404class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix, 405 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 406 : Hexagon_Intrinsic<GCCIntSuffix, 407 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 408 intr_properties>; 409 410// tag : 411class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, 412 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 413 : Hexagon_Intrinsic<GCCIntSuffix, 414 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], 415 intr_properties>; 416 417// tag : 418class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix, 419 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 420 : Hexagon_Intrinsic<GCCIntSuffix, 421 [llvm_v64i32_ty], [llvm_v32i32_ty], 422 intr_properties>; 423 424// tag : 425class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, 426 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 427 : Hexagon_Intrinsic<GCCIntSuffix, 428 [llvm_v32i32_ty], [llvm_v64i32_ty], 429 intr_properties>; 430 431// tag : 432class Hexagon_v4i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 433 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 434 : Hexagon_Intrinsic<GCCIntSuffix, 435 [llvm_v4i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 436 intr_properties>; 437 438// tag : 439class Hexagon_v4i32_v32i32i32_Intrinsic<string GCCIntSuffix, 440 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 441 : Hexagon_Intrinsic<GCCIntSuffix, 442 [llvm_v4i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 443 intr_properties>; 444 445// tag : 446class Hexagon_v32i32_v4i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 447 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 448 : Hexagon_Intrinsic<GCCIntSuffix, 449 [llvm_v32i32_ty], [llvm_v4i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 450 intr_properties>; 451 452// tag : 453class Hexagon_v64i32_v8i32v64i32v64i32_Intrinsic<string GCCIntSuffix, 454 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 455 : Hexagon_Intrinsic<GCCIntSuffix, 456 [llvm_v64i32_ty], [llvm_v8i32_ty,llvm_v64i32_ty,llvm_v64i32_ty], 457 intr_properties>; 458 459// tag : 460class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix, 461 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 462 : Hexagon_Intrinsic<GCCIntSuffix, 463 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 464 intr_properties>; 465 466// tag : 467class Hexagon_v32i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, 468 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 469 : Hexagon_Intrinsic<GCCIntSuffix, 470 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], 471 intr_properties>; 472 473// tag : 474class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 475 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 476 : Hexagon_Intrinsic<GCCIntSuffix, 477 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 478 intr_properties>; 479 480// tag : 481class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 482 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 483 : Hexagon_Intrinsic<GCCIntSuffix, 484 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 485 intr_properties>; 486 487// tag : 488class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 489 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 490 : Hexagon_Intrinsic<GCCIntSuffix, 491 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 492 intr_properties>; 493 494// tag : 495class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 496 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 497 : Hexagon_Intrinsic<GCCIntSuffix, 498 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 499 intr_properties>; 500 501// tag : 502class Hexagon_v32i32_v32i32v64i32_Intrinsic<string GCCIntSuffix, 503 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 504 : Hexagon_Intrinsic<GCCIntSuffix, 505 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty], 506 intr_properties>; 507 508// tag : 509class Hexagon_v64i32_v64i32v4i32_Intrinsic<string GCCIntSuffix, 510 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 511 : Hexagon_Intrinsic<GCCIntSuffix, 512 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v4i32_ty], 513 intr_properties>; 514 515// tag : 516class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 517 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 518 : Hexagon_Intrinsic<GCCIntSuffix, 519 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 520 intr_properties>; 521 522// tag : 523class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 524 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 525 : Hexagon_Intrinsic<GCCIntSuffix, 526 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 527 intr_properties>; 528 529// tag : 530class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix, 531 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 532 : Hexagon_Intrinsic<GCCIntSuffix, 533 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], 534 intr_properties>; 535 536// tag : 537class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 538 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 539 : Hexagon_Intrinsic<GCCIntSuffix, 540 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 541 intr_properties>; 542 543// tag : 544class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix, 545 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 546 : Hexagon_Intrinsic<GCCIntSuffix, 547 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 548 intr_properties>; 549 550// tag : V6_vS32b_qpred_ai 551class Hexagon_custom__v64i1ptrv16i32_Intrinsic< 552 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 553 : Hexagon_NonGCC_Intrinsic< 554 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], 555 intr_properties>; 556 557// tag : V6_vS32b_qpred_ai 558class Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B< 559 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 560 : Hexagon_NonGCC_Intrinsic< 561 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], 562 intr_properties>; 563 564// tag : V6_valignb 565class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 566 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 567 : Hexagon_Intrinsic<GCCIntSuffix, 568 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 569 intr_properties>; 570 571// tag : V6_vror 572class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix, 573 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 574 : Hexagon_Intrinsic<GCCIntSuffix, 575 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 576 intr_properties>; 577 578// tag : V6_vunpackub 579class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix, 580 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 581 : Hexagon_Intrinsic<GCCIntSuffix, 582 [llvm_v32i32_ty], [llvm_v16i32_ty], 583 intr_properties>; 584 585// tag : V6_vunpackob 586class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix, 587 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 588 : Hexagon_Intrinsic<GCCIntSuffix, 589 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 590 intr_properties>; 591 592// tag : V6_vpackeb 593class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 594 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 595 : Hexagon_Intrinsic<GCCIntSuffix, 596 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 597 intr_properties>; 598 599// tag : V6_vdmpyhvsat_acc 600class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 601 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 602 : Hexagon_Intrinsic<GCCIntSuffix, 603 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 604 intr_properties>; 605 606// tag : V6_vdmpyhisat 607class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix, 608 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 609 : Hexagon_Intrinsic<GCCIntSuffix, 610 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 611 intr_properties>; 612 613// tag : V6_vdmpyhisat_acc 614class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix, 615 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 616 : Hexagon_Intrinsic<GCCIntSuffix, 617 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], 618 intr_properties>; 619 620// tag : V6_vdmpyhisat_acc 621class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix, 622 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 623 : Hexagon_Intrinsic<GCCIntSuffix, 624 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], 625 intr_properties>; 626 627// tag : V6_vrmpyubi 628class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix, 629 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 630 : Hexagon_Intrinsic<GCCIntSuffix, 631 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 632 intr_properties>; 633 634// tag : V6_vrmpyubi 635class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix, 636 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 637 : Hexagon_Intrinsic<GCCIntSuffix, 638 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 639 intr_properties>; 640 641// tag : V6_vrmpyubi_acc 642class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix, 643 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 644 : Hexagon_Intrinsic<GCCIntSuffix, 645 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 646 intr_properties>; 647 648// tag : V6_vrmpyubi_acc 649class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix, 650 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 651 : Hexagon_Intrinsic<GCCIntSuffix, 652 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 653 intr_properties>; 654 655// tag : V6_vasr_into 656class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 657 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 658 : Hexagon_Intrinsic<GCCIntSuffix, 659 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 660 intr_properties>; 661 662// tag : V6_vaddcarrysat 663class Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic< 664 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 665 : Hexagon_NonGCC_Intrinsic< 666 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 667 intr_properties>; 668 669// tag : V6_vaddcarrysat 670class Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B< 671 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 672 : Hexagon_NonGCC_Intrinsic< 673 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 674 intr_properties>; 675 676// tag : V6_vaddcarry 677class Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic< 678 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 679 : Hexagon_NonGCC_Intrinsic< 680 [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 681 intr_properties>; 682 683// tag : V6_vaddcarry 684class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B< 685 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 686 : Hexagon_NonGCC_Intrinsic< 687 [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 688 intr_properties>; 689 690// tag : V6_vaddubh 691class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 692 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 693 : Hexagon_Intrinsic<GCCIntSuffix, 694 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 695 intr_properties>; 696 697// tag : V6_vd0 698class Hexagon_v16i32__Intrinsic<string GCCIntSuffix, 699 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 700 : Hexagon_Intrinsic<GCCIntSuffix, 701 [llvm_v16i32_ty], [], 702 intr_properties>; 703 704// tag : V6_vaddbq 705class Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic< 706 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 707 : Hexagon_NonGCC_Intrinsic< 708 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 709 intr_properties>; 710 711// tag : V6_vaddbq 712class Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B< 713 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 714 : Hexagon_NonGCC_Intrinsic< 715 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 716 intr_properties>; 717 718// tag : V6_vabsb 719class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix, 720 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 721 : Hexagon_Intrinsic<GCCIntSuffix, 722 [llvm_v16i32_ty], [llvm_v16i32_ty], 723 intr_properties>; 724 725// tag : V6_vmpyub 726class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix, 727 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 728 : Hexagon_Intrinsic<GCCIntSuffix, 729 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 730 intr_properties>; 731 732// tag : V6_vmpyub 733class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix, 734 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 735 : Hexagon_Intrinsic<GCCIntSuffix, 736 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 737 intr_properties>; 738 739// tag : V6_vmpyub_acc 740class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix, 741 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 742 : Hexagon_Intrinsic<GCCIntSuffix, 743 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], 744 intr_properties>; 745 746// tag : V6_vmpyub_acc 747class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix, 748 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 749 : Hexagon_Intrinsic<GCCIntSuffix, 750 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], 751 intr_properties>; 752 753// tag : V6_vandqrt 754class Hexagon_custom_v16i32_v64i1i32_Intrinsic< 755 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 756 : Hexagon_NonGCC_Intrinsic< 757 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_i32_ty], 758 intr_properties>; 759 760// tag : V6_vandqrt 761class Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B< 762 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 763 : Hexagon_NonGCC_Intrinsic< 764 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_i32_ty], 765 intr_properties>; 766 767// tag : V6_vandqrt_acc 768class Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic< 769 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 770 : Hexagon_NonGCC_Intrinsic< 771 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v64i1_ty,llvm_i32_ty], 772 intr_properties>; 773 774// tag : V6_vandqrt_acc 775class Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B< 776 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 777 : Hexagon_NonGCC_Intrinsic< 778 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v128i1_ty,llvm_i32_ty], 779 intr_properties>; 780 781// tag : V6_vandvrt 782class Hexagon_custom_v64i1_v16i32i32_Intrinsic< 783 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 784 : Hexagon_NonGCC_Intrinsic< 785 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_i32_ty], 786 intr_properties>; 787 788// tag : V6_vandvrt 789class Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B< 790 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 791 : Hexagon_NonGCC_Intrinsic< 792 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_i32_ty], 793 intr_properties>; 794 795// tag : V6_vandvrt_acc 796class Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic< 797 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 798 : Hexagon_NonGCC_Intrinsic< 799 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_i32_ty], 800 intr_properties>; 801 802// tag : V6_vandvrt_acc 803class Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B< 804 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 805 : Hexagon_NonGCC_Intrinsic< 806 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_i32_ty], 807 intr_properties>; 808 809// tag : V6_vandvqv 810class Hexagon_custom_v16i32_v64i1v16i32_Intrinsic< 811 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 812 : Hexagon_NonGCC_Intrinsic< 813 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty], 814 intr_properties>; 815 816// tag : V6_vandvqv 817class Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B< 818 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 819 : Hexagon_NonGCC_Intrinsic< 820 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty], 821 intr_properties>; 822 823// tag : V6_vgtw 824class Hexagon_custom_v64i1_v16i32v16i32_Intrinsic< 825 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 826 : Hexagon_NonGCC_Intrinsic< 827 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 828 intr_properties>; 829 830// tag : V6_vgtw 831class Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B< 832 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 833 : Hexagon_NonGCC_Intrinsic< 834 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 835 intr_properties>; 836 837// tag : V6_vgtw_and 838class Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic< 839 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 840 : Hexagon_NonGCC_Intrinsic< 841 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 842 intr_properties>; 843 844// tag : V6_vgtw_and 845class Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B< 846 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 847 : Hexagon_NonGCC_Intrinsic< 848 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 849 intr_properties>; 850 851// tag : V6_pred_scalar2 852class Hexagon_custom_v64i1_i32_Intrinsic< 853 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 854 : Hexagon_NonGCC_Intrinsic< 855 [llvm_v64i1_ty], [llvm_i32_ty], 856 intr_properties>; 857 858// tag : V6_pred_scalar2 859class Hexagon_custom_v128i1_i32_Intrinsic_128B< 860 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 861 : Hexagon_NonGCC_Intrinsic< 862 [llvm_v128i1_ty], [llvm_i32_ty], 863 intr_properties>; 864 865// tag : V6_shuffeqw 866class Hexagon_custom_v64i1_v64i1v64i1_Intrinsic< 867 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 868 : Hexagon_NonGCC_Intrinsic< 869 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v64i1_ty], 870 intr_properties>; 871 872// tag : V6_shuffeqw 873class Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B< 874 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 875 : Hexagon_NonGCC_Intrinsic< 876 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v128i1_ty], 877 intr_properties>; 878 879// tag : V6_pred_not 880class Hexagon_custom_v64i1_v64i1_Intrinsic< 881 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 882 : Hexagon_NonGCC_Intrinsic< 883 [llvm_v64i1_ty], [llvm_v64i1_ty], 884 intr_properties>; 885 886// tag : V6_pred_not 887class Hexagon_custom_v128i1_v128i1_Intrinsic_128B< 888 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 889 : Hexagon_NonGCC_Intrinsic< 890 [llvm_v128i1_ty], [llvm_v128i1_ty], 891 intr_properties>; 892 893// tag : V6_vswap 894class Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic< 895 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 896 : Hexagon_NonGCC_Intrinsic< 897 [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 898 intr_properties>; 899 900// tag : V6_vswap 901class Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B< 902 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 903 : Hexagon_NonGCC_Intrinsic< 904 [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 905 intr_properties>; 906 907// tag : V6_vshuffvdd 908class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 909 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 910 : Hexagon_Intrinsic<GCCIntSuffix, 911 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 912 intr_properties>; 913 914// tag : V6_extractw 915class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix, 916 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 917 : Hexagon_Intrinsic<GCCIntSuffix, 918 [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 919 intr_properties>; 920 921// tag : V6_lvsplatw 922class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix, 923 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 924 : Hexagon_Intrinsic<GCCIntSuffix, 925 [llvm_v16i32_ty], [llvm_i32_ty], 926 intr_properties>; 927 928// tag : V6_vlutvvb_oracc 929class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 930 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 931 : Hexagon_Intrinsic<GCCIntSuffix, 932 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 933 intr_properties>; 934 935// tag : V6_vlutvwh_oracc 936class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 937 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 938 : Hexagon_Intrinsic<GCCIntSuffix, 939 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 940 intr_properties>; 941 942// tag : V6_vmpahhsat 943class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix, 944 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 945 : Hexagon_Intrinsic<GCCIntSuffix, 946 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], 947 intr_properties>; 948 949// tag : V6_vlut4 950class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix, 951 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 952 : Hexagon_Intrinsic<GCCIntSuffix, 953 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 954 intr_properties>; 955 956// tag : V6_hi 957class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, 958 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 959 : Hexagon_Intrinsic<GCCIntSuffix, 960 [llvm_v16i32_ty], [llvm_v32i32_ty], 961 intr_properties>; 962 963// tag : V6_vgathermw 964class Hexagon__ptri32i32v16i32_Intrinsic<string GCCIntSuffix, 965 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 966 : Hexagon_Intrinsic<GCCIntSuffix, 967 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 968 intr_properties>; 969 970// tag : V6_vgathermw 971class Hexagon__ptri32i32v32i32_Intrinsic<string GCCIntSuffix, 972 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 973 : Hexagon_Intrinsic<GCCIntSuffix, 974 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 975 intr_properties>; 976 977// tag : V6_vgathermhw 978class Hexagon__ptri32i32v64i32_Intrinsic<string GCCIntSuffix, 979 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 980 : Hexagon_Intrinsic<GCCIntSuffix, 981 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 982 intr_properties>; 983 984// tag : V6_vgathermwq 985class Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic< 986 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 987 : Hexagon_NonGCC_Intrinsic< 988 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 989 intr_properties>; 990 991// tag : V6_vgathermwq 992class Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B< 993 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 994 : Hexagon_NonGCC_Intrinsic< 995 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 996 intr_properties>; 997 998// tag : V6_vgathermhwq 999class Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic< 1000 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1001 : Hexagon_NonGCC_Intrinsic< 1002 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 1003 intr_properties>; 1004 1005// tag : V6_vgathermhwq 1006class Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B< 1007 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1008 : Hexagon_NonGCC_Intrinsic< 1009 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 1010 intr_properties>; 1011 1012// tag : V6_vscattermw 1013class Hexagon__i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 1014 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1015 : Hexagon_Intrinsic<GCCIntSuffix, 1016 [], [llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 1017 intr_properties>; 1018 1019// tag : V6_vscattermw 1020class Hexagon__i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 1021 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1022 : Hexagon_Intrinsic<GCCIntSuffix, 1023 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 1024 intr_properties>; 1025 1026// tag : V6_vscattermwq 1027class Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic< 1028 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1029 : Hexagon_NonGCC_Intrinsic< 1030 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 1031 intr_properties>; 1032 1033// tag : V6_vscattermwq 1034class Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B< 1035 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1036 : Hexagon_NonGCC_Intrinsic< 1037 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 1038 intr_properties>; 1039 1040// tag : V6_vscattermhw 1041class Hexagon__i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix, 1042 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1043 : Hexagon_Intrinsic<GCCIntSuffix, 1044 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 1045 intr_properties>; 1046 1047// tag : V6_vscattermhw 1048class Hexagon__i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix, 1049 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1050 : Hexagon_Intrinsic<GCCIntSuffix, 1051 [], [llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 1052 intr_properties>; 1053 1054// tag : V6_vscattermhwq 1055class Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic< 1056 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1057 : Hexagon_NonGCC_Intrinsic< 1058 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 1059 intr_properties>; 1060 1061// tag : V6_vscattermhwq 1062class Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B< 1063 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1064 : Hexagon_NonGCC_Intrinsic< 1065 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 1066 intr_properties>; 1067 1068// tag : V6_vprefixqb 1069class Hexagon_custom_v16i32_v64i1_Intrinsic< 1070 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1071 : Hexagon_NonGCC_Intrinsic< 1072 [llvm_v16i32_ty], [llvm_v64i1_ty], 1073 intr_properties>; 1074 1075// tag : V6_vprefixqb 1076class Hexagon_custom_v32i32_v128i1_Intrinsic_128B< 1077 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1078 : Hexagon_NonGCC_Intrinsic< 1079 [llvm_v32i32_ty], [llvm_v128i1_ty], 1080 intr_properties>; 1081 1082// V5 Scalar Instructions. 1083 1084def int_hexagon_C2_cmpeq : 1085Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; 1086 1087def int_hexagon_C2_cmpgt : 1088Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; 1089 1090def int_hexagon_C2_cmpgtu : 1091Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; 1092 1093def int_hexagon_C2_cmpeqp : 1094Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; 1095 1096def int_hexagon_C2_cmpgtp : 1097Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; 1098 1099def int_hexagon_C2_cmpgtup : 1100Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; 1101 1102def int_hexagon_A4_rcmpeqi : 1103Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1104 1105def int_hexagon_A4_rcmpneqi : 1106Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1107 1108def int_hexagon_A4_rcmpeq : 1109Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; 1110 1111def int_hexagon_A4_rcmpneq : 1112Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; 1113 1114def int_hexagon_C2_bitsset : 1115Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; 1116 1117def int_hexagon_C2_bitsclr : 1118Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; 1119 1120def int_hexagon_C4_nbitsset : 1121Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; 1122 1123def int_hexagon_C4_nbitsclr : 1124Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; 1125 1126def int_hexagon_C2_cmpeqi : 1127Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1128 1129def int_hexagon_C2_cmpgti : 1130Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1131 1132def int_hexagon_C2_cmpgtui : 1133Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1134 1135def int_hexagon_C2_cmpgei : 1136Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1137 1138def int_hexagon_C2_cmpgeui : 1139Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1140 1141def int_hexagon_C2_cmplt : 1142Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; 1143 1144def int_hexagon_C2_cmpltu : 1145Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; 1146 1147def int_hexagon_C2_bitsclri : 1148Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1149 1150def int_hexagon_C4_nbitsclri : 1151Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1152 1153def int_hexagon_C4_cmpneqi : 1154Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1155 1156def int_hexagon_C4_cmpltei : 1157Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1158 1159def int_hexagon_C4_cmplteui : 1160Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1161 1162def int_hexagon_C4_cmpneq : 1163Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; 1164 1165def int_hexagon_C4_cmplte : 1166Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; 1167 1168def int_hexagon_C4_cmplteu : 1169Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; 1170 1171def int_hexagon_C2_and : 1172Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; 1173 1174def int_hexagon_C2_or : 1175Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; 1176 1177def int_hexagon_C2_xor : 1178Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; 1179 1180def int_hexagon_C2_andn : 1181Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; 1182 1183def int_hexagon_C2_not : 1184Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; 1185 1186def int_hexagon_C2_orn : 1187Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; 1188 1189def int_hexagon_C4_and_and : 1190Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; 1191 1192def int_hexagon_C4_and_or : 1193Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; 1194 1195def int_hexagon_C4_or_and : 1196Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; 1197 1198def int_hexagon_C4_or_or : 1199Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; 1200 1201def int_hexagon_C4_and_andn : 1202Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; 1203 1204def int_hexagon_C4_and_orn : 1205Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; 1206 1207def int_hexagon_C4_or_andn : 1208Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; 1209 1210def int_hexagon_C4_or_orn : 1211Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; 1212 1213def int_hexagon_C2_pxfer_map : 1214Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; 1215 1216def int_hexagon_C2_any8 : 1217Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; 1218 1219def int_hexagon_C2_all8 : 1220Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; 1221 1222def int_hexagon_C2_vitpack : 1223Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; 1224 1225def int_hexagon_C2_mux : 1226Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; 1227 1228def int_hexagon_C2_muxii : 1229Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1230 1231def int_hexagon_C2_muxir : 1232Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1233 1234def int_hexagon_C2_muxri : 1235Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1236 1237def int_hexagon_C2_vmux : 1238Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; 1239 1240def int_hexagon_C2_mask : 1241Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; 1242 1243def int_hexagon_A2_vcmpbeq : 1244Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; 1245 1246def int_hexagon_A4_vcmpbeqi : 1247Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1248 1249def int_hexagon_A4_vcmpbeq_any : 1250Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; 1251 1252def int_hexagon_A2_vcmpbgtu : 1253Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; 1254 1255def int_hexagon_A4_vcmpbgtui : 1256Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1257 1258def int_hexagon_A4_vcmpbgt : 1259Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; 1260 1261def int_hexagon_A4_vcmpbgti : 1262Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1263 1264def int_hexagon_A4_cmpbeq : 1265Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; 1266 1267def int_hexagon_A4_cmpbeqi : 1268Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1269 1270def int_hexagon_A4_cmpbgtu : 1271Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; 1272 1273def int_hexagon_A4_cmpbgtui : 1274Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1275 1276def int_hexagon_A4_cmpbgt : 1277Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; 1278 1279def int_hexagon_A4_cmpbgti : 1280Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1281 1282def int_hexagon_A2_vcmpheq : 1283Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; 1284 1285def int_hexagon_A2_vcmphgt : 1286Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; 1287 1288def int_hexagon_A2_vcmphgtu : 1289Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; 1290 1291def int_hexagon_A4_vcmpheqi : 1292Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1293 1294def int_hexagon_A4_vcmphgti : 1295Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1296 1297def int_hexagon_A4_vcmphgtui : 1298Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1299 1300def int_hexagon_A4_cmpheq : 1301Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; 1302 1303def int_hexagon_A4_cmphgt : 1304Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; 1305 1306def int_hexagon_A4_cmphgtu : 1307Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; 1308 1309def int_hexagon_A4_cmpheqi : 1310Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1311 1312def int_hexagon_A4_cmphgti : 1313Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1314 1315def int_hexagon_A4_cmphgtui : 1316Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1317 1318def int_hexagon_A2_vcmpweq : 1319Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; 1320 1321def int_hexagon_A2_vcmpwgt : 1322Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; 1323 1324def int_hexagon_A2_vcmpwgtu : 1325Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; 1326 1327def int_hexagon_A4_vcmpweqi : 1328Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1329 1330def int_hexagon_A4_vcmpwgti : 1331Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1332 1333def int_hexagon_A4_vcmpwgtui : 1334Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1335 1336def int_hexagon_A4_boundscheck : 1337Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; 1338 1339def int_hexagon_A4_tlbmatch : 1340Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; 1341 1342def int_hexagon_C2_tfrpr : 1343Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; 1344 1345def int_hexagon_C2_tfrrp : 1346Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; 1347 1348def int_hexagon_C4_fastcorner9 : 1349Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; 1350 1351def int_hexagon_C4_fastcorner9_not : 1352Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; 1353 1354def int_hexagon_M2_mpy_acc_hh_s0 : 1355Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; 1356 1357def int_hexagon_M2_mpy_acc_hh_s1 : 1358Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; 1359 1360def int_hexagon_M2_mpy_acc_hl_s0 : 1361Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; 1362 1363def int_hexagon_M2_mpy_acc_hl_s1 : 1364Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; 1365 1366def int_hexagon_M2_mpy_acc_lh_s0 : 1367Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; 1368 1369def int_hexagon_M2_mpy_acc_lh_s1 : 1370Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; 1371 1372def int_hexagon_M2_mpy_acc_ll_s0 : 1373Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; 1374 1375def int_hexagon_M2_mpy_acc_ll_s1 : 1376Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; 1377 1378def int_hexagon_M2_mpy_nac_hh_s0 : 1379Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; 1380 1381def int_hexagon_M2_mpy_nac_hh_s1 : 1382Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; 1383 1384def int_hexagon_M2_mpy_nac_hl_s0 : 1385Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; 1386 1387def int_hexagon_M2_mpy_nac_hl_s1 : 1388Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; 1389 1390def int_hexagon_M2_mpy_nac_lh_s0 : 1391Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; 1392 1393def int_hexagon_M2_mpy_nac_lh_s1 : 1394Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; 1395 1396def int_hexagon_M2_mpy_nac_ll_s0 : 1397Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; 1398 1399def int_hexagon_M2_mpy_nac_ll_s1 : 1400Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; 1401 1402def int_hexagon_M2_mpy_acc_sat_hh_s0 : 1403Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; 1404 1405def int_hexagon_M2_mpy_acc_sat_hh_s1 : 1406Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; 1407 1408def int_hexagon_M2_mpy_acc_sat_hl_s0 : 1409Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; 1410 1411def int_hexagon_M2_mpy_acc_sat_hl_s1 : 1412Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; 1413 1414def int_hexagon_M2_mpy_acc_sat_lh_s0 : 1415Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; 1416 1417def int_hexagon_M2_mpy_acc_sat_lh_s1 : 1418Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; 1419 1420def int_hexagon_M2_mpy_acc_sat_ll_s0 : 1421Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; 1422 1423def int_hexagon_M2_mpy_acc_sat_ll_s1 : 1424Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; 1425 1426def int_hexagon_M2_mpy_nac_sat_hh_s0 : 1427Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; 1428 1429def int_hexagon_M2_mpy_nac_sat_hh_s1 : 1430Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; 1431 1432def int_hexagon_M2_mpy_nac_sat_hl_s0 : 1433Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; 1434 1435def int_hexagon_M2_mpy_nac_sat_hl_s1 : 1436Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; 1437 1438def int_hexagon_M2_mpy_nac_sat_lh_s0 : 1439Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; 1440 1441def int_hexagon_M2_mpy_nac_sat_lh_s1 : 1442Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; 1443 1444def int_hexagon_M2_mpy_nac_sat_ll_s0 : 1445Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; 1446 1447def int_hexagon_M2_mpy_nac_sat_ll_s1 : 1448Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; 1449 1450def int_hexagon_M2_mpy_hh_s0 : 1451Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; 1452 1453def int_hexagon_M2_mpy_hh_s1 : 1454Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; 1455 1456def int_hexagon_M2_mpy_hl_s0 : 1457Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; 1458 1459def int_hexagon_M2_mpy_hl_s1 : 1460Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; 1461 1462def int_hexagon_M2_mpy_lh_s0 : 1463Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; 1464 1465def int_hexagon_M2_mpy_lh_s1 : 1466Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; 1467 1468def int_hexagon_M2_mpy_ll_s0 : 1469Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; 1470 1471def int_hexagon_M2_mpy_ll_s1 : 1472Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; 1473 1474def int_hexagon_M2_mpy_sat_hh_s0 : 1475Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; 1476 1477def int_hexagon_M2_mpy_sat_hh_s1 : 1478Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; 1479 1480def int_hexagon_M2_mpy_sat_hl_s0 : 1481Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; 1482 1483def int_hexagon_M2_mpy_sat_hl_s1 : 1484Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; 1485 1486def int_hexagon_M2_mpy_sat_lh_s0 : 1487Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; 1488 1489def int_hexagon_M2_mpy_sat_lh_s1 : 1490Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; 1491 1492def int_hexagon_M2_mpy_sat_ll_s0 : 1493Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; 1494 1495def int_hexagon_M2_mpy_sat_ll_s1 : 1496Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; 1497 1498def int_hexagon_M2_mpy_rnd_hh_s0 : 1499Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; 1500 1501def int_hexagon_M2_mpy_rnd_hh_s1 : 1502Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; 1503 1504def int_hexagon_M2_mpy_rnd_hl_s0 : 1505Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; 1506 1507def int_hexagon_M2_mpy_rnd_hl_s1 : 1508Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; 1509 1510def int_hexagon_M2_mpy_rnd_lh_s0 : 1511Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; 1512 1513def int_hexagon_M2_mpy_rnd_lh_s1 : 1514Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; 1515 1516def int_hexagon_M2_mpy_rnd_ll_s0 : 1517Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; 1518 1519def int_hexagon_M2_mpy_rnd_ll_s1 : 1520Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; 1521 1522def int_hexagon_M2_mpy_sat_rnd_hh_s0 : 1523Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; 1524 1525def int_hexagon_M2_mpy_sat_rnd_hh_s1 : 1526Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; 1527 1528def int_hexagon_M2_mpy_sat_rnd_hl_s0 : 1529Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; 1530 1531def int_hexagon_M2_mpy_sat_rnd_hl_s1 : 1532Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; 1533 1534def int_hexagon_M2_mpy_sat_rnd_lh_s0 : 1535Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; 1536 1537def int_hexagon_M2_mpy_sat_rnd_lh_s1 : 1538Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; 1539 1540def int_hexagon_M2_mpy_sat_rnd_ll_s0 : 1541Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; 1542 1543def int_hexagon_M2_mpy_sat_rnd_ll_s1 : 1544Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; 1545 1546def int_hexagon_M2_mpyd_acc_hh_s0 : 1547Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; 1548 1549def int_hexagon_M2_mpyd_acc_hh_s1 : 1550Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; 1551 1552def int_hexagon_M2_mpyd_acc_hl_s0 : 1553Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; 1554 1555def int_hexagon_M2_mpyd_acc_hl_s1 : 1556Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; 1557 1558def int_hexagon_M2_mpyd_acc_lh_s0 : 1559Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; 1560 1561def int_hexagon_M2_mpyd_acc_lh_s1 : 1562Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; 1563 1564def int_hexagon_M2_mpyd_acc_ll_s0 : 1565Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; 1566 1567def int_hexagon_M2_mpyd_acc_ll_s1 : 1568Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; 1569 1570def int_hexagon_M2_mpyd_nac_hh_s0 : 1571Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; 1572 1573def int_hexagon_M2_mpyd_nac_hh_s1 : 1574Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; 1575 1576def int_hexagon_M2_mpyd_nac_hl_s0 : 1577Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; 1578 1579def int_hexagon_M2_mpyd_nac_hl_s1 : 1580Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; 1581 1582def int_hexagon_M2_mpyd_nac_lh_s0 : 1583Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; 1584 1585def int_hexagon_M2_mpyd_nac_lh_s1 : 1586Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; 1587 1588def int_hexagon_M2_mpyd_nac_ll_s0 : 1589Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; 1590 1591def int_hexagon_M2_mpyd_nac_ll_s1 : 1592Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; 1593 1594def int_hexagon_M2_mpyd_hh_s0 : 1595Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; 1596 1597def int_hexagon_M2_mpyd_hh_s1 : 1598Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; 1599 1600def int_hexagon_M2_mpyd_hl_s0 : 1601Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; 1602 1603def int_hexagon_M2_mpyd_hl_s1 : 1604Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; 1605 1606def int_hexagon_M2_mpyd_lh_s0 : 1607Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; 1608 1609def int_hexagon_M2_mpyd_lh_s1 : 1610Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; 1611 1612def int_hexagon_M2_mpyd_ll_s0 : 1613Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; 1614 1615def int_hexagon_M2_mpyd_ll_s1 : 1616Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; 1617 1618def int_hexagon_M2_mpyd_rnd_hh_s0 : 1619Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; 1620 1621def int_hexagon_M2_mpyd_rnd_hh_s1 : 1622Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; 1623 1624def int_hexagon_M2_mpyd_rnd_hl_s0 : 1625Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; 1626 1627def int_hexagon_M2_mpyd_rnd_hl_s1 : 1628Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; 1629 1630def int_hexagon_M2_mpyd_rnd_lh_s0 : 1631Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; 1632 1633def int_hexagon_M2_mpyd_rnd_lh_s1 : 1634Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; 1635 1636def int_hexagon_M2_mpyd_rnd_ll_s0 : 1637Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; 1638 1639def int_hexagon_M2_mpyd_rnd_ll_s1 : 1640Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; 1641 1642def int_hexagon_M2_mpyu_acc_hh_s0 : 1643Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; 1644 1645def int_hexagon_M2_mpyu_acc_hh_s1 : 1646Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; 1647 1648def int_hexagon_M2_mpyu_acc_hl_s0 : 1649Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; 1650 1651def int_hexagon_M2_mpyu_acc_hl_s1 : 1652Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; 1653 1654def int_hexagon_M2_mpyu_acc_lh_s0 : 1655Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; 1656 1657def int_hexagon_M2_mpyu_acc_lh_s1 : 1658Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; 1659 1660def int_hexagon_M2_mpyu_acc_ll_s0 : 1661Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; 1662 1663def int_hexagon_M2_mpyu_acc_ll_s1 : 1664Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; 1665 1666def int_hexagon_M2_mpyu_nac_hh_s0 : 1667Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; 1668 1669def int_hexagon_M2_mpyu_nac_hh_s1 : 1670Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; 1671 1672def int_hexagon_M2_mpyu_nac_hl_s0 : 1673Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; 1674 1675def int_hexagon_M2_mpyu_nac_hl_s1 : 1676Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; 1677 1678def int_hexagon_M2_mpyu_nac_lh_s0 : 1679Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; 1680 1681def int_hexagon_M2_mpyu_nac_lh_s1 : 1682Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; 1683 1684def int_hexagon_M2_mpyu_nac_ll_s0 : 1685Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; 1686 1687def int_hexagon_M2_mpyu_nac_ll_s1 : 1688Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; 1689 1690def int_hexagon_M2_mpyu_hh_s0 : 1691Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; 1692 1693def int_hexagon_M2_mpyu_hh_s1 : 1694Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; 1695 1696def int_hexagon_M2_mpyu_hl_s0 : 1697Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; 1698 1699def int_hexagon_M2_mpyu_hl_s1 : 1700Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; 1701 1702def int_hexagon_M2_mpyu_lh_s0 : 1703Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; 1704 1705def int_hexagon_M2_mpyu_lh_s1 : 1706Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; 1707 1708def int_hexagon_M2_mpyu_ll_s0 : 1709Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; 1710 1711def int_hexagon_M2_mpyu_ll_s1 : 1712Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; 1713 1714def int_hexagon_M2_mpyud_acc_hh_s0 : 1715Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; 1716 1717def int_hexagon_M2_mpyud_acc_hh_s1 : 1718Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; 1719 1720def int_hexagon_M2_mpyud_acc_hl_s0 : 1721Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; 1722 1723def int_hexagon_M2_mpyud_acc_hl_s1 : 1724Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; 1725 1726def int_hexagon_M2_mpyud_acc_lh_s0 : 1727Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; 1728 1729def int_hexagon_M2_mpyud_acc_lh_s1 : 1730Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; 1731 1732def int_hexagon_M2_mpyud_acc_ll_s0 : 1733Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; 1734 1735def int_hexagon_M2_mpyud_acc_ll_s1 : 1736Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; 1737 1738def int_hexagon_M2_mpyud_nac_hh_s0 : 1739Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; 1740 1741def int_hexagon_M2_mpyud_nac_hh_s1 : 1742Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; 1743 1744def int_hexagon_M2_mpyud_nac_hl_s0 : 1745Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; 1746 1747def int_hexagon_M2_mpyud_nac_hl_s1 : 1748Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; 1749 1750def int_hexagon_M2_mpyud_nac_lh_s0 : 1751Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; 1752 1753def int_hexagon_M2_mpyud_nac_lh_s1 : 1754Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; 1755 1756def int_hexagon_M2_mpyud_nac_ll_s0 : 1757Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; 1758 1759def int_hexagon_M2_mpyud_nac_ll_s1 : 1760Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; 1761 1762def int_hexagon_M2_mpyud_hh_s0 : 1763Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; 1764 1765def int_hexagon_M2_mpyud_hh_s1 : 1766Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; 1767 1768def int_hexagon_M2_mpyud_hl_s0 : 1769Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; 1770 1771def int_hexagon_M2_mpyud_hl_s1 : 1772Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; 1773 1774def int_hexagon_M2_mpyud_lh_s0 : 1775Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; 1776 1777def int_hexagon_M2_mpyud_lh_s1 : 1778Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; 1779 1780def int_hexagon_M2_mpyud_ll_s0 : 1781Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; 1782 1783def int_hexagon_M2_mpyud_ll_s1 : 1784Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; 1785 1786def int_hexagon_M2_mpysmi : 1787Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1788 1789def int_hexagon_M2_macsip : 1790Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1791 1792def int_hexagon_M2_macsin : 1793Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1794 1795def int_hexagon_M2_dpmpyss_s0 : 1796Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; 1797 1798def int_hexagon_M2_dpmpyss_acc_s0 : 1799Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; 1800 1801def int_hexagon_M2_dpmpyss_nac_s0 : 1802Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; 1803 1804def int_hexagon_M2_dpmpyuu_s0 : 1805Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; 1806 1807def int_hexagon_M2_dpmpyuu_acc_s0 : 1808Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; 1809 1810def int_hexagon_M2_dpmpyuu_nac_s0 : 1811Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; 1812 1813def int_hexagon_M2_mpy_up : 1814Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; 1815 1816def int_hexagon_M2_mpy_up_s1 : 1817Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; 1818 1819def int_hexagon_M2_mpy_up_s1_sat : 1820Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; 1821 1822def int_hexagon_M2_mpyu_up : 1823Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; 1824 1825def int_hexagon_M2_mpysu_up : 1826Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; 1827 1828def int_hexagon_M2_dpmpyss_rnd_s0 : 1829Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; 1830 1831def int_hexagon_M4_mac_up_s1_sat : 1832Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; 1833 1834def int_hexagon_M4_nac_up_s1_sat : 1835Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; 1836 1837def int_hexagon_M2_mpyi : 1838Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; 1839 1840def int_hexagon_M2_mpyui : 1841Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; 1842 1843def int_hexagon_M2_maci : 1844Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; 1845 1846def int_hexagon_M2_acci : 1847Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; 1848 1849def int_hexagon_M2_accii : 1850Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1851 1852def int_hexagon_M2_nacci : 1853Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; 1854 1855def int_hexagon_M2_naccii : 1856Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1857 1858def int_hexagon_M2_subacc : 1859Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; 1860 1861def int_hexagon_M4_mpyrr_addr : 1862Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; 1863 1864def int_hexagon_M4_mpyri_addr_u2 : 1865Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1866 1867def int_hexagon_M4_mpyri_addr : 1868Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1869 1870def int_hexagon_M4_mpyri_addi : 1871Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 1872 1873def int_hexagon_M4_mpyrr_addi : 1874Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1875 1876def int_hexagon_M2_vmpy2s_s0 : 1877Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; 1878 1879def int_hexagon_M2_vmpy2s_s1 : 1880Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; 1881 1882def int_hexagon_M2_vmac2s_s0 : 1883Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; 1884 1885def int_hexagon_M2_vmac2s_s1 : 1886Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; 1887 1888def int_hexagon_M2_vmpy2su_s0 : 1889Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; 1890 1891def int_hexagon_M2_vmpy2su_s1 : 1892Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; 1893 1894def int_hexagon_M2_vmac2su_s0 : 1895Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; 1896 1897def int_hexagon_M2_vmac2su_s1 : 1898Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; 1899 1900def int_hexagon_M2_vmpy2s_s0pack : 1901Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; 1902 1903def int_hexagon_M2_vmpy2s_s1pack : 1904Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; 1905 1906def int_hexagon_M2_vmac2 : 1907Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; 1908 1909def int_hexagon_M2_vmpy2es_s0 : 1910Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; 1911 1912def int_hexagon_M2_vmpy2es_s1 : 1913Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; 1914 1915def int_hexagon_M2_vmac2es_s0 : 1916Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; 1917 1918def int_hexagon_M2_vmac2es_s1 : 1919Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; 1920 1921def int_hexagon_M2_vmac2es : 1922Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; 1923 1924def int_hexagon_M2_vrmac_s0 : 1925Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; 1926 1927def int_hexagon_M2_vrmpy_s0 : 1928Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; 1929 1930def int_hexagon_M2_vdmpyrs_s0 : 1931Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; 1932 1933def int_hexagon_M2_vdmpyrs_s1 : 1934Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; 1935 1936def int_hexagon_M5_vrmpybuu : 1937Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; 1938 1939def int_hexagon_M5_vrmacbuu : 1940Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; 1941 1942def int_hexagon_M5_vrmpybsu : 1943Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; 1944 1945def int_hexagon_M5_vrmacbsu : 1946Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; 1947 1948def int_hexagon_M5_vmpybuu : 1949Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; 1950 1951def int_hexagon_M5_vmpybsu : 1952Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; 1953 1954def int_hexagon_M5_vmacbuu : 1955Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; 1956 1957def int_hexagon_M5_vmacbsu : 1958Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; 1959 1960def int_hexagon_M5_vdmpybsu : 1961Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; 1962 1963def int_hexagon_M5_vdmacbsu : 1964Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; 1965 1966def int_hexagon_M2_vdmacs_s0 : 1967Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; 1968 1969def int_hexagon_M2_vdmacs_s1 : 1970Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; 1971 1972def int_hexagon_M2_vdmpys_s0 : 1973Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; 1974 1975def int_hexagon_M2_vdmpys_s1 : 1976Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; 1977 1978def int_hexagon_M2_cmpyrs_s0 : 1979Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; 1980 1981def int_hexagon_M2_cmpyrs_s1 : 1982Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; 1983 1984def int_hexagon_M2_cmpyrsc_s0 : 1985Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; 1986 1987def int_hexagon_M2_cmpyrsc_s1 : 1988Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; 1989 1990def int_hexagon_M2_cmacs_s0 : 1991Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; 1992 1993def int_hexagon_M2_cmacs_s1 : 1994Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">; 1995 1996def int_hexagon_M2_cmacsc_s0 : 1997Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; 1998 1999def int_hexagon_M2_cmacsc_s1 : 2000Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; 2001 2002def int_hexagon_M2_cmpys_s0 : 2003Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; 2004 2005def int_hexagon_M2_cmpys_s1 : 2006Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">; 2007 2008def int_hexagon_M2_cmpysc_s0 : 2009Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">; 2010 2011def int_hexagon_M2_cmpysc_s1 : 2012Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">; 2013 2014def int_hexagon_M2_cnacs_s0 : 2015Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">; 2016 2017def int_hexagon_M2_cnacs_s1 : 2018Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">; 2019 2020def int_hexagon_M2_cnacsc_s0 : 2021Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; 2022 2023def int_hexagon_M2_cnacsc_s1 : 2024Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; 2025 2026def int_hexagon_M2_vrcmpys_s1 : 2027Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; 2028 2029def int_hexagon_M2_vrcmpys_acc_s1 : 2030Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; 2031 2032def int_hexagon_M2_vrcmpys_s1rp : 2033Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; 2034 2035def int_hexagon_M2_mmacls_s0 : 2036Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; 2037 2038def int_hexagon_M2_mmacls_s1 : 2039Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; 2040 2041def int_hexagon_M2_mmachs_s0 : 2042Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; 2043 2044def int_hexagon_M2_mmachs_s1 : 2045Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; 2046 2047def int_hexagon_M2_mmpyl_s0 : 2048Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; 2049 2050def int_hexagon_M2_mmpyl_s1 : 2051Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; 2052 2053def int_hexagon_M2_mmpyh_s0 : 2054Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; 2055 2056def int_hexagon_M2_mmpyh_s1 : 2057Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; 2058 2059def int_hexagon_M2_mmacls_rs0 : 2060Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; 2061 2062def int_hexagon_M2_mmacls_rs1 : 2063Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; 2064 2065def int_hexagon_M2_mmachs_rs0 : 2066Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; 2067 2068def int_hexagon_M2_mmachs_rs1 : 2069Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; 2070 2071def int_hexagon_M2_mmpyl_rs0 : 2072Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; 2073 2074def int_hexagon_M2_mmpyl_rs1 : 2075Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; 2076 2077def int_hexagon_M2_mmpyh_rs0 : 2078Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; 2079 2080def int_hexagon_M2_mmpyh_rs1 : 2081Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; 2082 2083def int_hexagon_M4_vrmpyeh_s0 : 2084Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; 2085 2086def int_hexagon_M4_vrmpyeh_s1 : 2087Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; 2088 2089def int_hexagon_M4_vrmpyeh_acc_s0 : 2090Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; 2091 2092def int_hexagon_M4_vrmpyeh_acc_s1 : 2093Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; 2094 2095def int_hexagon_M4_vrmpyoh_s0 : 2096Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; 2097 2098def int_hexagon_M4_vrmpyoh_s1 : 2099Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; 2100 2101def int_hexagon_M4_vrmpyoh_acc_s0 : 2102Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; 2103 2104def int_hexagon_M4_vrmpyoh_acc_s1 : 2105Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; 2106 2107def int_hexagon_M2_hmmpyl_rs1 : 2108Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; 2109 2110def int_hexagon_M2_hmmpyh_rs1 : 2111Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; 2112 2113def int_hexagon_M2_hmmpyl_s1 : 2114Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; 2115 2116def int_hexagon_M2_hmmpyh_s1 : 2117Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; 2118 2119def int_hexagon_M2_mmaculs_s0 : 2120Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; 2121 2122def int_hexagon_M2_mmaculs_s1 : 2123Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; 2124 2125def int_hexagon_M2_mmacuhs_s0 : 2126Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; 2127 2128def int_hexagon_M2_mmacuhs_s1 : 2129Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; 2130 2131def int_hexagon_M2_mmpyul_s0 : 2132Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; 2133 2134def int_hexagon_M2_mmpyul_s1 : 2135Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; 2136 2137def int_hexagon_M2_mmpyuh_s0 : 2138Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; 2139 2140def int_hexagon_M2_mmpyuh_s1 : 2141Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; 2142 2143def int_hexagon_M2_mmaculs_rs0 : 2144Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; 2145 2146def int_hexagon_M2_mmaculs_rs1 : 2147Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; 2148 2149def int_hexagon_M2_mmacuhs_rs0 : 2150Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; 2151 2152def int_hexagon_M2_mmacuhs_rs1 : 2153Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; 2154 2155def int_hexagon_M2_mmpyul_rs0 : 2156Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; 2157 2158def int_hexagon_M2_mmpyul_rs1 : 2159Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; 2160 2161def int_hexagon_M2_mmpyuh_rs0 : 2162Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; 2163 2164def int_hexagon_M2_mmpyuh_rs1 : 2165Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; 2166 2167def int_hexagon_M2_vrcmaci_s0 : 2168Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; 2169 2170def int_hexagon_M2_vrcmacr_s0 : 2171Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; 2172 2173def int_hexagon_M2_vrcmaci_s0c : 2174Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; 2175 2176def int_hexagon_M2_vrcmacr_s0c : 2177Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; 2178 2179def int_hexagon_M2_cmaci_s0 : 2180Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; 2181 2182def int_hexagon_M2_cmacr_s0 : 2183Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; 2184 2185def int_hexagon_M2_vrcmpyi_s0 : 2186Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; 2187 2188def int_hexagon_M2_vrcmpyr_s0 : 2189Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; 2190 2191def int_hexagon_M2_vrcmpyi_s0c : 2192Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; 2193 2194def int_hexagon_M2_vrcmpyr_s0c : 2195Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; 2196 2197def int_hexagon_M2_cmpyi_s0 : 2198Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; 2199 2200def int_hexagon_M2_cmpyr_s0 : 2201Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; 2202 2203def int_hexagon_M4_cmpyi_wh : 2204Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; 2205 2206def int_hexagon_M4_cmpyr_wh : 2207Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; 2208 2209def int_hexagon_M4_cmpyi_whc : 2210Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; 2211 2212def int_hexagon_M4_cmpyr_whc : 2213Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; 2214 2215def int_hexagon_M2_vcmpy_s0_sat_i : 2216Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; 2217 2218def int_hexagon_M2_vcmpy_s0_sat_r : 2219Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; 2220 2221def int_hexagon_M2_vcmpy_s1_sat_i : 2222Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; 2223 2224def int_hexagon_M2_vcmpy_s1_sat_r : 2225Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; 2226 2227def int_hexagon_M2_vcmac_s0_sat_i : 2228Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; 2229 2230def int_hexagon_M2_vcmac_s0_sat_r : 2231Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; 2232 2233def int_hexagon_S2_vcrotate : 2234Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; 2235 2236def int_hexagon_S4_vrcrotate_acc : 2237Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 2238 2239def int_hexagon_S4_vrcrotate : 2240Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2241 2242def int_hexagon_S2_vcnegh : 2243Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; 2244 2245def int_hexagon_S2_vrcnegh : 2246Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; 2247 2248def int_hexagon_M4_pmpyw : 2249Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; 2250 2251def int_hexagon_M4_vpmpyh : 2252Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; 2253 2254def int_hexagon_M4_pmpyw_acc : 2255Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; 2256 2257def int_hexagon_M4_vpmpyh_acc : 2258Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; 2259 2260def int_hexagon_A2_add : 2261Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; 2262 2263def int_hexagon_A2_sub : 2264Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; 2265 2266def int_hexagon_A2_addsat : 2267Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; 2268 2269def int_hexagon_A2_subsat : 2270Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; 2271 2272def int_hexagon_A2_addi : 2273Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2274 2275def int_hexagon_A2_addh_l16_ll : 2276Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; 2277 2278def int_hexagon_A2_addh_l16_hl : 2279Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; 2280 2281def int_hexagon_A2_addh_l16_sat_ll : 2282Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; 2283 2284def int_hexagon_A2_addh_l16_sat_hl : 2285Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; 2286 2287def int_hexagon_A2_subh_l16_ll : 2288Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; 2289 2290def int_hexagon_A2_subh_l16_hl : 2291Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; 2292 2293def int_hexagon_A2_subh_l16_sat_ll : 2294Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; 2295 2296def int_hexagon_A2_subh_l16_sat_hl : 2297Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; 2298 2299def int_hexagon_A2_addh_h16_ll : 2300Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; 2301 2302def int_hexagon_A2_addh_h16_lh : 2303Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; 2304 2305def int_hexagon_A2_addh_h16_hl : 2306Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; 2307 2308def int_hexagon_A2_addh_h16_hh : 2309Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; 2310 2311def int_hexagon_A2_addh_h16_sat_ll : 2312Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; 2313 2314def int_hexagon_A2_addh_h16_sat_lh : 2315Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; 2316 2317def int_hexagon_A2_addh_h16_sat_hl : 2318Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; 2319 2320def int_hexagon_A2_addh_h16_sat_hh : 2321Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; 2322 2323def int_hexagon_A2_subh_h16_ll : 2324Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; 2325 2326def int_hexagon_A2_subh_h16_lh : 2327Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; 2328 2329def int_hexagon_A2_subh_h16_hl : 2330Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; 2331 2332def int_hexagon_A2_subh_h16_hh : 2333Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; 2334 2335def int_hexagon_A2_subh_h16_sat_ll : 2336Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; 2337 2338def int_hexagon_A2_subh_h16_sat_lh : 2339Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; 2340 2341def int_hexagon_A2_subh_h16_sat_hl : 2342Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; 2343 2344def int_hexagon_A2_subh_h16_sat_hh : 2345Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; 2346 2347def int_hexagon_A2_aslh : 2348Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; 2349 2350def int_hexagon_A2_asrh : 2351Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; 2352 2353def int_hexagon_A2_addp : 2354Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; 2355 2356def int_hexagon_A2_addpsat : 2357Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; 2358 2359def int_hexagon_A2_addsp : 2360Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; 2361 2362def int_hexagon_A2_subp : 2363Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; 2364 2365def int_hexagon_A2_neg : 2366Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; 2367 2368def int_hexagon_A2_negsat : 2369Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; 2370 2371def int_hexagon_A2_abs : 2372Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; 2373 2374def int_hexagon_A2_abssat : 2375Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; 2376 2377def int_hexagon_A2_vconj : 2378Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; 2379 2380def int_hexagon_A2_negp : 2381Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; 2382 2383def int_hexagon_A2_absp : 2384Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; 2385 2386def int_hexagon_A2_max : 2387Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; 2388 2389def int_hexagon_A2_maxu : 2390Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; 2391 2392def int_hexagon_A2_min : 2393Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; 2394 2395def int_hexagon_A2_minu : 2396Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; 2397 2398def int_hexagon_A2_maxp : 2399Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; 2400 2401def int_hexagon_A2_maxup : 2402Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; 2403 2404def int_hexagon_A2_minp : 2405Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; 2406 2407def int_hexagon_A2_minup : 2408Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; 2409 2410def int_hexagon_A2_tfr : 2411Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; 2412 2413def int_hexagon_A2_tfrsi : 2414Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2415 2416def int_hexagon_A2_tfrp : 2417Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; 2418 2419def int_hexagon_A2_tfrpi : 2420Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2421 2422def int_hexagon_A2_zxtb : 2423Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; 2424 2425def int_hexagon_A2_sxtb : 2426Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; 2427 2428def int_hexagon_A2_zxth : 2429Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; 2430 2431def int_hexagon_A2_sxth : 2432Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; 2433 2434def int_hexagon_A2_combinew : 2435Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; 2436 2437def int_hexagon_A4_combineri : 2438Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2439 2440def int_hexagon_A4_combineir : 2441Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2442 2443def int_hexagon_A2_combineii : 2444Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 2445 2446def int_hexagon_A2_combine_hh : 2447Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; 2448 2449def int_hexagon_A2_combine_hl : 2450Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; 2451 2452def int_hexagon_A2_combine_lh : 2453Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; 2454 2455def int_hexagon_A2_combine_ll : 2456Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; 2457 2458def int_hexagon_A2_tfril : 2459Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2460 2461def int_hexagon_A2_tfrih : 2462Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2463 2464def int_hexagon_A2_and : 2465Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; 2466 2467def int_hexagon_A2_or : 2468Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; 2469 2470def int_hexagon_A2_xor : 2471Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; 2472 2473def int_hexagon_A2_not : 2474Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; 2475 2476def int_hexagon_M2_xor_xacc : 2477Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; 2478 2479def int_hexagon_M4_xor_xacc : 2480Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; 2481 2482def int_hexagon_A4_andn : 2483Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; 2484 2485def int_hexagon_A4_orn : 2486Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; 2487 2488def int_hexagon_A4_andnp : 2489Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; 2490 2491def int_hexagon_A4_ornp : 2492Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; 2493 2494def int_hexagon_S4_addaddi : 2495Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2496 2497def int_hexagon_S4_subaddi : 2498Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2499 2500def int_hexagon_M4_and_and : 2501Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; 2502 2503def int_hexagon_M4_and_andn : 2504Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">; 2505 2506def int_hexagon_M4_and_or : 2507Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; 2508 2509def int_hexagon_M4_and_xor : 2510Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; 2511 2512def int_hexagon_M4_or_and : 2513Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; 2514 2515def int_hexagon_M4_or_andn : 2516Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">; 2517 2518def int_hexagon_M4_or_or : 2519Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; 2520 2521def int_hexagon_M4_or_xor : 2522Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; 2523 2524def int_hexagon_S4_or_andix : 2525Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2526 2527def int_hexagon_S4_or_andi : 2528Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2529 2530def int_hexagon_S4_or_ori : 2531Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2532 2533def int_hexagon_M4_xor_and : 2534Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; 2535 2536def int_hexagon_M4_xor_or : 2537Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; 2538 2539def int_hexagon_M4_xor_andn : 2540Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; 2541 2542def int_hexagon_A2_subri : 2543Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2544 2545def int_hexagon_A2_andir : 2546Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2547 2548def int_hexagon_A2_orir : 2549Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2550 2551def int_hexagon_A2_andp : 2552Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; 2553 2554def int_hexagon_A2_orp : 2555Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; 2556 2557def int_hexagon_A2_xorp : 2558Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; 2559 2560def int_hexagon_A2_notp : 2561Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; 2562 2563def int_hexagon_A2_sxtw : 2564Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; 2565 2566def int_hexagon_A2_sat : 2567Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; 2568 2569def int_hexagon_A2_roundsat : 2570Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; 2571 2572def int_hexagon_A2_sath : 2573Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; 2574 2575def int_hexagon_A2_satuh : 2576Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; 2577 2578def int_hexagon_A2_satub : 2579Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; 2580 2581def int_hexagon_A2_satb : 2582Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; 2583 2584def int_hexagon_A2_vaddub : 2585Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; 2586 2587def int_hexagon_A2_vaddb_map : 2588Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; 2589 2590def int_hexagon_A2_vaddubs : 2591Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; 2592 2593def int_hexagon_A2_vaddh : 2594Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; 2595 2596def int_hexagon_A2_vaddhs : 2597Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; 2598 2599def int_hexagon_A2_vadduhs : 2600Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; 2601 2602def int_hexagon_A5_vaddhubs : 2603Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; 2604 2605def int_hexagon_A2_vaddw : 2606Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; 2607 2608def int_hexagon_A2_vaddws : 2609Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; 2610 2611def int_hexagon_S4_vxaddsubw : 2612Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; 2613 2614def int_hexagon_S4_vxsubaddw : 2615Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; 2616 2617def int_hexagon_S4_vxaddsubh : 2618Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; 2619 2620def int_hexagon_S4_vxsubaddh : 2621Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; 2622 2623def int_hexagon_S4_vxaddsubhr : 2624Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; 2625 2626def int_hexagon_S4_vxsubaddhr : 2627Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; 2628 2629def int_hexagon_A2_svavgh : 2630Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; 2631 2632def int_hexagon_A2_svavghs : 2633Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; 2634 2635def int_hexagon_A2_svnavgh : 2636Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; 2637 2638def int_hexagon_A2_svaddh : 2639Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; 2640 2641def int_hexagon_A2_svaddhs : 2642Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; 2643 2644def int_hexagon_A2_svadduhs : 2645Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; 2646 2647def int_hexagon_A2_svsubh : 2648Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; 2649 2650def int_hexagon_A2_svsubhs : 2651Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; 2652 2653def int_hexagon_A2_svsubuhs : 2654Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; 2655 2656def int_hexagon_A2_vraddub : 2657Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; 2658 2659def int_hexagon_A2_vraddub_acc : 2660Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; 2661 2662def int_hexagon_M2_vraddh : 2663Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; 2664 2665def int_hexagon_M2_vradduh : 2666Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; 2667 2668def int_hexagon_A2_vsubub : 2669Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; 2670 2671def int_hexagon_A2_vsubb_map : 2672Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; 2673 2674def int_hexagon_A2_vsububs : 2675Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; 2676 2677def int_hexagon_A2_vsubh : 2678Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; 2679 2680def int_hexagon_A2_vsubhs : 2681Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; 2682 2683def int_hexagon_A2_vsubuhs : 2684Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; 2685 2686def int_hexagon_A2_vsubw : 2687Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; 2688 2689def int_hexagon_A2_vsubws : 2690Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; 2691 2692def int_hexagon_A2_vabsh : 2693Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; 2694 2695def int_hexagon_A2_vabshsat : 2696Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; 2697 2698def int_hexagon_A2_vabsw : 2699Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; 2700 2701def int_hexagon_A2_vabswsat : 2702Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; 2703 2704def int_hexagon_M2_vabsdiffw : 2705Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; 2706 2707def int_hexagon_M2_vabsdiffh : 2708Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; 2709 2710def int_hexagon_A2_vrsadub : 2711Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; 2712 2713def int_hexagon_A2_vrsadub_acc : 2714Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; 2715 2716def int_hexagon_A2_vavgub : 2717Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; 2718 2719def int_hexagon_A2_vavguh : 2720Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; 2721 2722def int_hexagon_A2_vavgh : 2723Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; 2724 2725def int_hexagon_A2_vnavgh : 2726Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; 2727 2728def int_hexagon_A2_vavgw : 2729Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; 2730 2731def int_hexagon_A2_vnavgw : 2732Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; 2733 2734def int_hexagon_A2_vavgwr : 2735Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; 2736 2737def int_hexagon_A2_vnavgwr : 2738Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; 2739 2740def int_hexagon_A2_vavgwcr : 2741Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; 2742 2743def int_hexagon_A2_vnavgwcr : 2744Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; 2745 2746def int_hexagon_A2_vavghcr : 2747Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; 2748 2749def int_hexagon_A2_vnavghcr : 2750Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; 2751 2752def int_hexagon_A2_vavguw : 2753Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; 2754 2755def int_hexagon_A2_vavguwr : 2756Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; 2757 2758def int_hexagon_A2_vavgubr : 2759Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; 2760 2761def int_hexagon_A2_vavguhr : 2762Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; 2763 2764def int_hexagon_A2_vavghr : 2765Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; 2766 2767def int_hexagon_A2_vnavghr : 2768Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; 2769 2770def int_hexagon_A4_round_ri : 2771Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2772 2773def int_hexagon_A4_round_rr : 2774Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; 2775 2776def int_hexagon_A4_round_ri_sat : 2777Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2778 2779def int_hexagon_A4_round_rr_sat : 2780Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; 2781 2782def int_hexagon_A4_cround_ri : 2783Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2784 2785def int_hexagon_A4_cround_rr : 2786Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; 2787 2788def int_hexagon_A4_vrminh : 2789Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; 2790 2791def int_hexagon_A4_vrmaxh : 2792Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; 2793 2794def int_hexagon_A4_vrminuh : 2795Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; 2796 2797def int_hexagon_A4_vrmaxuh : 2798Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; 2799 2800def int_hexagon_A4_vrminw : 2801Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; 2802 2803def int_hexagon_A4_vrmaxw : 2804Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; 2805 2806def int_hexagon_A4_vrminuw : 2807Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; 2808 2809def int_hexagon_A4_vrmaxuw : 2810Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; 2811 2812def int_hexagon_A2_vminb : 2813Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; 2814 2815def int_hexagon_A2_vmaxb : 2816Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; 2817 2818def int_hexagon_A2_vminub : 2819Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; 2820 2821def int_hexagon_A2_vmaxub : 2822Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; 2823 2824def int_hexagon_A2_vminh : 2825Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; 2826 2827def int_hexagon_A2_vmaxh : 2828Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; 2829 2830def int_hexagon_A2_vminuh : 2831Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; 2832 2833def int_hexagon_A2_vmaxuh : 2834Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; 2835 2836def int_hexagon_A2_vminw : 2837Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; 2838 2839def int_hexagon_A2_vmaxw : 2840Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; 2841 2842def int_hexagon_A2_vminuw : 2843Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; 2844 2845def int_hexagon_A2_vmaxuw : 2846Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; 2847 2848def int_hexagon_A4_modwrapu : 2849Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; 2850 2851def int_hexagon_F2_sfadd : 2852Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>; 2853 2854def int_hexagon_F2_sfsub : 2855Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>; 2856 2857def int_hexagon_F2_sfmpy : 2858Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>; 2859 2860def int_hexagon_F2_sffma : 2861Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>; 2862 2863def int_hexagon_F2_sffma_sc : 2864Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>; 2865 2866def int_hexagon_F2_sffms : 2867Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>; 2868 2869def int_hexagon_F2_sffma_lib : 2870Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>; 2871 2872def int_hexagon_F2_sffms_lib : 2873Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>; 2874 2875def int_hexagon_F2_sfcmpeq : 2876Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>; 2877 2878def int_hexagon_F2_sfcmpgt : 2879Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>; 2880 2881def int_hexagon_F2_sfcmpge : 2882Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>; 2883 2884def int_hexagon_F2_sfcmpuo : 2885Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>; 2886 2887def int_hexagon_F2_sfmax : 2888Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>; 2889 2890def int_hexagon_F2_sfmin : 2891Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>; 2892 2893def int_hexagon_F2_sfclass : 2894Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 2895 2896def int_hexagon_F2_sfimm_p : 2897Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 2898 2899def int_hexagon_F2_sfimm_n : 2900Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 2901 2902def int_hexagon_F2_sffixupn : 2903Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>; 2904 2905def int_hexagon_F2_sffixupd : 2906Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>; 2907 2908def int_hexagon_F2_sffixupr : 2909Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>; 2910 2911def int_hexagon_F2_dfcmpeq : 2912Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>; 2913 2914def int_hexagon_F2_dfcmpgt : 2915Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>; 2916 2917def int_hexagon_F2_dfcmpge : 2918Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>; 2919 2920def int_hexagon_F2_dfcmpuo : 2921Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>; 2922 2923def int_hexagon_F2_dfclass : 2924Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 2925 2926def int_hexagon_F2_dfimm_p : 2927Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 2928 2929def int_hexagon_F2_dfimm_n : 2930Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 2931 2932def int_hexagon_F2_conv_sf2df : 2933Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; 2934 2935def int_hexagon_F2_conv_df2sf : 2936Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; 2937 2938def int_hexagon_F2_conv_uw2sf : 2939Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; 2940 2941def int_hexagon_F2_conv_uw2df : 2942Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; 2943 2944def int_hexagon_F2_conv_w2sf : 2945Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; 2946 2947def int_hexagon_F2_conv_w2df : 2948Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; 2949 2950def int_hexagon_F2_conv_ud2sf : 2951Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; 2952 2953def int_hexagon_F2_conv_ud2df : 2954Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; 2955 2956def int_hexagon_F2_conv_d2sf : 2957Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; 2958 2959def int_hexagon_F2_conv_d2df : 2960Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; 2961 2962def int_hexagon_F2_conv_sf2uw : 2963Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; 2964 2965def int_hexagon_F2_conv_sf2w : 2966Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; 2967 2968def int_hexagon_F2_conv_sf2ud : 2969Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; 2970 2971def int_hexagon_F2_conv_sf2d : 2972Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; 2973 2974def int_hexagon_F2_conv_df2uw : 2975Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; 2976 2977def int_hexagon_F2_conv_df2w : 2978Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; 2979 2980def int_hexagon_F2_conv_df2ud : 2981Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; 2982 2983def int_hexagon_F2_conv_df2d : 2984Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; 2985 2986def int_hexagon_F2_conv_sf2uw_chop : 2987Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; 2988 2989def int_hexagon_F2_conv_sf2w_chop : 2990Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; 2991 2992def int_hexagon_F2_conv_sf2ud_chop : 2993Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; 2994 2995def int_hexagon_F2_conv_sf2d_chop : 2996Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; 2997 2998def int_hexagon_F2_conv_df2uw_chop : 2999Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; 3000 3001def int_hexagon_F2_conv_df2w_chop : 3002Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; 3003 3004def int_hexagon_F2_conv_df2ud_chop : 3005Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; 3006 3007def int_hexagon_F2_conv_df2d_chop : 3008Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; 3009 3010def int_hexagon_S2_asr_r_r : 3011Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; 3012 3013def int_hexagon_S2_asl_r_r : 3014Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; 3015 3016def int_hexagon_S2_lsr_r_r : 3017Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; 3018 3019def int_hexagon_S2_lsl_r_r : 3020Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; 3021 3022def int_hexagon_S2_asr_r_p : 3023Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; 3024 3025def int_hexagon_S2_asl_r_p : 3026Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; 3027 3028def int_hexagon_S2_lsr_r_p : 3029Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; 3030 3031def int_hexagon_S2_lsl_r_p : 3032Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; 3033 3034def int_hexagon_S2_asr_r_r_acc : 3035Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; 3036 3037def int_hexagon_S2_asl_r_r_acc : 3038Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; 3039 3040def int_hexagon_S2_lsr_r_r_acc : 3041Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; 3042 3043def int_hexagon_S2_lsl_r_r_acc : 3044Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; 3045 3046def int_hexagon_S2_asr_r_p_acc : 3047Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; 3048 3049def int_hexagon_S2_asl_r_p_acc : 3050Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; 3051 3052def int_hexagon_S2_lsr_r_p_acc : 3053Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; 3054 3055def int_hexagon_S2_lsl_r_p_acc : 3056Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; 3057 3058def int_hexagon_S2_asr_r_r_nac : 3059Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; 3060 3061def int_hexagon_S2_asl_r_r_nac : 3062Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; 3063 3064def int_hexagon_S2_lsr_r_r_nac : 3065Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; 3066 3067def int_hexagon_S2_lsl_r_r_nac : 3068Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; 3069 3070def int_hexagon_S2_asr_r_p_nac : 3071Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; 3072 3073def int_hexagon_S2_asl_r_p_nac : 3074Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; 3075 3076def int_hexagon_S2_lsr_r_p_nac : 3077Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; 3078 3079def int_hexagon_S2_lsl_r_p_nac : 3080Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; 3081 3082def int_hexagon_S2_asr_r_r_and : 3083Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; 3084 3085def int_hexagon_S2_asl_r_r_and : 3086Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; 3087 3088def int_hexagon_S2_lsr_r_r_and : 3089Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; 3090 3091def int_hexagon_S2_lsl_r_r_and : 3092Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; 3093 3094def int_hexagon_S2_asr_r_r_or : 3095Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; 3096 3097def int_hexagon_S2_asl_r_r_or : 3098Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; 3099 3100def int_hexagon_S2_lsr_r_r_or : 3101Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; 3102 3103def int_hexagon_S2_lsl_r_r_or : 3104Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; 3105 3106def int_hexagon_S2_asr_r_p_and : 3107Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; 3108 3109def int_hexagon_S2_asl_r_p_and : 3110Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; 3111 3112def int_hexagon_S2_lsr_r_p_and : 3113Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; 3114 3115def int_hexagon_S2_lsl_r_p_and : 3116Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; 3117 3118def int_hexagon_S2_asr_r_p_or : 3119Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; 3120 3121def int_hexagon_S2_asl_r_p_or : 3122Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; 3123 3124def int_hexagon_S2_lsr_r_p_or : 3125Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; 3126 3127def int_hexagon_S2_lsl_r_p_or : 3128Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; 3129 3130def int_hexagon_S2_asr_r_p_xor : 3131Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; 3132 3133def int_hexagon_S2_asl_r_p_xor : 3134Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; 3135 3136def int_hexagon_S2_lsr_r_p_xor : 3137Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; 3138 3139def int_hexagon_S2_lsl_r_p_xor : 3140Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; 3141 3142def int_hexagon_S2_asr_r_r_sat : 3143Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; 3144 3145def int_hexagon_S2_asl_r_r_sat : 3146Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; 3147 3148def int_hexagon_S2_asr_i_r : 3149Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3150 3151def int_hexagon_S2_lsr_i_r : 3152Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3153 3154def int_hexagon_S2_asl_i_r : 3155Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3156 3157def int_hexagon_S2_asr_i_p : 3158Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3159 3160def int_hexagon_S2_lsr_i_p : 3161Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3162 3163def int_hexagon_S2_asl_i_p : 3164Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3165 3166def int_hexagon_S2_asr_i_r_acc : 3167Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3168 3169def int_hexagon_S2_lsr_i_r_acc : 3170Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3171 3172def int_hexagon_S2_asl_i_r_acc : 3173Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3174 3175def int_hexagon_S2_asr_i_p_acc : 3176Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3177 3178def int_hexagon_S2_lsr_i_p_acc : 3179Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3180 3181def int_hexagon_S2_asl_i_p_acc : 3182Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3183 3184def int_hexagon_S2_asr_i_r_nac : 3185Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3186 3187def int_hexagon_S2_lsr_i_r_nac : 3188Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3189 3190def int_hexagon_S2_asl_i_r_nac : 3191Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3192 3193def int_hexagon_S2_asr_i_p_nac : 3194Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3195 3196def int_hexagon_S2_lsr_i_p_nac : 3197Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3198 3199def int_hexagon_S2_asl_i_p_nac : 3200Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3201 3202def int_hexagon_S2_lsr_i_r_xacc : 3203Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3204 3205def int_hexagon_S2_asl_i_r_xacc : 3206Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3207 3208def int_hexagon_S2_lsr_i_p_xacc : 3209Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3210 3211def int_hexagon_S2_asl_i_p_xacc : 3212Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3213 3214def int_hexagon_S2_asr_i_r_and : 3215Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3216 3217def int_hexagon_S2_lsr_i_r_and : 3218Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3219 3220def int_hexagon_S2_asl_i_r_and : 3221Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3222 3223def int_hexagon_S2_asr_i_r_or : 3224Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3225 3226def int_hexagon_S2_lsr_i_r_or : 3227Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3228 3229def int_hexagon_S2_asl_i_r_or : 3230Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3231 3232def int_hexagon_S2_asr_i_p_and : 3233Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3234 3235def int_hexagon_S2_lsr_i_p_and : 3236Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3237 3238def int_hexagon_S2_asl_i_p_and : 3239Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3240 3241def int_hexagon_S2_asr_i_p_or : 3242Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3243 3244def int_hexagon_S2_lsr_i_p_or : 3245Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3246 3247def int_hexagon_S2_asl_i_p_or : 3248Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3249 3250def int_hexagon_S2_asl_i_r_sat : 3251Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3252 3253def int_hexagon_S2_asr_i_r_rnd : 3254Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3255 3256def int_hexagon_S2_asr_i_r_rnd_goodsyntax : 3257Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3258 3259def int_hexagon_S2_asr_i_p_rnd : 3260Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3261 3262def int_hexagon_S2_asr_i_p_rnd_goodsyntax : 3263Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3264 3265def int_hexagon_S4_lsli : 3266Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 3267 3268def int_hexagon_S2_addasl_rrri : 3269Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3270 3271def int_hexagon_S4_andi_asl_ri : 3272Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3273 3274def int_hexagon_S4_ori_asl_ri : 3275Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3276 3277def int_hexagon_S4_addi_asl_ri : 3278Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3279 3280def int_hexagon_S4_subi_asl_ri : 3281Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3282 3283def int_hexagon_S4_andi_lsr_ri : 3284Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3285 3286def int_hexagon_S4_ori_lsr_ri : 3287Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3288 3289def int_hexagon_S4_addi_lsr_ri : 3290Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3291 3292def int_hexagon_S4_subi_lsr_ri : 3293Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3294 3295def int_hexagon_S2_valignib : 3296Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3297 3298def int_hexagon_S2_valignrb : 3299Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; 3300 3301def int_hexagon_S2_vspliceib : 3302Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3303 3304def int_hexagon_S2_vsplicerb : 3305Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; 3306 3307def int_hexagon_S2_vsplatrh : 3308Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; 3309 3310def int_hexagon_S2_vsplatrb : 3311Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; 3312 3313def int_hexagon_S2_insert : 3314Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3315 3316def int_hexagon_S2_tableidxb_goodsyntax : 3317Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3318 3319def int_hexagon_S2_tableidxh_goodsyntax : 3320Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3321 3322def int_hexagon_S2_tableidxw_goodsyntax : 3323Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3324 3325def int_hexagon_S2_tableidxd_goodsyntax : 3326Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3327 3328def int_hexagon_A4_bitspliti : 3329Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3330 3331def int_hexagon_A4_bitsplit : 3332Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; 3333 3334def int_hexagon_S4_extract : 3335Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3336 3337def int_hexagon_S2_extractu : 3338Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3339 3340def int_hexagon_S2_insertp : 3341Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3342 3343def int_hexagon_S4_extractp : 3344Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3345 3346def int_hexagon_S2_extractup : 3347Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3348 3349def int_hexagon_S2_insert_rp : 3350Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; 3351 3352def int_hexagon_S4_extract_rp : 3353Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; 3354 3355def int_hexagon_S2_extractu_rp : 3356Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; 3357 3358def int_hexagon_S2_insertp_rp : 3359Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; 3360 3361def int_hexagon_S4_extractp_rp : 3362Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; 3363 3364def int_hexagon_S2_extractup_rp : 3365Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; 3366 3367def int_hexagon_S2_tstbit_i : 3368Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3369 3370def int_hexagon_S4_ntstbit_i : 3371Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3372 3373def int_hexagon_S2_setbit_i : 3374Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3375 3376def int_hexagon_S2_togglebit_i : 3377Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3378 3379def int_hexagon_S2_clrbit_i : 3380Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3381 3382def int_hexagon_S2_tstbit_r : 3383Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; 3384 3385def int_hexagon_S4_ntstbit_r : 3386Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; 3387 3388def int_hexagon_S2_setbit_r : 3389Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; 3390 3391def int_hexagon_S2_togglebit_r : 3392Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; 3393 3394def int_hexagon_S2_clrbit_r : 3395Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; 3396 3397def int_hexagon_S2_asr_i_vh : 3398Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3399 3400def int_hexagon_S2_lsr_i_vh : 3401Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3402 3403def int_hexagon_S2_asl_i_vh : 3404Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3405 3406def int_hexagon_S2_asr_r_vh : 3407Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; 3408 3409def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : 3410Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3411 3412def int_hexagon_S5_asrhub_sat : 3413Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3414 3415def int_hexagon_S5_vasrhrnd_goodsyntax : 3416Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3417 3418def int_hexagon_S2_asl_r_vh : 3419Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; 3420 3421def int_hexagon_S2_lsr_r_vh : 3422Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; 3423 3424def int_hexagon_S2_lsl_r_vh : 3425Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; 3426 3427def int_hexagon_S2_asr_i_vw : 3428Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3429 3430def int_hexagon_S2_asr_i_svw_trun : 3431Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3432 3433def int_hexagon_S2_asr_r_svw_trun : 3434Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; 3435 3436def int_hexagon_S2_lsr_i_vw : 3437Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3438 3439def int_hexagon_S2_asl_i_vw : 3440Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3441 3442def int_hexagon_S2_asr_r_vw : 3443Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; 3444 3445def int_hexagon_S2_asl_r_vw : 3446Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; 3447 3448def int_hexagon_S2_lsr_r_vw : 3449Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; 3450 3451def int_hexagon_S2_lsl_r_vw : 3452Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; 3453 3454def int_hexagon_S2_vrndpackwh : 3455Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; 3456 3457def int_hexagon_S2_vrndpackwhs : 3458Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; 3459 3460def int_hexagon_S2_vsxtbh : 3461Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; 3462 3463def int_hexagon_S2_vzxtbh : 3464Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; 3465 3466def int_hexagon_S2_vsathub : 3467Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; 3468 3469def int_hexagon_S2_svsathub : 3470Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; 3471 3472def int_hexagon_S2_svsathb : 3473Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; 3474 3475def int_hexagon_S2_vsathb : 3476Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; 3477 3478def int_hexagon_S2_vtrunohb : 3479Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; 3480 3481def int_hexagon_S2_vtrunewh : 3482Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; 3483 3484def int_hexagon_S2_vtrunowh : 3485Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; 3486 3487def int_hexagon_S2_vtrunehb : 3488Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; 3489 3490def int_hexagon_S2_vsxthw : 3491Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; 3492 3493def int_hexagon_S2_vzxthw : 3494Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; 3495 3496def int_hexagon_S2_vsatwh : 3497Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; 3498 3499def int_hexagon_S2_vsatwuh : 3500Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; 3501 3502def int_hexagon_S2_packhl : 3503Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; 3504 3505def int_hexagon_A2_swiz : 3506Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; 3507 3508def int_hexagon_S2_vsathub_nopack : 3509Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; 3510 3511def int_hexagon_S2_vsathb_nopack : 3512Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; 3513 3514def int_hexagon_S2_vsatwh_nopack : 3515Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; 3516 3517def int_hexagon_S2_vsatwuh_nopack : 3518Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; 3519 3520def int_hexagon_S2_shuffob : 3521Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; 3522 3523def int_hexagon_S2_shuffeb : 3524Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; 3525 3526def int_hexagon_S2_shuffoh : 3527Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; 3528 3529def int_hexagon_S2_shuffeh : 3530Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; 3531 3532def int_hexagon_S5_popcountp : 3533Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; 3534 3535def int_hexagon_S4_parity : 3536Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; 3537 3538def int_hexagon_S2_parityp : 3539Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; 3540 3541def int_hexagon_S2_lfsp : 3542Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; 3543 3544def int_hexagon_S2_clbnorm : 3545Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; 3546 3547def int_hexagon_S4_clbaddi : 3548Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3549 3550def int_hexagon_S4_clbpnorm : 3551Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; 3552 3553def int_hexagon_S4_clbpaddi : 3554Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3555 3556def int_hexagon_S2_clb : 3557Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; 3558 3559def int_hexagon_S2_cl0 : 3560Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; 3561 3562def int_hexagon_S2_cl1 : 3563Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; 3564 3565def int_hexagon_S2_clbp : 3566Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; 3567 3568def int_hexagon_S2_cl0p : 3569Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; 3570 3571def int_hexagon_S2_cl1p : 3572Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; 3573 3574def int_hexagon_S2_brev : 3575Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; 3576 3577def int_hexagon_S2_brevp : 3578Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; 3579 3580def int_hexagon_S2_ct0 : 3581Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; 3582 3583def int_hexagon_S2_ct1 : 3584Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; 3585 3586def int_hexagon_S2_ct0p : 3587Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; 3588 3589def int_hexagon_S2_ct1p : 3590Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; 3591 3592def int_hexagon_S2_interleave : 3593Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; 3594 3595def int_hexagon_S2_deinterleave : 3596Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; 3597 3598def int_hexagon_Y2_dcfetch : 3599Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>; 3600 3601def int_hexagon_Y2_dczeroa : 3602Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>; 3603 3604def int_hexagon_Y2_dccleana : 3605Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>; 3606 3607def int_hexagon_Y2_dccleaninva : 3608Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>; 3609 3610def int_hexagon_Y2_dcinva : 3611Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>; 3612 3613def int_hexagon_Y4_l2fetch : 3614Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>; 3615 3616def int_hexagon_Y5_l2fetch : 3617Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>; 3618 3619// V60 Scalar Instructions. 3620 3621def int_hexagon_S6_rol_i_r : 3622Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3623 3624def int_hexagon_S6_rol_i_p : 3625Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3626 3627def int_hexagon_S6_rol_i_r_acc : 3628Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3629 3630def int_hexagon_S6_rol_i_p_acc : 3631Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3632 3633def int_hexagon_S6_rol_i_r_nac : 3634Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3635 3636def int_hexagon_S6_rol_i_p_nac : 3637Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3638 3639def int_hexagon_S6_rol_i_r_xacc : 3640Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3641 3642def int_hexagon_S6_rol_i_p_xacc : 3643Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3644 3645def int_hexagon_S6_rol_i_r_and : 3646Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3647 3648def int_hexagon_S6_rol_i_r_or : 3649Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3650 3651def int_hexagon_S6_rol_i_p_and : 3652Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3653 3654def int_hexagon_S6_rol_i_p_or : 3655Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3656 3657// V62 Scalar Instructions. 3658 3659def int_hexagon_M6_vabsdiffb : 3660Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">; 3661 3662def int_hexagon_M6_vabsdiffub : 3663Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">; 3664 3665def int_hexagon_S6_vsplatrbp : 3666Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">; 3667 3668def int_hexagon_S6_vtrunehb_ppp : 3669Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; 3670 3671def int_hexagon_S6_vtrunohb_ppp : 3672Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; 3673 3674// V65 Scalar Instructions. 3675 3676def int_hexagon_A6_vcmpbeq_notany : 3677Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; 3678 3679// V66 Scalar Instructions. 3680 3681def int_hexagon_M2_mnaci : 3682Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; 3683 3684def int_hexagon_F2_dfadd : 3685Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>; 3686 3687def int_hexagon_F2_dfsub : 3688Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>; 3689 3690def int_hexagon_S2_mask : 3691Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 3692 3693// V67 Scalar Instructions. 3694 3695def int_hexagon_M7_dcmpyrw : 3696Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">; 3697 3698def int_hexagon_M7_dcmpyrw_acc : 3699Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">; 3700 3701def int_hexagon_M7_dcmpyrwc : 3702Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">; 3703 3704def int_hexagon_M7_dcmpyrwc_acc : 3705Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">; 3706 3707def int_hexagon_M7_dcmpyiw : 3708Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">; 3709 3710def int_hexagon_M7_dcmpyiw_acc : 3711Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">; 3712 3713def int_hexagon_M7_dcmpyiwc : 3714Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">; 3715 3716def int_hexagon_M7_dcmpyiwc_acc : 3717Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">; 3718 3719def int_hexagon_M7_vdmpy : 3720Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">; 3721 3722def int_hexagon_M7_vdmpy_acc : 3723Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">; 3724 3725def int_hexagon_M7_wcmpyrw : 3726Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">; 3727 3728def int_hexagon_M7_wcmpyrwc : 3729Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">; 3730 3731def int_hexagon_M7_wcmpyiw : 3732Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">; 3733 3734def int_hexagon_M7_wcmpyiwc : 3735Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">; 3736 3737def int_hexagon_M7_wcmpyrw_rnd : 3738Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">; 3739 3740def int_hexagon_M7_wcmpyrwc_rnd : 3741Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">; 3742 3743def int_hexagon_M7_wcmpyiw_rnd : 3744Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">; 3745 3746def int_hexagon_M7_wcmpyiwc_rnd : 3747Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">; 3748 3749def int_hexagon_A7_croundd_ri : 3750Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3751 3752def int_hexagon_A7_croundd_rr : 3753Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_rr">; 3754 3755def int_hexagon_A7_clip : 3756Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3757 3758def int_hexagon_A7_vclip : 3759Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3760 3761def int_hexagon_F2_dfmax : 3762Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmax", [IntrNoMem, Throws]>; 3763 3764def int_hexagon_F2_dfmin : 3765Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>; 3766 3767def int_hexagon_F2_dfmpyfix : 3768Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>; 3769 3770def int_hexagon_F2_dfmpyll : 3771Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>; 3772 3773def int_hexagon_F2_dfmpylh : 3774Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>; 3775 3776def int_hexagon_F2_dfmpyhh : 3777Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>; 3778 3779// V60 HVX Instructions. 3780 3781def int_hexagon_V6_vS32b_qpred_ai : 3782Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3783 3784def int_hexagon_V6_vS32b_qpred_ai_128B : 3785Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3786 3787def int_hexagon_V6_vS32b_nqpred_ai : 3788Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3789 3790def int_hexagon_V6_vS32b_nqpred_ai_128B : 3791Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3792 3793def int_hexagon_V6_vS32b_nt_qpred_ai : 3794Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3795 3796def int_hexagon_V6_vS32b_nt_qpred_ai_128B : 3797Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3798 3799def int_hexagon_V6_vS32b_nt_nqpred_ai : 3800Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3801 3802def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : 3803Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3804 3805def int_hexagon_V6_valignb : 3806Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; 3807 3808def int_hexagon_V6_valignb_128B : 3809Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; 3810 3811def int_hexagon_V6_vlalignb : 3812Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; 3813 3814def int_hexagon_V6_vlalignb_128B : 3815Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; 3816 3817def int_hexagon_V6_valignbi : 3818Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3819 3820def int_hexagon_V6_valignbi_128B : 3821Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3822 3823def int_hexagon_V6_vlalignbi : 3824Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3825 3826def int_hexagon_V6_vlalignbi_128B : 3827Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3828 3829def int_hexagon_V6_vror : 3830Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; 3831 3832def int_hexagon_V6_vror_128B : 3833Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; 3834 3835def int_hexagon_V6_vunpackub : 3836Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; 3837 3838def int_hexagon_V6_vunpackub_128B : 3839Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; 3840 3841def int_hexagon_V6_vunpackb : 3842Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; 3843 3844def int_hexagon_V6_vunpackb_128B : 3845Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; 3846 3847def int_hexagon_V6_vunpackuh : 3848Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; 3849 3850def int_hexagon_V6_vunpackuh_128B : 3851Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; 3852 3853def int_hexagon_V6_vunpackh : 3854Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; 3855 3856def int_hexagon_V6_vunpackh_128B : 3857Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; 3858 3859def int_hexagon_V6_vunpackob : 3860Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; 3861 3862def int_hexagon_V6_vunpackob_128B : 3863Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; 3864 3865def int_hexagon_V6_vunpackoh : 3866Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; 3867 3868def int_hexagon_V6_vunpackoh_128B : 3869Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; 3870 3871def int_hexagon_V6_vpackeb : 3872Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; 3873 3874def int_hexagon_V6_vpackeb_128B : 3875Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; 3876 3877def int_hexagon_V6_vpackeh : 3878Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; 3879 3880def int_hexagon_V6_vpackeh_128B : 3881Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; 3882 3883def int_hexagon_V6_vpackob : 3884Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; 3885 3886def int_hexagon_V6_vpackob_128B : 3887Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; 3888 3889def int_hexagon_V6_vpackoh : 3890Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; 3891 3892def int_hexagon_V6_vpackoh_128B : 3893Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; 3894 3895def int_hexagon_V6_vpackhub_sat : 3896Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; 3897 3898def int_hexagon_V6_vpackhub_sat_128B : 3899Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; 3900 3901def int_hexagon_V6_vpackhb_sat : 3902Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; 3903 3904def int_hexagon_V6_vpackhb_sat_128B : 3905Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; 3906 3907def int_hexagon_V6_vpackwuh_sat : 3908Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; 3909 3910def int_hexagon_V6_vpackwuh_sat_128B : 3911Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; 3912 3913def int_hexagon_V6_vpackwh_sat : 3914Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; 3915 3916def int_hexagon_V6_vpackwh_sat_128B : 3917Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; 3918 3919def int_hexagon_V6_vzb : 3920Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; 3921 3922def int_hexagon_V6_vzb_128B : 3923Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; 3924 3925def int_hexagon_V6_vsb : 3926Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; 3927 3928def int_hexagon_V6_vsb_128B : 3929Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; 3930 3931def int_hexagon_V6_vzh : 3932Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; 3933 3934def int_hexagon_V6_vzh_128B : 3935Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; 3936 3937def int_hexagon_V6_vsh : 3938Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; 3939 3940def int_hexagon_V6_vsh_128B : 3941Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; 3942 3943def int_hexagon_V6_vdmpybus : 3944Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; 3945 3946def int_hexagon_V6_vdmpybus_128B : 3947Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; 3948 3949def int_hexagon_V6_vdmpybus_acc : 3950Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; 3951 3952def int_hexagon_V6_vdmpybus_acc_128B : 3953Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; 3954 3955def int_hexagon_V6_vdmpybus_dv : 3956Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; 3957 3958def int_hexagon_V6_vdmpybus_dv_128B : 3959Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; 3960 3961def int_hexagon_V6_vdmpybus_dv_acc : 3962Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; 3963 3964def int_hexagon_V6_vdmpybus_dv_acc_128B : 3965Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; 3966 3967def int_hexagon_V6_vdmpyhb : 3968Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">; 3969 3970def int_hexagon_V6_vdmpyhb_128B : 3971Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; 3972 3973def int_hexagon_V6_vdmpyhb_acc : 3974Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; 3975 3976def int_hexagon_V6_vdmpyhb_acc_128B : 3977Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; 3978 3979def int_hexagon_V6_vdmpyhb_dv : 3980Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; 3981 3982def int_hexagon_V6_vdmpyhb_dv_128B : 3983Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; 3984 3985def int_hexagon_V6_vdmpyhb_dv_acc : 3986Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; 3987 3988def int_hexagon_V6_vdmpyhb_dv_acc_128B : 3989Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; 3990 3991def int_hexagon_V6_vdmpyhvsat : 3992Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; 3993 3994def int_hexagon_V6_vdmpyhvsat_128B : 3995Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; 3996 3997def int_hexagon_V6_vdmpyhvsat_acc : 3998Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; 3999 4000def int_hexagon_V6_vdmpyhvsat_acc_128B : 4001Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; 4002 4003def int_hexagon_V6_vdmpyhsat : 4004Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; 4005 4006def int_hexagon_V6_vdmpyhsat_128B : 4007Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; 4008 4009def int_hexagon_V6_vdmpyhsat_acc : 4010Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; 4011 4012def int_hexagon_V6_vdmpyhsat_acc_128B : 4013Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; 4014 4015def int_hexagon_V6_vdmpyhisat : 4016Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; 4017 4018def int_hexagon_V6_vdmpyhisat_128B : 4019Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; 4020 4021def int_hexagon_V6_vdmpyhisat_acc : 4022Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; 4023 4024def int_hexagon_V6_vdmpyhisat_acc_128B : 4025Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; 4026 4027def int_hexagon_V6_vdmpyhsusat : 4028Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; 4029 4030def int_hexagon_V6_vdmpyhsusat_128B : 4031Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; 4032 4033def int_hexagon_V6_vdmpyhsusat_acc : 4034Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; 4035 4036def int_hexagon_V6_vdmpyhsusat_acc_128B : 4037Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; 4038 4039def int_hexagon_V6_vdmpyhsuisat : 4040Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; 4041 4042def int_hexagon_V6_vdmpyhsuisat_128B : 4043Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; 4044 4045def int_hexagon_V6_vdmpyhsuisat_acc : 4046Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; 4047 4048def int_hexagon_V6_vdmpyhsuisat_acc_128B : 4049Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; 4050 4051def int_hexagon_V6_vtmpyb : 4052Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; 4053 4054def int_hexagon_V6_vtmpyb_128B : 4055Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; 4056 4057def int_hexagon_V6_vtmpyb_acc : 4058Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; 4059 4060def int_hexagon_V6_vtmpyb_acc_128B : 4061Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; 4062 4063def int_hexagon_V6_vtmpybus : 4064Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; 4065 4066def int_hexagon_V6_vtmpybus_128B : 4067Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; 4068 4069def int_hexagon_V6_vtmpybus_acc : 4070Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; 4071 4072def int_hexagon_V6_vtmpybus_acc_128B : 4073Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; 4074 4075def int_hexagon_V6_vtmpyhb : 4076Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; 4077 4078def int_hexagon_V6_vtmpyhb_128B : 4079Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; 4080 4081def int_hexagon_V6_vtmpyhb_acc : 4082Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; 4083 4084def int_hexagon_V6_vtmpyhb_acc_128B : 4085Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; 4086 4087def int_hexagon_V6_vrmpyub : 4088Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; 4089 4090def int_hexagon_V6_vrmpyub_128B : 4091Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; 4092 4093def int_hexagon_V6_vrmpyub_acc : 4094Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; 4095 4096def int_hexagon_V6_vrmpyub_acc_128B : 4097Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; 4098 4099def int_hexagon_V6_vrmpyubv : 4100Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; 4101 4102def int_hexagon_V6_vrmpyubv_128B : 4103Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; 4104 4105def int_hexagon_V6_vrmpyubv_acc : 4106Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; 4107 4108def int_hexagon_V6_vrmpyubv_acc_128B : 4109Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; 4110 4111def int_hexagon_V6_vrmpybv : 4112Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; 4113 4114def int_hexagon_V6_vrmpybv_128B : 4115Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; 4116 4117def int_hexagon_V6_vrmpybv_acc : 4118Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; 4119 4120def int_hexagon_V6_vrmpybv_acc_128B : 4121Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; 4122 4123def int_hexagon_V6_vrmpyubi : 4124Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4125 4126def int_hexagon_V6_vrmpyubi_128B : 4127Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4128 4129def int_hexagon_V6_vrmpyubi_acc : 4130Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 4131 4132def int_hexagon_V6_vrmpyubi_acc_128B : 4133Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 4134 4135def int_hexagon_V6_vrmpybus : 4136Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; 4137 4138def int_hexagon_V6_vrmpybus_128B : 4139Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; 4140 4141def int_hexagon_V6_vrmpybus_acc : 4142Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; 4143 4144def int_hexagon_V6_vrmpybus_acc_128B : 4145Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; 4146 4147def int_hexagon_V6_vrmpybusi : 4148Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4149 4150def int_hexagon_V6_vrmpybusi_128B : 4151Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4152 4153def int_hexagon_V6_vrmpybusi_acc : 4154Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 4155 4156def int_hexagon_V6_vrmpybusi_acc_128B : 4157Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 4158 4159def int_hexagon_V6_vrmpybusv : 4160Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">; 4161 4162def int_hexagon_V6_vrmpybusv_128B : 4163Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; 4164 4165def int_hexagon_V6_vrmpybusv_acc : 4166Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; 4167 4168def int_hexagon_V6_vrmpybusv_acc_128B : 4169Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; 4170 4171def int_hexagon_V6_vdsaduh : 4172Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; 4173 4174def int_hexagon_V6_vdsaduh_128B : 4175Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; 4176 4177def int_hexagon_V6_vdsaduh_acc : 4178Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; 4179 4180def int_hexagon_V6_vdsaduh_acc_128B : 4181Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; 4182 4183def int_hexagon_V6_vrsadubi : 4184Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4185 4186def int_hexagon_V6_vrsadubi_128B : 4187Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4188 4189def int_hexagon_V6_vrsadubi_acc : 4190Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 4191 4192def int_hexagon_V6_vrsadubi_acc_128B : 4193Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 4194 4195def int_hexagon_V6_vasrw : 4196Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; 4197 4198def int_hexagon_V6_vasrw_128B : 4199Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; 4200 4201def int_hexagon_V6_vaslw : 4202Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; 4203 4204def int_hexagon_V6_vaslw_128B : 4205Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; 4206 4207def int_hexagon_V6_vlsrw : 4208Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; 4209 4210def int_hexagon_V6_vlsrw_128B : 4211Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; 4212 4213def int_hexagon_V6_vasrwv : 4214Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; 4215 4216def int_hexagon_V6_vasrwv_128B : 4217Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; 4218 4219def int_hexagon_V6_vaslwv : 4220Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; 4221 4222def int_hexagon_V6_vaslwv_128B : 4223Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; 4224 4225def int_hexagon_V6_vlsrwv : 4226Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; 4227 4228def int_hexagon_V6_vlsrwv_128B : 4229Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; 4230 4231def int_hexagon_V6_vasrh : 4232Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; 4233 4234def int_hexagon_V6_vasrh_128B : 4235Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; 4236 4237def int_hexagon_V6_vaslh : 4238Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; 4239 4240def int_hexagon_V6_vaslh_128B : 4241Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; 4242 4243def int_hexagon_V6_vlsrh : 4244Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; 4245 4246def int_hexagon_V6_vlsrh_128B : 4247Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; 4248 4249def int_hexagon_V6_vasrhv : 4250Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; 4251 4252def int_hexagon_V6_vasrhv_128B : 4253Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; 4254 4255def int_hexagon_V6_vaslhv : 4256Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; 4257 4258def int_hexagon_V6_vaslhv_128B : 4259Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; 4260 4261def int_hexagon_V6_vlsrhv : 4262Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; 4263 4264def int_hexagon_V6_vlsrhv_128B : 4265Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; 4266 4267def int_hexagon_V6_vasrwh : 4268Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; 4269 4270def int_hexagon_V6_vasrwh_128B : 4271Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; 4272 4273def int_hexagon_V6_vasrwhsat : 4274Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; 4275 4276def int_hexagon_V6_vasrwhsat_128B : 4277Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; 4278 4279def int_hexagon_V6_vasrwhrndsat : 4280Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; 4281 4282def int_hexagon_V6_vasrwhrndsat_128B : 4283Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; 4284 4285def int_hexagon_V6_vasrwuhsat : 4286Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; 4287 4288def int_hexagon_V6_vasrwuhsat_128B : 4289Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; 4290 4291def int_hexagon_V6_vroundwh : 4292Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; 4293 4294def int_hexagon_V6_vroundwh_128B : 4295Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; 4296 4297def int_hexagon_V6_vroundwuh : 4298Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; 4299 4300def int_hexagon_V6_vroundwuh_128B : 4301Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; 4302 4303def int_hexagon_V6_vasrhubsat : 4304Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; 4305 4306def int_hexagon_V6_vasrhubsat_128B : 4307Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; 4308 4309def int_hexagon_V6_vasrhubrndsat : 4310Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; 4311 4312def int_hexagon_V6_vasrhubrndsat_128B : 4313Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; 4314 4315def int_hexagon_V6_vasrhbrndsat : 4316Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; 4317 4318def int_hexagon_V6_vasrhbrndsat_128B : 4319Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; 4320 4321def int_hexagon_V6_vroundhb : 4322Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; 4323 4324def int_hexagon_V6_vroundhb_128B : 4325Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">; 4326 4327def int_hexagon_V6_vroundhub : 4328Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; 4329 4330def int_hexagon_V6_vroundhub_128B : 4331Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; 4332 4333def int_hexagon_V6_vaslw_acc : 4334Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; 4335 4336def int_hexagon_V6_vaslw_acc_128B : 4337Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; 4338 4339def int_hexagon_V6_vasrw_acc : 4340Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; 4341 4342def int_hexagon_V6_vasrw_acc_128B : 4343Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; 4344 4345def int_hexagon_V6_vaddb : 4346Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; 4347 4348def int_hexagon_V6_vaddb_128B : 4349Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; 4350 4351def int_hexagon_V6_vsubb : 4352Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; 4353 4354def int_hexagon_V6_vsubb_128B : 4355Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; 4356 4357def int_hexagon_V6_vaddb_dv : 4358Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; 4359 4360def int_hexagon_V6_vaddb_dv_128B : 4361Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; 4362 4363def int_hexagon_V6_vsubb_dv : 4364Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; 4365 4366def int_hexagon_V6_vsubb_dv_128B : 4367Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; 4368 4369def int_hexagon_V6_vaddh : 4370Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; 4371 4372def int_hexagon_V6_vaddh_128B : 4373Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; 4374 4375def int_hexagon_V6_vsubh : 4376Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; 4377 4378def int_hexagon_V6_vsubh_128B : 4379Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; 4380 4381def int_hexagon_V6_vaddh_dv : 4382Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; 4383 4384def int_hexagon_V6_vaddh_dv_128B : 4385Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; 4386 4387def int_hexagon_V6_vsubh_dv : 4388Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; 4389 4390def int_hexagon_V6_vsubh_dv_128B : 4391Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; 4392 4393def int_hexagon_V6_vaddw : 4394Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; 4395 4396def int_hexagon_V6_vaddw_128B : 4397Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; 4398 4399def int_hexagon_V6_vsubw : 4400Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; 4401 4402def int_hexagon_V6_vsubw_128B : 4403Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; 4404 4405def int_hexagon_V6_vaddw_dv : 4406Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; 4407 4408def int_hexagon_V6_vaddw_dv_128B : 4409Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; 4410 4411def int_hexagon_V6_vsubw_dv : 4412Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; 4413 4414def int_hexagon_V6_vsubw_dv_128B : 4415Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; 4416 4417def int_hexagon_V6_vaddubsat : 4418Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; 4419 4420def int_hexagon_V6_vaddubsat_128B : 4421Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; 4422 4423def int_hexagon_V6_vaddubsat_dv : 4424Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; 4425 4426def int_hexagon_V6_vaddubsat_dv_128B : 4427Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; 4428 4429def int_hexagon_V6_vsububsat : 4430Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; 4431 4432def int_hexagon_V6_vsububsat_128B : 4433Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; 4434 4435def int_hexagon_V6_vsububsat_dv : 4436Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; 4437 4438def int_hexagon_V6_vsububsat_dv_128B : 4439Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; 4440 4441def int_hexagon_V6_vadduhsat : 4442Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; 4443 4444def int_hexagon_V6_vadduhsat_128B : 4445Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; 4446 4447def int_hexagon_V6_vadduhsat_dv : 4448Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; 4449 4450def int_hexagon_V6_vadduhsat_dv_128B : 4451Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; 4452 4453def int_hexagon_V6_vsubuhsat : 4454Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; 4455 4456def int_hexagon_V6_vsubuhsat_128B : 4457Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; 4458 4459def int_hexagon_V6_vsubuhsat_dv : 4460Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; 4461 4462def int_hexagon_V6_vsubuhsat_dv_128B : 4463Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; 4464 4465def int_hexagon_V6_vaddhsat : 4466Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; 4467 4468def int_hexagon_V6_vaddhsat_128B : 4469Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; 4470 4471def int_hexagon_V6_vaddhsat_dv : 4472Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; 4473 4474def int_hexagon_V6_vaddhsat_dv_128B : 4475Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; 4476 4477def int_hexagon_V6_vsubhsat : 4478Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; 4479 4480def int_hexagon_V6_vsubhsat_128B : 4481Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; 4482 4483def int_hexagon_V6_vsubhsat_dv : 4484Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; 4485 4486def int_hexagon_V6_vsubhsat_dv_128B : 4487Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; 4488 4489def int_hexagon_V6_vaddwsat : 4490Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; 4491 4492def int_hexagon_V6_vaddwsat_128B : 4493Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; 4494 4495def int_hexagon_V6_vaddwsat_dv : 4496Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; 4497 4498def int_hexagon_V6_vaddwsat_dv_128B : 4499Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; 4500 4501def int_hexagon_V6_vsubwsat : 4502Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; 4503 4504def int_hexagon_V6_vsubwsat_128B : 4505Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; 4506 4507def int_hexagon_V6_vsubwsat_dv : 4508Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; 4509 4510def int_hexagon_V6_vsubwsat_dv_128B : 4511Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; 4512 4513def int_hexagon_V6_vavgub : 4514Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; 4515 4516def int_hexagon_V6_vavgub_128B : 4517Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; 4518 4519def int_hexagon_V6_vavgubrnd : 4520Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; 4521 4522def int_hexagon_V6_vavgubrnd_128B : 4523Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; 4524 4525def int_hexagon_V6_vavguh : 4526Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; 4527 4528def int_hexagon_V6_vavguh_128B : 4529Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; 4530 4531def int_hexagon_V6_vavguhrnd : 4532Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; 4533 4534def int_hexagon_V6_vavguhrnd_128B : 4535Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; 4536 4537def int_hexagon_V6_vavgh : 4538Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; 4539 4540def int_hexagon_V6_vavgh_128B : 4541Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; 4542 4543def int_hexagon_V6_vavghrnd : 4544Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; 4545 4546def int_hexagon_V6_vavghrnd_128B : 4547Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; 4548 4549def int_hexagon_V6_vnavgh : 4550Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; 4551 4552def int_hexagon_V6_vnavgh_128B : 4553Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; 4554 4555def int_hexagon_V6_vavgw : 4556Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; 4557 4558def int_hexagon_V6_vavgw_128B : 4559Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; 4560 4561def int_hexagon_V6_vavgwrnd : 4562Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; 4563 4564def int_hexagon_V6_vavgwrnd_128B : 4565Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; 4566 4567def int_hexagon_V6_vnavgw : 4568Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; 4569 4570def int_hexagon_V6_vnavgw_128B : 4571Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; 4572 4573def int_hexagon_V6_vabsdiffub : 4574Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; 4575 4576def int_hexagon_V6_vabsdiffub_128B : 4577Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; 4578 4579def int_hexagon_V6_vabsdiffuh : 4580Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; 4581 4582def int_hexagon_V6_vabsdiffuh_128B : 4583Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; 4584 4585def int_hexagon_V6_vabsdiffh : 4586Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; 4587 4588def int_hexagon_V6_vabsdiffh_128B : 4589Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; 4590 4591def int_hexagon_V6_vabsdiffw : 4592Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; 4593 4594def int_hexagon_V6_vabsdiffw_128B : 4595Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; 4596 4597def int_hexagon_V6_vnavgub : 4598Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; 4599 4600def int_hexagon_V6_vnavgub_128B : 4601Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; 4602 4603def int_hexagon_V6_vaddubh : 4604Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; 4605 4606def int_hexagon_V6_vaddubh_128B : 4607Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; 4608 4609def int_hexagon_V6_vsububh : 4610Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; 4611 4612def int_hexagon_V6_vsububh_128B : 4613Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; 4614 4615def int_hexagon_V6_vaddhw : 4616Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; 4617 4618def int_hexagon_V6_vaddhw_128B : 4619Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; 4620 4621def int_hexagon_V6_vsubhw : 4622Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; 4623 4624def int_hexagon_V6_vsubhw_128B : 4625Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; 4626 4627def int_hexagon_V6_vadduhw : 4628Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; 4629 4630def int_hexagon_V6_vadduhw_128B : 4631Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; 4632 4633def int_hexagon_V6_vsubuhw : 4634Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; 4635 4636def int_hexagon_V6_vsubuhw_128B : 4637Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; 4638 4639def int_hexagon_V6_vd0 : 4640Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; 4641 4642def int_hexagon_V6_vd0_128B : 4643Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; 4644 4645def int_hexagon_V6_vaddbq : 4646Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4647 4648def int_hexagon_V6_vaddbq_128B : 4649Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4650 4651def int_hexagon_V6_vsubbq : 4652Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4653 4654def int_hexagon_V6_vsubbq_128B : 4655Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4656 4657def int_hexagon_V6_vaddbnq : 4658Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4659 4660def int_hexagon_V6_vaddbnq_128B : 4661Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4662 4663def int_hexagon_V6_vsubbnq : 4664Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4665 4666def int_hexagon_V6_vsubbnq_128B : 4667Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4668 4669def int_hexagon_V6_vaddhq : 4670Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4671 4672def int_hexagon_V6_vaddhq_128B : 4673Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4674 4675def int_hexagon_V6_vsubhq : 4676Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4677 4678def int_hexagon_V6_vsubhq_128B : 4679Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4680 4681def int_hexagon_V6_vaddhnq : 4682Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4683 4684def int_hexagon_V6_vaddhnq_128B : 4685Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4686 4687def int_hexagon_V6_vsubhnq : 4688Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4689 4690def int_hexagon_V6_vsubhnq_128B : 4691Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4692 4693def int_hexagon_V6_vaddwq : 4694Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4695 4696def int_hexagon_V6_vaddwq_128B : 4697Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4698 4699def int_hexagon_V6_vsubwq : 4700Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4701 4702def int_hexagon_V6_vsubwq_128B : 4703Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4704 4705def int_hexagon_V6_vaddwnq : 4706Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4707 4708def int_hexagon_V6_vaddwnq_128B : 4709Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4710 4711def int_hexagon_V6_vsubwnq : 4712Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4713 4714def int_hexagon_V6_vsubwnq_128B : 4715Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4716 4717def int_hexagon_V6_vabsh : 4718Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; 4719 4720def int_hexagon_V6_vabsh_128B : 4721Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; 4722 4723def int_hexagon_V6_vabsh_sat : 4724Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; 4725 4726def int_hexagon_V6_vabsh_sat_128B : 4727Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; 4728 4729def int_hexagon_V6_vabsw : 4730Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; 4731 4732def int_hexagon_V6_vabsw_128B : 4733Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; 4734 4735def int_hexagon_V6_vabsw_sat : 4736Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; 4737 4738def int_hexagon_V6_vabsw_sat_128B : 4739Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; 4740 4741def int_hexagon_V6_vmpybv : 4742Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; 4743 4744def int_hexagon_V6_vmpybv_128B : 4745Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; 4746 4747def int_hexagon_V6_vmpybv_acc : 4748Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; 4749 4750def int_hexagon_V6_vmpybv_acc_128B : 4751Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; 4752 4753def int_hexagon_V6_vmpyubv : 4754Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; 4755 4756def int_hexagon_V6_vmpyubv_128B : 4757Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; 4758 4759def int_hexagon_V6_vmpyubv_acc : 4760Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; 4761 4762def int_hexagon_V6_vmpyubv_acc_128B : 4763Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; 4764 4765def int_hexagon_V6_vmpybusv : 4766Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; 4767 4768def int_hexagon_V6_vmpybusv_128B : 4769Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; 4770 4771def int_hexagon_V6_vmpybusv_acc : 4772Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; 4773 4774def int_hexagon_V6_vmpybusv_acc_128B : 4775Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; 4776 4777def int_hexagon_V6_vmpabusv : 4778Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; 4779 4780def int_hexagon_V6_vmpabusv_128B : 4781Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; 4782 4783def int_hexagon_V6_vmpabuuv : 4784Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; 4785 4786def int_hexagon_V6_vmpabuuv_128B : 4787Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; 4788 4789def int_hexagon_V6_vmpyhv : 4790Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; 4791 4792def int_hexagon_V6_vmpyhv_128B : 4793Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; 4794 4795def int_hexagon_V6_vmpyhv_acc : 4796Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; 4797 4798def int_hexagon_V6_vmpyhv_acc_128B : 4799Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; 4800 4801def int_hexagon_V6_vmpyuhv : 4802Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; 4803 4804def int_hexagon_V6_vmpyuhv_128B : 4805Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; 4806 4807def int_hexagon_V6_vmpyuhv_acc : 4808Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; 4809 4810def int_hexagon_V6_vmpyuhv_acc_128B : 4811Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; 4812 4813def int_hexagon_V6_vmpyhvsrs : 4814Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; 4815 4816def int_hexagon_V6_vmpyhvsrs_128B : 4817Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; 4818 4819def int_hexagon_V6_vmpyhus : 4820Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; 4821 4822def int_hexagon_V6_vmpyhus_128B : 4823Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; 4824 4825def int_hexagon_V6_vmpyhus_acc : 4826Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; 4827 4828def int_hexagon_V6_vmpyhus_acc_128B : 4829Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; 4830 4831def int_hexagon_V6_vmpyih : 4832Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; 4833 4834def int_hexagon_V6_vmpyih_128B : 4835Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; 4836 4837def int_hexagon_V6_vmpyih_acc : 4838Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; 4839 4840def int_hexagon_V6_vmpyih_acc_128B : 4841Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; 4842 4843def int_hexagon_V6_vmpyewuh : 4844Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; 4845 4846def int_hexagon_V6_vmpyewuh_128B : 4847Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; 4848 4849def int_hexagon_V6_vmpyowh : 4850Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; 4851 4852def int_hexagon_V6_vmpyowh_128B : 4853Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; 4854 4855def int_hexagon_V6_vmpyowh_rnd : 4856Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; 4857 4858def int_hexagon_V6_vmpyowh_rnd_128B : 4859Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; 4860 4861def int_hexagon_V6_vmpyowh_sacc : 4862Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; 4863 4864def int_hexagon_V6_vmpyowh_sacc_128B : 4865Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; 4866 4867def int_hexagon_V6_vmpyowh_rnd_sacc : 4868Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; 4869 4870def int_hexagon_V6_vmpyowh_rnd_sacc_128B : 4871Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; 4872 4873def int_hexagon_V6_vmpyieoh : 4874Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; 4875 4876def int_hexagon_V6_vmpyieoh_128B : 4877Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; 4878 4879def int_hexagon_V6_vmpyiewuh : 4880Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; 4881 4882def int_hexagon_V6_vmpyiewuh_128B : 4883Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; 4884 4885def int_hexagon_V6_vmpyiowh : 4886Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; 4887 4888def int_hexagon_V6_vmpyiowh_128B : 4889Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; 4890 4891def int_hexagon_V6_vmpyiewh_acc : 4892Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; 4893 4894def int_hexagon_V6_vmpyiewh_acc_128B : 4895Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; 4896 4897def int_hexagon_V6_vmpyiewuh_acc : 4898Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; 4899 4900def int_hexagon_V6_vmpyiewuh_acc_128B : 4901Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; 4902 4903def int_hexagon_V6_vmpyub : 4904Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; 4905 4906def int_hexagon_V6_vmpyub_128B : 4907Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; 4908 4909def int_hexagon_V6_vmpyub_acc : 4910Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; 4911 4912def int_hexagon_V6_vmpyub_acc_128B : 4913Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; 4914 4915def int_hexagon_V6_vmpybus : 4916Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; 4917 4918def int_hexagon_V6_vmpybus_128B : 4919Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; 4920 4921def int_hexagon_V6_vmpybus_acc : 4922Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; 4923 4924def int_hexagon_V6_vmpybus_acc_128B : 4925Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; 4926 4927def int_hexagon_V6_vmpabus : 4928Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; 4929 4930def int_hexagon_V6_vmpabus_128B : 4931Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; 4932 4933def int_hexagon_V6_vmpabus_acc : 4934Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; 4935 4936def int_hexagon_V6_vmpabus_acc_128B : 4937Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; 4938 4939def int_hexagon_V6_vmpahb : 4940Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; 4941 4942def int_hexagon_V6_vmpahb_128B : 4943Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; 4944 4945def int_hexagon_V6_vmpahb_acc : 4946Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; 4947 4948def int_hexagon_V6_vmpahb_acc_128B : 4949Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; 4950 4951def int_hexagon_V6_vmpyh : 4952Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; 4953 4954def int_hexagon_V6_vmpyh_128B : 4955Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; 4956 4957def int_hexagon_V6_vmpyhsat_acc : 4958Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; 4959 4960def int_hexagon_V6_vmpyhsat_acc_128B : 4961Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; 4962 4963def int_hexagon_V6_vmpyhss : 4964Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; 4965 4966def int_hexagon_V6_vmpyhss_128B : 4967Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; 4968 4969def int_hexagon_V6_vmpyhsrs : 4970Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; 4971 4972def int_hexagon_V6_vmpyhsrs_128B : 4973Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; 4974 4975def int_hexagon_V6_vmpyuh : 4976Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; 4977 4978def int_hexagon_V6_vmpyuh_128B : 4979Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; 4980 4981def int_hexagon_V6_vmpyuh_acc : 4982Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; 4983 4984def int_hexagon_V6_vmpyuh_acc_128B : 4985Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; 4986 4987def int_hexagon_V6_vmpyihb : 4988Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; 4989 4990def int_hexagon_V6_vmpyihb_128B : 4991Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; 4992 4993def int_hexagon_V6_vmpyihb_acc : 4994Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; 4995 4996def int_hexagon_V6_vmpyihb_acc_128B : 4997Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; 4998 4999def int_hexagon_V6_vmpyiwb : 5000Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; 5001 5002def int_hexagon_V6_vmpyiwb_128B : 5003Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; 5004 5005def int_hexagon_V6_vmpyiwb_acc : 5006Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; 5007 5008def int_hexagon_V6_vmpyiwb_acc_128B : 5009Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; 5010 5011def int_hexagon_V6_vmpyiwh : 5012Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; 5013 5014def int_hexagon_V6_vmpyiwh_128B : 5015Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; 5016 5017def int_hexagon_V6_vmpyiwh_acc : 5018Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; 5019 5020def int_hexagon_V6_vmpyiwh_acc_128B : 5021Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; 5022 5023def int_hexagon_V6_vand : 5024Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; 5025 5026def int_hexagon_V6_vand_128B : 5027Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; 5028 5029def int_hexagon_V6_vor : 5030Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; 5031 5032def int_hexagon_V6_vor_128B : 5033Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; 5034 5035def int_hexagon_V6_vxor : 5036Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; 5037 5038def int_hexagon_V6_vxor_128B : 5039Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; 5040 5041def int_hexagon_V6_vnot : 5042Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; 5043 5044def int_hexagon_V6_vnot_128B : 5045Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; 5046 5047def int_hexagon_V6_vandqrt : 5048Hexagon_custom_v16i32_v64i1i32_Intrinsic; 5049 5050def int_hexagon_V6_vandqrt_128B : 5051Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; 5052 5053def int_hexagon_V6_vandqrt_acc : 5054Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; 5055 5056def int_hexagon_V6_vandqrt_acc_128B : 5057Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; 5058 5059def int_hexagon_V6_vandvrt : 5060Hexagon_custom_v64i1_v16i32i32_Intrinsic; 5061 5062def int_hexagon_V6_vandvrt_128B : 5063Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B; 5064 5065def int_hexagon_V6_vandvrt_acc : 5066Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic; 5067 5068def int_hexagon_V6_vandvrt_acc_128B : 5069Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B; 5070 5071def int_hexagon_V6_vgtw : 5072Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5073 5074def int_hexagon_V6_vgtw_128B : 5075Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5076 5077def int_hexagon_V6_vgtw_and : 5078Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5079 5080def int_hexagon_V6_vgtw_and_128B : 5081Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5082 5083def int_hexagon_V6_vgtw_or : 5084Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5085 5086def int_hexagon_V6_vgtw_or_128B : 5087Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5088 5089def int_hexagon_V6_vgtw_xor : 5090Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5091 5092def int_hexagon_V6_vgtw_xor_128B : 5093Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5094 5095def int_hexagon_V6_veqw : 5096Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5097 5098def int_hexagon_V6_veqw_128B : 5099Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5100 5101def int_hexagon_V6_veqw_and : 5102Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5103 5104def int_hexagon_V6_veqw_and_128B : 5105Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5106 5107def int_hexagon_V6_veqw_or : 5108Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5109 5110def int_hexagon_V6_veqw_or_128B : 5111Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5112 5113def int_hexagon_V6_veqw_xor : 5114Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5115 5116def int_hexagon_V6_veqw_xor_128B : 5117Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5118 5119def int_hexagon_V6_vgth : 5120Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5121 5122def int_hexagon_V6_vgth_128B : 5123Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5124 5125def int_hexagon_V6_vgth_and : 5126Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5127 5128def int_hexagon_V6_vgth_and_128B : 5129Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5130 5131def int_hexagon_V6_vgth_or : 5132Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5133 5134def int_hexagon_V6_vgth_or_128B : 5135Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5136 5137def int_hexagon_V6_vgth_xor : 5138Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5139 5140def int_hexagon_V6_vgth_xor_128B : 5141Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5142 5143def int_hexagon_V6_veqh : 5144Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5145 5146def int_hexagon_V6_veqh_128B : 5147Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5148 5149def int_hexagon_V6_veqh_and : 5150Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5151 5152def int_hexagon_V6_veqh_and_128B : 5153Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5154 5155def int_hexagon_V6_veqh_or : 5156Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5157 5158def int_hexagon_V6_veqh_or_128B : 5159Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5160 5161def int_hexagon_V6_veqh_xor : 5162Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5163 5164def int_hexagon_V6_veqh_xor_128B : 5165Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5166 5167def int_hexagon_V6_vgtb : 5168Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5169 5170def int_hexagon_V6_vgtb_128B : 5171Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5172 5173def int_hexagon_V6_vgtb_and : 5174Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5175 5176def int_hexagon_V6_vgtb_and_128B : 5177Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5178 5179def int_hexagon_V6_vgtb_or : 5180Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5181 5182def int_hexagon_V6_vgtb_or_128B : 5183Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5184 5185def int_hexagon_V6_vgtb_xor : 5186Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5187 5188def int_hexagon_V6_vgtb_xor_128B : 5189Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5190 5191def int_hexagon_V6_veqb : 5192Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5193 5194def int_hexagon_V6_veqb_128B : 5195Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5196 5197def int_hexagon_V6_veqb_and : 5198Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5199 5200def int_hexagon_V6_veqb_and_128B : 5201Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5202 5203def int_hexagon_V6_veqb_or : 5204Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5205 5206def int_hexagon_V6_veqb_or_128B : 5207Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5208 5209def int_hexagon_V6_veqb_xor : 5210Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5211 5212def int_hexagon_V6_veqb_xor_128B : 5213Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5214 5215def int_hexagon_V6_vgtuw : 5216Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5217 5218def int_hexagon_V6_vgtuw_128B : 5219Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5220 5221def int_hexagon_V6_vgtuw_and : 5222Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5223 5224def int_hexagon_V6_vgtuw_and_128B : 5225Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5226 5227def int_hexagon_V6_vgtuw_or : 5228Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5229 5230def int_hexagon_V6_vgtuw_or_128B : 5231Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5232 5233def int_hexagon_V6_vgtuw_xor : 5234Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5235 5236def int_hexagon_V6_vgtuw_xor_128B : 5237Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5238 5239def int_hexagon_V6_vgtuh : 5240Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5241 5242def int_hexagon_V6_vgtuh_128B : 5243Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5244 5245def int_hexagon_V6_vgtuh_and : 5246Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5247 5248def int_hexagon_V6_vgtuh_and_128B : 5249Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5250 5251def int_hexagon_V6_vgtuh_or : 5252Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5253 5254def int_hexagon_V6_vgtuh_or_128B : 5255Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5256 5257def int_hexagon_V6_vgtuh_xor : 5258Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5259 5260def int_hexagon_V6_vgtuh_xor_128B : 5261Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5262 5263def int_hexagon_V6_vgtub : 5264Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 5265 5266def int_hexagon_V6_vgtub_128B : 5267Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 5268 5269def int_hexagon_V6_vgtub_and : 5270Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5271 5272def int_hexagon_V6_vgtub_and_128B : 5273Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5274 5275def int_hexagon_V6_vgtub_or : 5276Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5277 5278def int_hexagon_V6_vgtub_or_128B : 5279Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5280 5281def int_hexagon_V6_vgtub_xor : 5282Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 5283 5284def int_hexagon_V6_vgtub_xor_128B : 5285Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 5286 5287def int_hexagon_V6_pred_or : 5288Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5289 5290def int_hexagon_V6_pred_or_128B : 5291Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5292 5293def int_hexagon_V6_pred_and : 5294Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5295 5296def int_hexagon_V6_pred_and_128B : 5297Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5298 5299def int_hexagon_V6_pred_not : 5300Hexagon_custom_v64i1_v64i1_Intrinsic; 5301 5302def int_hexagon_V6_pred_not_128B : 5303Hexagon_custom_v128i1_v128i1_Intrinsic_128B; 5304 5305def int_hexagon_V6_pred_xor : 5306Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5307 5308def int_hexagon_V6_pred_xor_128B : 5309Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5310 5311def int_hexagon_V6_pred_and_n : 5312Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5313 5314def int_hexagon_V6_pred_and_n_128B : 5315Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5316 5317def int_hexagon_V6_pred_or_n : 5318Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5319 5320def int_hexagon_V6_pred_or_n_128B : 5321Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5322 5323def int_hexagon_V6_pred_scalar2 : 5324Hexagon_custom_v64i1_i32_Intrinsic; 5325 5326def int_hexagon_V6_pred_scalar2_128B : 5327Hexagon_custom_v128i1_i32_Intrinsic_128B; 5328 5329def int_hexagon_V6_vmux : 5330Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5331 5332def int_hexagon_V6_vmux_128B : 5333Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5334 5335def int_hexagon_V6_vswap : 5336Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic; 5337 5338def int_hexagon_V6_vswap_128B : 5339Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B; 5340 5341def int_hexagon_V6_vmaxub : 5342Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; 5343 5344def int_hexagon_V6_vmaxub_128B : 5345Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; 5346 5347def int_hexagon_V6_vminub : 5348Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; 5349 5350def int_hexagon_V6_vminub_128B : 5351Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; 5352 5353def int_hexagon_V6_vmaxuh : 5354Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; 5355 5356def int_hexagon_V6_vmaxuh_128B : 5357Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; 5358 5359def int_hexagon_V6_vminuh : 5360Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; 5361 5362def int_hexagon_V6_vminuh_128B : 5363Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; 5364 5365def int_hexagon_V6_vmaxh : 5366Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; 5367 5368def int_hexagon_V6_vmaxh_128B : 5369Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; 5370 5371def int_hexagon_V6_vminh : 5372Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; 5373 5374def int_hexagon_V6_vminh_128B : 5375Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; 5376 5377def int_hexagon_V6_vmaxw : 5378Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; 5379 5380def int_hexagon_V6_vmaxw_128B : 5381Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; 5382 5383def int_hexagon_V6_vminw : 5384Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; 5385 5386def int_hexagon_V6_vminw_128B : 5387Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; 5388 5389def int_hexagon_V6_vsathub : 5390Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; 5391 5392def int_hexagon_V6_vsathub_128B : 5393Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">; 5394 5395def int_hexagon_V6_vsatwh : 5396Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; 5397 5398def int_hexagon_V6_vsatwh_128B : 5399Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; 5400 5401def int_hexagon_V6_vshuffeb : 5402Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; 5403 5404def int_hexagon_V6_vshuffeb_128B : 5405Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; 5406 5407def int_hexagon_V6_vshuffob : 5408Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; 5409 5410def int_hexagon_V6_vshuffob_128B : 5411Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; 5412 5413def int_hexagon_V6_vshufeh : 5414Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; 5415 5416def int_hexagon_V6_vshufeh_128B : 5417Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; 5418 5419def int_hexagon_V6_vshufoh : 5420Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; 5421 5422def int_hexagon_V6_vshufoh_128B : 5423Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; 5424 5425def int_hexagon_V6_vshuffvdd : 5426Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; 5427 5428def int_hexagon_V6_vshuffvdd_128B : 5429Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; 5430 5431def int_hexagon_V6_vdealvdd : 5432Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; 5433 5434def int_hexagon_V6_vdealvdd_128B : 5435Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; 5436 5437def int_hexagon_V6_vshufoeh : 5438Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; 5439 5440def int_hexagon_V6_vshufoeh_128B : 5441Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; 5442 5443def int_hexagon_V6_vshufoeb : 5444Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; 5445 5446def int_hexagon_V6_vshufoeb_128B : 5447Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; 5448 5449def int_hexagon_V6_vdealh : 5450Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; 5451 5452def int_hexagon_V6_vdealh_128B : 5453Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; 5454 5455def int_hexagon_V6_vdealb : 5456Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; 5457 5458def int_hexagon_V6_vdealb_128B : 5459Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; 5460 5461def int_hexagon_V6_vdealb4w : 5462Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; 5463 5464def int_hexagon_V6_vdealb4w_128B : 5465Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; 5466 5467def int_hexagon_V6_vshuffh : 5468Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; 5469 5470def int_hexagon_V6_vshuffh_128B : 5471Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; 5472 5473def int_hexagon_V6_vshuffb : 5474Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; 5475 5476def int_hexagon_V6_vshuffb_128B : 5477Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; 5478 5479def int_hexagon_V6_extractw : 5480Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; 5481 5482def int_hexagon_V6_extractw_128B : 5483Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; 5484 5485def int_hexagon_V6_vinsertwr : 5486Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; 5487 5488def int_hexagon_V6_vinsertwr_128B : 5489Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; 5490 5491def int_hexagon_V6_lvsplatw : 5492Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; 5493 5494def int_hexagon_V6_lvsplatw_128B : 5495Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; 5496 5497def int_hexagon_V6_vassignp : 5498Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; 5499 5500def int_hexagon_V6_vassignp_128B : 5501Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; 5502 5503def int_hexagon_V6_vassign : 5504Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; 5505 5506def int_hexagon_V6_vassign_128B : 5507Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; 5508 5509def int_hexagon_V6_vcombine : 5510Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; 5511 5512def int_hexagon_V6_vcombine_128B : 5513Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; 5514 5515def int_hexagon_V6_vdelta : 5516Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; 5517 5518def int_hexagon_V6_vdelta_128B : 5519Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; 5520 5521def int_hexagon_V6_vrdelta : 5522Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; 5523 5524def int_hexagon_V6_vrdelta_128B : 5525Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; 5526 5527def int_hexagon_V6_vcl0w : 5528Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; 5529 5530def int_hexagon_V6_vcl0w_128B : 5531Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; 5532 5533def int_hexagon_V6_vcl0h : 5534Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; 5535 5536def int_hexagon_V6_vcl0h_128B : 5537Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; 5538 5539def int_hexagon_V6_vnormamtw : 5540Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; 5541 5542def int_hexagon_V6_vnormamtw_128B : 5543Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; 5544 5545def int_hexagon_V6_vnormamth : 5546Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; 5547 5548def int_hexagon_V6_vnormamth_128B : 5549Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; 5550 5551def int_hexagon_V6_vpopcounth : 5552Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; 5553 5554def int_hexagon_V6_vpopcounth_128B : 5555Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; 5556 5557def int_hexagon_V6_vlutvvb : 5558Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; 5559 5560def int_hexagon_V6_vlutvvb_128B : 5561Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; 5562 5563def int_hexagon_V6_vlutvvb_oracc : 5564Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; 5565 5566def int_hexagon_V6_vlutvvb_oracc_128B : 5567Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; 5568 5569def int_hexagon_V6_vlutvwh : 5570Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; 5571 5572def int_hexagon_V6_vlutvwh_128B : 5573Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; 5574 5575def int_hexagon_V6_vlutvwh_oracc : 5576Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; 5577 5578def int_hexagon_V6_vlutvwh_oracc_128B : 5579Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; 5580 5581def int_hexagon_V6_hi : 5582Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; 5583 5584def int_hexagon_V6_hi_128B : 5585Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; 5586 5587def int_hexagon_V6_lo : 5588Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; 5589 5590def int_hexagon_V6_lo_128B : 5591Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; 5592 5593// V62 HVX Instructions. 5594 5595def int_hexagon_V6_vlsrb : 5596Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; 5597 5598def int_hexagon_V6_vlsrb_128B : 5599Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; 5600 5601def int_hexagon_V6_vasrwuhrndsat : 5602Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; 5603 5604def int_hexagon_V6_vasrwuhrndsat_128B : 5605Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; 5606 5607def int_hexagon_V6_vasruwuhrndsat : 5608Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; 5609 5610def int_hexagon_V6_vasruwuhrndsat_128B : 5611Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; 5612 5613def int_hexagon_V6_vasrhbsat : 5614Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; 5615 5616def int_hexagon_V6_vasrhbsat_128B : 5617Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; 5618 5619def int_hexagon_V6_vrounduwuh : 5620Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; 5621 5622def int_hexagon_V6_vrounduwuh_128B : 5623Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; 5624 5625def int_hexagon_V6_vrounduhub : 5626Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; 5627 5628def int_hexagon_V6_vrounduhub_128B : 5629Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; 5630 5631def int_hexagon_V6_vadduwsat : 5632Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; 5633 5634def int_hexagon_V6_vadduwsat_128B : 5635Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; 5636 5637def int_hexagon_V6_vadduwsat_dv : 5638Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; 5639 5640def int_hexagon_V6_vadduwsat_dv_128B : 5641Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; 5642 5643def int_hexagon_V6_vsubuwsat : 5644Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; 5645 5646def int_hexagon_V6_vsubuwsat_128B : 5647Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; 5648 5649def int_hexagon_V6_vsubuwsat_dv : 5650Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; 5651 5652def int_hexagon_V6_vsubuwsat_dv_128B : 5653Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; 5654 5655def int_hexagon_V6_vaddbsat : 5656Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; 5657 5658def int_hexagon_V6_vaddbsat_128B : 5659Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; 5660 5661def int_hexagon_V6_vaddbsat_dv : 5662Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; 5663 5664def int_hexagon_V6_vaddbsat_dv_128B : 5665Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; 5666 5667def int_hexagon_V6_vsubbsat : 5668Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; 5669 5670def int_hexagon_V6_vsubbsat_128B : 5671Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; 5672 5673def int_hexagon_V6_vsubbsat_dv : 5674Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; 5675 5676def int_hexagon_V6_vsubbsat_dv_128B : 5677Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; 5678 5679def int_hexagon_V6_vaddcarry : 5680Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5681 5682def int_hexagon_V6_vaddcarry_128B : 5683Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5684 5685def int_hexagon_V6_vsubcarry : 5686Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5687 5688def int_hexagon_V6_vsubcarry_128B : 5689Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5690 5691def int_hexagon_V6_vaddububb_sat : 5692Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; 5693 5694def int_hexagon_V6_vaddububb_sat_128B : 5695Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; 5696 5697def int_hexagon_V6_vsubububb_sat : 5698Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; 5699 5700def int_hexagon_V6_vsubububb_sat_128B : 5701Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; 5702 5703def int_hexagon_V6_vaddhw_acc : 5704Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; 5705 5706def int_hexagon_V6_vaddhw_acc_128B : 5707Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; 5708 5709def int_hexagon_V6_vadduhw_acc : 5710Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; 5711 5712def int_hexagon_V6_vadduhw_acc_128B : 5713Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; 5714 5715def int_hexagon_V6_vaddubh_acc : 5716Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; 5717 5718def int_hexagon_V6_vaddubh_acc_128B : 5719Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; 5720 5721def int_hexagon_V6_vmpyewuh_64 : 5722Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; 5723 5724def int_hexagon_V6_vmpyewuh_64_128B : 5725Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; 5726 5727def int_hexagon_V6_vmpyowh_64_acc : 5728Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; 5729 5730def int_hexagon_V6_vmpyowh_64_acc_128B : 5731Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; 5732 5733def int_hexagon_V6_vmpauhb : 5734Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; 5735 5736def int_hexagon_V6_vmpauhb_128B : 5737Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; 5738 5739def int_hexagon_V6_vmpauhb_acc : 5740Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; 5741 5742def int_hexagon_V6_vmpauhb_acc_128B : 5743Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; 5744 5745def int_hexagon_V6_vmpyiwub : 5746Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; 5747 5748def int_hexagon_V6_vmpyiwub_128B : 5749Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; 5750 5751def int_hexagon_V6_vmpyiwub_acc : 5752Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; 5753 5754def int_hexagon_V6_vmpyiwub_acc_128B : 5755Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; 5756 5757def int_hexagon_V6_vandnqrt : 5758Hexagon_custom_v16i32_v64i1i32_Intrinsic; 5759 5760def int_hexagon_V6_vandnqrt_128B : 5761Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; 5762 5763def int_hexagon_V6_vandnqrt_acc : 5764Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; 5765 5766def int_hexagon_V6_vandnqrt_acc_128B : 5767Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; 5768 5769def int_hexagon_V6_vandvqv : 5770Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; 5771 5772def int_hexagon_V6_vandvqv_128B : 5773Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; 5774 5775def int_hexagon_V6_vandvnqv : 5776Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; 5777 5778def int_hexagon_V6_vandvnqv_128B : 5779Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; 5780 5781def int_hexagon_V6_pred_scalar2v2 : 5782Hexagon_custom_v64i1_i32_Intrinsic; 5783 5784def int_hexagon_V6_pred_scalar2v2_128B : 5785Hexagon_custom_v128i1_i32_Intrinsic_128B; 5786 5787def int_hexagon_V6_shuffeqw : 5788Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5789 5790def int_hexagon_V6_shuffeqw_128B : 5791Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5792 5793def int_hexagon_V6_shuffeqh : 5794Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5795 5796def int_hexagon_V6_shuffeqh_128B : 5797Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5798 5799def int_hexagon_V6_vmaxb : 5800Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; 5801 5802def int_hexagon_V6_vmaxb_128B : 5803Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">; 5804 5805def int_hexagon_V6_vminb : 5806Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; 5807 5808def int_hexagon_V6_vminb_128B : 5809Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; 5810 5811def int_hexagon_V6_vsatuwuh : 5812Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; 5813 5814def int_hexagon_V6_vsatuwuh_128B : 5815Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; 5816 5817def int_hexagon_V6_lvsplath : 5818Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; 5819 5820def int_hexagon_V6_lvsplath_128B : 5821Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; 5822 5823def int_hexagon_V6_lvsplatb : 5824Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; 5825 5826def int_hexagon_V6_lvsplatb_128B : 5827Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; 5828 5829def int_hexagon_V6_vaddclbw : 5830Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; 5831 5832def int_hexagon_V6_vaddclbw_128B : 5833Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; 5834 5835def int_hexagon_V6_vaddclbh : 5836Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; 5837 5838def int_hexagon_V6_vaddclbh_128B : 5839Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; 5840 5841def int_hexagon_V6_vlutvvbi : 5842Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5843 5844def int_hexagon_V6_vlutvvbi_128B : 5845Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5846 5847def int_hexagon_V6_vlutvvb_oracci : 5848Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5849 5850def int_hexagon_V6_vlutvvb_oracci_128B : 5851Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5852 5853def int_hexagon_V6_vlutvwhi : 5854Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5855 5856def int_hexagon_V6_vlutvwhi_128B : 5857Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5858 5859def int_hexagon_V6_vlutvwh_oracci : 5860Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5861 5862def int_hexagon_V6_vlutvwh_oracci_128B : 5863Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5864 5865def int_hexagon_V6_vlutvvb_nm : 5866Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; 5867 5868def int_hexagon_V6_vlutvvb_nm_128B : 5869Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; 5870 5871def int_hexagon_V6_vlutvwh_nm : 5872Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; 5873 5874def int_hexagon_V6_vlutvwh_nm_128B : 5875Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; 5876 5877// V65 HVX Instructions. 5878 5879def int_hexagon_V6_vasruwuhsat : 5880Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; 5881 5882def int_hexagon_V6_vasruwuhsat_128B : 5883Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; 5884 5885def int_hexagon_V6_vasruhubsat : 5886Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; 5887 5888def int_hexagon_V6_vasruhubsat_128B : 5889Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; 5890 5891def int_hexagon_V6_vasruhubrndsat : 5892Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; 5893 5894def int_hexagon_V6_vasruhubrndsat_128B : 5895Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; 5896 5897def int_hexagon_V6_vaslh_acc : 5898Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; 5899 5900def int_hexagon_V6_vaslh_acc_128B : 5901Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; 5902 5903def int_hexagon_V6_vasrh_acc : 5904Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; 5905 5906def int_hexagon_V6_vasrh_acc_128B : 5907Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; 5908 5909def int_hexagon_V6_vavguw : 5910Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; 5911 5912def int_hexagon_V6_vavguw_128B : 5913Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; 5914 5915def int_hexagon_V6_vavguwrnd : 5916Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; 5917 5918def int_hexagon_V6_vavguwrnd_128B : 5919Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; 5920 5921def int_hexagon_V6_vavgb : 5922Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; 5923 5924def int_hexagon_V6_vavgb_128B : 5925Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; 5926 5927def int_hexagon_V6_vavgbrnd : 5928Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; 5929 5930def int_hexagon_V6_vavgbrnd_128B : 5931Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; 5932 5933def int_hexagon_V6_vnavgb : 5934Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; 5935 5936def int_hexagon_V6_vnavgb_128B : 5937Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; 5938 5939def int_hexagon_V6_vdd0 : 5940Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; 5941 5942def int_hexagon_V6_vdd0_128B : 5943Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; 5944 5945def int_hexagon_V6_vabsb : 5946Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; 5947 5948def int_hexagon_V6_vabsb_128B : 5949Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">; 5950 5951def int_hexagon_V6_vabsb_sat : 5952Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; 5953 5954def int_hexagon_V6_vabsb_sat_128B : 5955Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; 5956 5957def int_hexagon_V6_vmpabuu : 5958Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; 5959 5960def int_hexagon_V6_vmpabuu_128B : 5961Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; 5962 5963def int_hexagon_V6_vmpabuu_acc : 5964Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; 5965 5966def int_hexagon_V6_vmpabuu_acc_128B : 5967Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; 5968 5969def int_hexagon_V6_vmpyh_acc : 5970Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; 5971 5972def int_hexagon_V6_vmpyh_acc_128B : 5973Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; 5974 5975def int_hexagon_V6_vmpahhsat : 5976Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; 5977 5978def int_hexagon_V6_vmpahhsat_128B : 5979Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; 5980 5981def int_hexagon_V6_vmpauhuhsat : 5982Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; 5983 5984def int_hexagon_V6_vmpauhuhsat_128B : 5985Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; 5986 5987def int_hexagon_V6_vmpsuhuhsat : 5988Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; 5989 5990def int_hexagon_V6_vmpsuhuhsat_128B : 5991Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; 5992 5993def int_hexagon_V6_vlut4 : 5994Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; 5995 5996def int_hexagon_V6_vlut4_128B : 5997Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; 5998 5999def int_hexagon_V6_vmpyuhe : 6000Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; 6001 6002def int_hexagon_V6_vmpyuhe_128B : 6003Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; 6004 6005def int_hexagon_V6_vmpyuhe_acc : 6006Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; 6007 6008def int_hexagon_V6_vmpyuhe_acc_128B : 6009Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; 6010 6011def int_hexagon_V6_vgathermw : 6012Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; 6013 6014def int_hexagon_V6_vgathermw_128B : 6015Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; 6016 6017def int_hexagon_V6_vgathermh : 6018Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>; 6019 6020def int_hexagon_V6_vgathermh_128B : 6021Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; 6022 6023def int_hexagon_V6_vgathermhw : 6024Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; 6025 6026def int_hexagon_V6_vgathermhw_128B : 6027Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; 6028 6029def int_hexagon_V6_vgathermwq : 6030Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; 6031 6032def int_hexagon_V6_vgathermwq_128B : 6033Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; 6034 6035def int_hexagon_V6_vgathermhq : 6036Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; 6037 6038def int_hexagon_V6_vgathermhq_128B : 6039Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; 6040 6041def int_hexagon_V6_vgathermhwq : 6042Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic<[IntrArgMemOnly]>; 6043 6044def int_hexagon_V6_vgathermhwq_128B : 6045Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B<[IntrArgMemOnly]>; 6046 6047def int_hexagon_V6_vscattermw : 6048Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; 6049 6050def int_hexagon_V6_vscattermw_128B : 6051Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>; 6052 6053def int_hexagon_V6_vscattermh : 6054Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; 6055 6056def int_hexagon_V6_vscattermh_128B : 6057Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>; 6058 6059def int_hexagon_V6_vscattermw_add : 6060Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>; 6061 6062def int_hexagon_V6_vscattermw_add_128B : 6063Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; 6064 6065def int_hexagon_V6_vscattermh_add : 6066Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>; 6067 6068def int_hexagon_V6_vscattermh_add_128B : 6069Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; 6070 6071def int_hexagon_V6_vscattermwq : 6072Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; 6073 6074def int_hexagon_V6_vscattermwq_128B : 6075Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; 6076 6077def int_hexagon_V6_vscattermhq : 6078Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; 6079 6080def int_hexagon_V6_vscattermhq_128B : 6081Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; 6082 6083def int_hexagon_V6_vscattermhw : 6084Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; 6085 6086def int_hexagon_V6_vscattermhw_128B : 6087Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>; 6088 6089def int_hexagon_V6_vscattermhwq : 6090Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic<[IntrWriteMem]>; 6091 6092def int_hexagon_V6_vscattermhwq_128B : 6093Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B<[IntrWriteMem]>; 6094 6095def int_hexagon_V6_vscattermhw_add : 6096Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>; 6097 6098def int_hexagon_V6_vscattermhw_add_128B : 6099Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; 6100 6101def int_hexagon_V6_vprefixqb : 6102Hexagon_custom_v16i32_v64i1_Intrinsic; 6103 6104def int_hexagon_V6_vprefixqb_128B : 6105Hexagon_custom_v32i32_v128i1_Intrinsic_128B; 6106 6107def int_hexagon_V6_vprefixqh : 6108Hexagon_custom_v16i32_v64i1_Intrinsic; 6109 6110def int_hexagon_V6_vprefixqh_128B : 6111Hexagon_custom_v32i32_v128i1_Intrinsic_128B; 6112 6113def int_hexagon_V6_vprefixqw : 6114Hexagon_custom_v16i32_v64i1_Intrinsic; 6115 6116def int_hexagon_V6_vprefixqw_128B : 6117Hexagon_custom_v32i32_v128i1_Intrinsic_128B; 6118 6119// V66 HVX Instructions. 6120 6121def int_hexagon_V6_vrotr : 6122Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; 6123 6124def int_hexagon_V6_vrotr_128B : 6125Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; 6126 6127def int_hexagon_V6_vasr_into : 6128Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; 6129 6130def int_hexagon_V6_vasr_into_128B : 6131Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; 6132 6133def int_hexagon_V6_vaddcarrysat : 6134Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic; 6135 6136def int_hexagon_V6_vaddcarrysat_128B : 6137Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B; 6138 6139def int_hexagon_V6_vsatdw : 6140Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; 6141 6142def int_hexagon_V6_vsatdw_128B : 6143Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; 6144 6145