1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file declares the API of helper functions used throughout the 10 /// GlobalISel pipeline. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H 15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H 16 17 #include "GISelWorkList.h" 18 #include "LostDebugLocObserver.h" 19 #include "llvm/ADT/APFloat.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/CodeGen/MachineBasicBlock.h" 22 #include "llvm/CodeGen/Register.h" 23 #include "llvm/Support/Alignment.h" 24 #include "llvm/Support/LowLevelTypeImpl.h" 25 #include <cstdint> 26 27 namespace llvm { 28 29 class AnalysisUsage; 30 class BlockFrequencyInfo; 31 class GISelKnownBits; 32 class MachineFunction; 33 class MachineInstr; 34 class MachineOperand; 35 class MachineOptimizationRemarkEmitter; 36 class MachineOptimizationRemarkMissed; 37 struct MachinePointerInfo; 38 class MachineRegisterInfo; 39 class MCInstrDesc; 40 class ProfileSummaryInfo; 41 class RegisterBankInfo; 42 class TargetInstrInfo; 43 class TargetLowering; 44 class TargetPassConfig; 45 class TargetRegisterInfo; 46 class TargetRegisterClass; 47 class ConstantInt; 48 class ConstantFP; 49 class APFloat; 50 class MachineIRBuilder; 51 52 // Convenience macros for dealing with vector reduction opcodes. 53 #define GISEL_VECREDUCE_CASES_ALL \ 54 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \ 55 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \ 56 case TargetOpcode::G_VECREDUCE_FADD: \ 57 case TargetOpcode::G_VECREDUCE_FMUL: \ 58 case TargetOpcode::G_VECREDUCE_FMAX: \ 59 case TargetOpcode::G_VECREDUCE_FMIN: \ 60 case TargetOpcode::G_VECREDUCE_ADD: \ 61 case TargetOpcode::G_VECREDUCE_MUL: \ 62 case TargetOpcode::G_VECREDUCE_AND: \ 63 case TargetOpcode::G_VECREDUCE_OR: \ 64 case TargetOpcode::G_VECREDUCE_XOR: \ 65 case TargetOpcode::G_VECREDUCE_SMAX: \ 66 case TargetOpcode::G_VECREDUCE_SMIN: \ 67 case TargetOpcode::G_VECREDUCE_UMAX: \ 68 case TargetOpcode::G_VECREDUCE_UMIN: 69 70 #define GISEL_VECREDUCE_CASES_NONSEQ \ 71 case TargetOpcode::G_VECREDUCE_FADD: \ 72 case TargetOpcode::G_VECREDUCE_FMUL: \ 73 case TargetOpcode::G_VECREDUCE_FMAX: \ 74 case TargetOpcode::G_VECREDUCE_FMIN: \ 75 case TargetOpcode::G_VECREDUCE_ADD: \ 76 case TargetOpcode::G_VECREDUCE_MUL: \ 77 case TargetOpcode::G_VECREDUCE_AND: \ 78 case TargetOpcode::G_VECREDUCE_OR: \ 79 case TargetOpcode::G_VECREDUCE_XOR: \ 80 case TargetOpcode::G_VECREDUCE_SMAX: \ 81 case TargetOpcode::G_VECREDUCE_SMIN: \ 82 case TargetOpcode::G_VECREDUCE_UMAX: \ 83 case TargetOpcode::G_VECREDUCE_UMIN: 84 85 /// Try to constrain Reg to the specified register class. If this fails, 86 /// create a new virtual register in the correct class. 87 /// 88 /// \return The virtual register constrained to the right register class. 89 Register constrainRegToClass(MachineRegisterInfo &MRI, 90 const TargetInstrInfo &TII, 91 const RegisterBankInfo &RBI, Register Reg, 92 const TargetRegisterClass &RegClass); 93 94 /// Constrain the Register operand OpIdx, so that it is now constrained to the 95 /// TargetRegisterClass passed as an argument (RegClass). 96 /// If this fails, create a new virtual register in the correct class and insert 97 /// a COPY before \p InsertPt if it is a use or after if it is a definition. 98 /// In both cases, the function also updates the register of RegMo. The debug 99 /// location of \p InsertPt is used for the new copy. 100 /// 101 /// \return The virtual register constrained to the right register class. 102 Register constrainOperandRegClass(const MachineFunction &MF, 103 const TargetRegisterInfo &TRI, 104 MachineRegisterInfo &MRI, 105 const TargetInstrInfo &TII, 106 const RegisterBankInfo &RBI, 107 MachineInstr &InsertPt, 108 const TargetRegisterClass &RegClass, 109 MachineOperand &RegMO); 110 111 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided 112 /// MCInstrDesc \p II. If this fails, create a new virtual register in the 113 /// correct class and insert a COPY before \p InsertPt if it is a use or after 114 /// if it is a definition. In both cases, the function also updates the register 115 /// of RegMo. 116 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...) 117 /// with RegClass obtained from the MCInstrDesc. The debug location of \p 118 /// InsertPt is used for the new copy. 119 /// 120 /// \return The virtual register constrained to the right register class. 121 Register constrainOperandRegClass(const MachineFunction &MF, 122 const TargetRegisterInfo &TRI, 123 MachineRegisterInfo &MRI, 124 const TargetInstrInfo &TII, 125 const RegisterBankInfo &RBI, 126 MachineInstr &InsertPt, const MCInstrDesc &II, 127 MachineOperand &RegMO, unsigned OpIdx); 128 129 /// Mutate the newly-selected instruction \p I to constrain its (possibly 130 /// generic) virtual register operands to the instruction's register class. 131 /// This could involve inserting COPYs before (for uses) or after (for defs). 132 /// This requires the number of operands to match the instruction description. 133 /// \returns whether operand regclass constraining succeeded. 134 /// 135 // FIXME: Not all instructions have the same number of operands. We should 136 // probably expose a constrain helper per operand and let the target selector 137 // constrain individual registers, like fast-isel. 138 bool constrainSelectedInstRegOperands(MachineInstr &I, 139 const TargetInstrInfo &TII, 140 const TargetRegisterInfo &TRI, 141 const RegisterBankInfo &RBI); 142 143 /// Check if DstReg can be replaced with SrcReg depending on the register 144 /// constraints. 145 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI); 146 147 /// Check whether an instruction \p MI is dead: it only defines dead virtual 148 /// registers, and doesn't have other side effects. 149 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI); 150 151 /// Report an ISel error as a missed optimization remark to the LLVMContext's 152 /// diagnostic stream. Set the FailedISel MachineFunction property. 153 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 154 MachineOptimizationRemarkEmitter &MORE, 155 MachineOptimizationRemarkMissed &R); 156 157 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 158 MachineOptimizationRemarkEmitter &MORE, 159 const char *PassName, StringRef Msg, 160 const MachineInstr &MI); 161 162 /// Report an ISel warning as a missed optimization remark to the LLVMContext's 163 /// diagnostic stream. 164 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 165 MachineOptimizationRemarkEmitter &MORE, 166 MachineOptimizationRemarkMissed &R); 167 168 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value. 169 Optional<APInt> getIConstantVRegVal(Register VReg, 170 const MachineRegisterInfo &MRI); 171 172 /// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it. 173 Optional<int64_t> getIConstantVRegSExtVal(Register VReg, 174 const MachineRegisterInfo &MRI); 175 176 /// Simple struct used to hold a constant integer value and a virtual 177 /// register. 178 struct ValueAndVReg { 179 APInt Value; 180 Register VReg; 181 }; 182 183 /// If \p VReg is defined by a statically evaluable chain of instructions rooted 184 /// on a G_CONSTANT returns its APInt value and def register. 185 Optional<ValueAndVReg> 186 getIConstantVRegValWithLookThrough(Register VReg, 187 const MachineRegisterInfo &MRI, 188 bool LookThroughInstrs = true); 189 190 /// If \p VReg is defined by a statically evaluable chain of instructions rooted 191 /// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register. 192 Optional<ValueAndVReg> getAnyConstantVRegValWithLookThrough( 193 Register VReg, const MachineRegisterInfo &MRI, 194 bool LookThroughInstrs = true, bool LookThroughAnyExt = false); 195 196 struct FPValueAndVReg { 197 APFloat Value; 198 Register VReg; 199 }; 200 201 /// If \p VReg is defined by a statically evaluable chain of instructions rooted 202 /// on a G_FCONSTANT returns its APFloat value and def register. 203 Optional<FPValueAndVReg> 204 getFConstantVRegValWithLookThrough(Register VReg, 205 const MachineRegisterInfo &MRI, 206 bool LookThroughInstrs = true); 207 208 const ConstantFP* getConstantFPVRegVal(Register VReg, 209 const MachineRegisterInfo &MRI); 210 211 /// See if Reg is defined by an single def instruction that is 212 /// Opcode. Also try to do trivial folding if it's a COPY with 213 /// same types. Returns null otherwise. 214 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg, 215 const MachineRegisterInfo &MRI); 216 217 /// Simple struct used to hold a Register value and the instruction which 218 /// defines it. 219 struct DefinitionAndSourceRegister { 220 MachineInstr *MI; 221 Register Reg; 222 }; 223 224 /// Find the def instruction for \p Reg, and underlying value Register folding 225 /// away any copies. 226 /// 227 /// Also walks through hints such as G_ASSERT_ZEXT. 228 Optional<DefinitionAndSourceRegister> 229 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI); 230 231 /// Find the def instruction for \p Reg, folding away any trivial copies. May 232 /// return nullptr if \p Reg is not a generic virtual register. 233 /// 234 /// Also walks through hints such as G_ASSERT_ZEXT. 235 MachineInstr *getDefIgnoringCopies(Register Reg, 236 const MachineRegisterInfo &MRI); 237 238 /// Find the source register for \p Reg, folding away any trivial copies. It 239 /// will be an output register of the instruction that getDefIgnoringCopies 240 /// returns. May return an invalid register if \p Reg is not a generic virtual 241 /// register. 242 /// 243 /// Also walks through hints such as G_ASSERT_ZEXT. 244 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI); 245 246 // Templated variant of getOpcodeDef returning a MachineInstr derived T. 247 /// See if Reg is defined by an single def instruction of type T 248 /// Also try to do trivial folding if it's a COPY with 249 /// same types. Returns null otherwise. 250 template <class T> 251 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { 252 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); 253 return dyn_cast_or_null<T>(DefMI); 254 } 255 256 /// Returns an APFloat from Val converted to the appropriate size. 257 APFloat getAPFloatFromSize(double Val, unsigned Size); 258 259 /// Modify analysis usage so it preserves passes required for the SelectionDAG 260 /// fallback. 261 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU); 262 263 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1, 264 const Register Op2, 265 const MachineRegisterInfo &MRI); 266 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, 267 const Register Op2, 268 const MachineRegisterInfo &MRI); 269 270 /// Tries to constant fold a vector binop with sources \p Op1 and \p Op2. 271 /// If successful, returns the G_BUILD_VECTOR representing the folded vector 272 /// constant. \p MIB should have an insertion point already set to create new 273 /// G_CONSTANT instructions as needed. 274 Optional<MachineInstr *> 275 ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, 276 const MachineRegisterInfo &MRI, MachineIRBuilder &MIB); 277 278 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1, 279 uint64_t Imm, const MachineRegisterInfo &MRI); 280 281 Optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, 282 Register Src, 283 const MachineRegisterInfo &MRI); 284 285 /// Tries to constant fold a G_CTLZ operation on \p Src. If \p Src is a vector 286 /// then it tries to do an element-wise constant fold. 287 Optional<SmallVector<unsigned>> 288 ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI); 289 290 /// Test if the given value is known to have exactly one bit set. This differs 291 /// from computeKnownBits in that it doesn't necessarily determine which bit is 292 /// set. 293 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI, 294 GISelKnownBits *KnownBits = nullptr); 295 296 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true, 297 /// this returns if \p Val can be assumed to never be a signaling NaN. 298 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 299 bool SNaN = false); 300 301 /// Returns true if \p Val can be assumed to never be a signaling NaN. 302 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) { 303 return isKnownNeverNaN(Val, MRI, true); 304 } 305 306 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO); 307 308 /// Return a virtual register corresponding to the incoming argument register \p 309 /// PhysReg. This register is expected to have class \p RC, and optional type \p 310 /// RegTy. This assumes all references to the register will use the same type. 311 /// 312 /// If there is an existing live-in argument register, it will be returned. 313 /// This will also ensure there is a valid copy 314 Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, 315 MCRegister PhysReg, 316 const TargetRegisterClass &RC, 317 LLT RegTy = LLT()); 318 319 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the 320 /// number of vector elements or scalar bitwidth. The intent is a 321 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from 322 /// \p OrigTy elements, and unmerged into \p TargetTy 323 LLVM_READNONE 324 LLT getLCMType(LLT OrigTy, LLT TargetTy); 325 326 /// Return a type where the total size is the greatest common divisor of \p 327 /// OrigTy and \p TargetTy. This will try to either change the number of vector 328 /// elements, or bitwidth of scalars. The intent is the result type can be used 329 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some 330 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly 331 /// with intermediate casts) can re-form \p TargetTy. 332 /// 333 /// If these are vectors with different element types, this will try to produce 334 /// a vector with a compatible total size, but the element type of \p OrigTy. If 335 /// this can't be satisfied, this will produce a scalar smaller than the 336 /// original vector elements. 337 /// 338 /// In the worst case, this returns LLT::scalar(1) 339 LLVM_READNONE 340 LLT getGCDType(LLT OrigTy, LLT TargetTy); 341 342 /// Represents a value which can be a Register or a constant. 343 /// 344 /// This is useful in situations where an instruction may have an interesting 345 /// register operand or interesting constant operand. For a concrete example, 346 /// \see getVectorSplat. 347 class RegOrConstant { 348 int64_t Cst; 349 Register Reg; 350 bool IsReg; 351 352 public: 353 explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {} 354 explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {} 355 bool isReg() const { return IsReg; } 356 bool isCst() const { return !IsReg; } 357 Register getReg() const { 358 assert(isReg() && "Expected a register!"); 359 return Reg; 360 } 361 int64_t getCst() const { 362 assert(isCst() && "Expected a constant!"); 363 return Cst; 364 } 365 }; 366 367 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat. 368 /// If \p MI is not a splat, returns None. 369 Optional<int> getSplatIndex(MachineInstr &MI); 370 371 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists. 372 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI, 373 const MachineRegisterInfo &MRI); 374 375 /// Returns a floating point scalar constant of a build vector splat if it 376 /// exists. When \p AllowUndef == true some elements can be undef but not all. 377 Optional<FPValueAndVReg> getFConstantSplat(Register VReg, 378 const MachineRegisterInfo &MRI, 379 bool AllowUndef = true); 380 381 /// Return true if the specified instruction is a G_BUILD_VECTOR or 382 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef. 383 bool isBuildVectorAllZeros(const MachineInstr &MI, 384 const MachineRegisterInfo &MRI, 385 bool AllowUndef = false); 386 387 /// Return true if the specified instruction is a G_BUILD_VECTOR or 388 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef. 389 bool isBuildVectorAllOnes(const MachineInstr &MI, 390 const MachineRegisterInfo &MRI, 391 bool AllowUndef = false); 392 393 /// \returns a value when \p MI is a vector splat. The splat can be either a 394 /// Register or a constant. 395 /// 396 /// Examples: 397 /// 398 /// \code 399 /// %reg = COPY $physreg 400 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg 401 /// \endcode 402 /// 403 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant 404 /// containing %reg. 405 /// 406 /// \code 407 /// %cst = G_CONSTANT iN 4 408 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst 409 /// \endcode 410 /// 411 /// In the above case, this will return a RegOrConstant containing 4. 412 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI, 413 const MachineRegisterInfo &MRI); 414 415 /// Determines if \p MI defines a constant integer or a build vector of 416 /// constant integers. Treats undef values as constants. 417 bool isConstantOrConstantVector(MachineInstr &MI, 418 const MachineRegisterInfo &MRI); 419 420 /// Determines if \p MI defines a constant integer or a splat vector of 421 /// constant integers. 422 /// \returns the scalar constant or None. 423 Optional<APInt> isConstantOrConstantSplatVector(MachineInstr &MI, 424 const MachineRegisterInfo &MRI); 425 426 /// Attempt to match a unary predicate against a scalar/splat constant or every 427 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source 428 /// value was undef. 429 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, 430 std::function<bool(const Constant *ConstVal)> Match, 431 bool AllowUndefs = false); 432 433 /// Returns true if given the TargetLowering's boolean contents information, 434 /// the value \p Val contains a true value. 435 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, 436 bool IsFP); 437 438 /// Returns an integer representing true, as defined by the 439 /// TargetBooleanContents. 440 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP); 441 442 /// Returns true if the given block should be optimized for size. 443 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, 444 BlockFrequencyInfo *BFI); 445 446 using SmallInstListTy = GISelWorkList<4>; 447 void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, 448 LostDebugLocObserver *LocObserver, 449 SmallInstListTy &DeadInstChain); 450 void eraseInstrs(ArrayRef<MachineInstr *> DeadInstrs, MachineRegisterInfo &MRI, 451 LostDebugLocObserver *LocObserver = nullptr); 452 void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, 453 LostDebugLocObserver *LocObserver = nullptr); 454 455 } // End namespace llvm. 456 #endif 457