1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/NameMatches.h" 13 #include "lldb/Utility/Stream.h" 14 #include "lldb/Utility/StringList.h" 15 #include "lldb/lldb-defines.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/BinaryFormat/COFF.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/Host.h" 23 24 using namespace lldb; 25 using namespace lldb_private; 26 27 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 28 bool try_inverse, bool enforce_exact_match); 29 30 namespace lldb_private { 31 32 struct CoreDefinition { 33 ByteOrder default_byte_order; 34 uint32_t addr_byte_size; 35 uint32_t min_opcode_byte_size; 36 uint32_t max_opcode_byte_size; 37 llvm::Triple::ArchType machine; 38 ArchSpec::Core core; 39 const char *const name; 40 }; 41 42 } // namespace lldb_private 43 44 // This core information can be looked using the ArchSpec::Core as the index 45 static const CoreDefinition g_core_definitions[] = { 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 47 "arm"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 49 "armv4"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 51 "armv4t"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 53 "armv5"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 55 "armv5e"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 57 "armv5t"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 59 "armv6"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 61 "armv6m"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 63 "armv7"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_aarch64, "aarch64"}, 106 107 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 108 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 109 "mips"}, 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 111 "mipsr2"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 113 "mipsr3"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 115 "mipsr5"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 117 "mipsr6"}, 118 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 119 "mipsel"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 121 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 128 129 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 130 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 131 "mips64"}, 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 133 "mips64r2"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 135 "mips64r3"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 137 "mips64r5"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 139 "mips64r6"}, 140 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 141 ArchSpec::eCore_mips64el, "mips64el"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 150 151 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 152 "powerpc"}, 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 154 "ppc601"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 156 "ppc602"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 158 "ppc603"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 160 "ppc603e"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 162 "ppc603ev"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 164 "ppc604"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 166 "ppc604e"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 168 "ppc620"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 170 "ppc750"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 172 "ppc7400"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 174 "ppc7450"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 176 "ppc970"}, 177 178 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 179 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 180 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 181 "powerpc64"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 183 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 184 185 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 186 ArchSpec::eCore_s390x_generic, "s390x"}, 187 188 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 189 ArchSpec::eCore_sparc_generic, "sparc"}, 190 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 191 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 192 193 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 194 "i386"}, 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 196 "i486"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 198 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 200 "i686"}, 201 202 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 203 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 206 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 207 ArchSpec::eCore_hexagon_generic, "hexagon"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 212 213 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 214 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 215 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 217 }; 218 219 // Ensure that we have an entry in the g_core_definitions for each core. If you 220 // comment out an entry above, you will need to comment out the corresponding 221 // ArchSpec::Core enumeration. 222 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 223 ArchSpec::kNumCores, 224 "make sure we have one core definition for each core"); 225 226 struct ArchDefinitionEntry { 227 ArchSpec::Core core; 228 uint32_t cpu; 229 uint32_t sub; 230 uint32_t cpu_mask; 231 uint32_t sub_mask; 232 }; 233 234 struct ArchDefinition { 235 ArchitectureType type; 236 size_t num_entries; 237 const ArchDefinitionEntry *entries; 238 const char *name; 239 }; 240 241 void ArchSpec::ListSupportedArchNames(StringList &list) { 242 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 243 list.AppendString(g_core_definitions[i].name); 244 } 245 246 size_t ArchSpec::AutoComplete(CompletionRequest &request) { 247 if (!request.GetCursorArgumentPrefix().empty()) { 248 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 249 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, 250 request.GetCursorArgumentPrefix())) 251 request.AddCompletion(g_core_definitions[i].name); 252 } 253 } else { 254 StringList matches; 255 ListSupportedArchNames(matches); 256 request.AddCompletions(matches); 257 } 258 return request.GetNumberOfMatches(); 259 } 260 261 #define CPU_ANY (UINT32_MAX) 262 263 //===----------------------------------------------------------------------===// 264 // A table that gets searched linearly for matches. This table is used to 265 // convert cpu type and subtypes to architecture names, and to convert 266 // architecture names to cpu types and subtypes. The ordering is important and 267 // allows the precedence to be set when the table is built. 268 #define SUBTYPE_MASK 0x00FFFFFFu 269 270 static const ArchDefinitionEntry g_macho_arch_entries[] = { 271 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 272 UINT32_MAX, UINT32_MAX}, 273 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 310 UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 312 SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 336 UINT32_MAX, UINT32_MAX}, 337 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 364 UINT32_MAX, SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 366 UINT32_MAX, SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 368 UINT32_MAX, SUBTYPE_MASK}, 369 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 370 SUBTYPE_MASK}, 371 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 372 SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 374 UINT32_MAX, SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 376 UINT32_MAX, UINT32_MAX}, 377 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 378 SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 380 SUBTYPE_MASK}, 381 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 382 UINT32_MAX, SUBTYPE_MASK}, 383 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 384 UINT32_MAX, UINT32_MAX}, 385 // Catch any unknown mach architectures so we can always use the object and 386 // symbol mach-o files 387 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 388 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 389 0x00000000u}}; 390 391 static const ArchDefinition g_macho_arch_def = { 392 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 393 g_macho_arch_entries, "mach-o"}; 394 395 //===----------------------------------------------------------------------===// 396 // A table that gets searched linearly for matches. This table is used to 397 // convert cpu type and subtypes to architecture names, and to convert 398 // architecture names to cpu types and subtypes. The ordering is important and 399 // allows the precedence to be set when the table is built. 400 static const ArchDefinitionEntry g_elf_arch_entries[] = { 401 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 402 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 403 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 404 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 405 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 407 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 409 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 411 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 413 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 415 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 417 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 419 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 420 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 421 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 423 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 424 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 425 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 426 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 427 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 428 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 429 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 431 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 433 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 435 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 436 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 437 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 439 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 440 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 441 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 443 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 445 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 447 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 448 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 449 }; 450 451 static const ArchDefinition g_elf_arch_def = { 452 eArchTypeELF, 453 llvm::array_lengthof(g_elf_arch_entries), 454 g_elf_arch_entries, 455 "elf", 456 }; 457 458 static const ArchDefinitionEntry g_coff_arch_entries[] = { 459 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 460 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 461 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 462 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 463 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 464 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 465 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 466 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 467 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 469 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 471 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 473 }; 474 475 static const ArchDefinition g_coff_arch_def = { 476 eArchTypeCOFF, 477 llvm::array_lengthof(g_coff_arch_entries), 478 g_coff_arch_entries, 479 "pe-coff", 480 }; 481 482 //===----------------------------------------------------------------------===// 483 // Table of all ArchDefinitions 484 static const ArchDefinition *g_arch_definitions[] = { 485 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 486 487 static const size_t k_num_arch_definitions = 488 llvm::array_lengthof(g_arch_definitions); 489 490 //===----------------------------------------------------------------------===// 491 // Static helper functions. 492 493 // Get the architecture definition for a given object type. 494 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 495 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 496 const ArchDefinition *def = g_arch_definitions[i]; 497 if (def->type == arch_type) 498 return def; 499 } 500 return nullptr; 501 } 502 503 // Get an architecture definition by name. 504 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 505 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 506 if (name.equals_lower(g_core_definitions[i].name)) 507 return &g_core_definitions[i]; 508 } 509 return nullptr; 510 } 511 512 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 513 if (core < llvm::array_lengthof(g_core_definitions)) 514 return &g_core_definitions[core]; 515 return nullptr; 516 } 517 518 // Get a definition entry by cpu type and subtype. 519 static const ArchDefinitionEntry * 520 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 521 if (def == nullptr) 522 return nullptr; 523 524 const ArchDefinitionEntry *entries = def->entries; 525 for (size_t i = 0; i < def->num_entries; ++i) { 526 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 527 if (entries[i].sub == (sub & entries[i].sub_mask)) 528 return &entries[i]; 529 } 530 return nullptr; 531 } 532 533 static const ArchDefinitionEntry * 534 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 535 if (def == nullptr) 536 return nullptr; 537 538 const ArchDefinitionEntry *entries = def->entries; 539 for (size_t i = 0; i < def->num_entries; ++i) { 540 if (entries[i].core == core) 541 return &entries[i]; 542 } 543 return nullptr; 544 } 545 546 //===----------------------------------------------------------------------===// 547 // Constructors and destructors. 548 549 ArchSpec::ArchSpec() {} 550 551 ArchSpec::ArchSpec(const char *triple_cstr) { 552 if (triple_cstr) 553 SetTriple(triple_cstr); 554 } 555 556 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 557 558 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 559 560 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 561 SetArchitecture(arch_type, cpu, subtype); 562 } 563 564 ArchSpec::~ArchSpec() = default; 565 566 //===----------------------------------------------------------------------===// 567 // Assignment and initialization. 568 569 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 570 if (this != &rhs) { 571 m_triple = rhs.m_triple; 572 m_core = rhs.m_core; 573 m_byte_order = rhs.m_byte_order; 574 m_distribution_id = rhs.m_distribution_id; 575 m_flags = rhs.m_flags; 576 } 577 return *this; 578 } 579 580 void ArchSpec::Clear() { 581 m_triple = llvm::Triple(); 582 m_core = kCore_invalid; 583 m_byte_order = eByteOrderInvalid; 584 m_distribution_id.Clear(); 585 m_flags = 0; 586 } 587 588 //===----------------------------------------------------------------------===// 589 // Predicates. 590 591 const char *ArchSpec::GetArchitectureName() const { 592 const CoreDefinition *core_def = FindCoreDefinition(m_core); 593 if (core_def) 594 return core_def->name; 595 return "unknown"; 596 } 597 598 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 599 600 std::string ArchSpec::GetTargetABI() const { 601 602 std::string abi; 603 604 if (IsMIPS()) { 605 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 606 case ArchSpec::eMIPSABI_N64: 607 abi = "n64"; 608 return abi; 609 case ArchSpec::eMIPSABI_N32: 610 abi = "n32"; 611 return abi; 612 case ArchSpec::eMIPSABI_O32: 613 abi = "o32"; 614 return abi; 615 default: 616 return abi; 617 } 618 } 619 return abi; 620 } 621 622 void ArchSpec::SetFlags(std::string elf_abi) { 623 624 uint32_t flag = GetFlags(); 625 if (IsMIPS()) { 626 if (elf_abi == "n64") 627 flag |= ArchSpec::eMIPSABI_N64; 628 else if (elf_abi == "n32") 629 flag |= ArchSpec::eMIPSABI_N32; 630 else if (elf_abi == "o32") 631 flag |= ArchSpec::eMIPSABI_O32; 632 } 633 SetFlags(flag); 634 } 635 636 std::string ArchSpec::GetClangTargetCPU() const { 637 std::string cpu; 638 639 if (IsMIPS()) { 640 switch (m_core) { 641 case ArchSpec::eCore_mips32: 642 case ArchSpec::eCore_mips32el: 643 cpu = "mips32"; 644 break; 645 case ArchSpec::eCore_mips32r2: 646 case ArchSpec::eCore_mips32r2el: 647 cpu = "mips32r2"; 648 break; 649 case ArchSpec::eCore_mips32r3: 650 case ArchSpec::eCore_mips32r3el: 651 cpu = "mips32r3"; 652 break; 653 case ArchSpec::eCore_mips32r5: 654 case ArchSpec::eCore_mips32r5el: 655 cpu = "mips32r5"; 656 break; 657 case ArchSpec::eCore_mips32r6: 658 case ArchSpec::eCore_mips32r6el: 659 cpu = "mips32r6"; 660 break; 661 case ArchSpec::eCore_mips64: 662 case ArchSpec::eCore_mips64el: 663 cpu = "mips64"; 664 break; 665 case ArchSpec::eCore_mips64r2: 666 case ArchSpec::eCore_mips64r2el: 667 cpu = "mips64r2"; 668 break; 669 case ArchSpec::eCore_mips64r3: 670 case ArchSpec::eCore_mips64r3el: 671 cpu = "mips64r3"; 672 break; 673 case ArchSpec::eCore_mips64r5: 674 case ArchSpec::eCore_mips64r5el: 675 cpu = "mips64r5"; 676 break; 677 case ArchSpec::eCore_mips64r6: 678 case ArchSpec::eCore_mips64r6el: 679 cpu = "mips64r6"; 680 break; 681 default: 682 break; 683 } 684 } 685 return cpu; 686 } 687 688 uint32_t ArchSpec::GetMachOCPUType() const { 689 const CoreDefinition *core_def = FindCoreDefinition(m_core); 690 if (core_def) { 691 const ArchDefinitionEntry *arch_def = 692 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 693 if (arch_def) { 694 return arch_def->cpu; 695 } 696 } 697 return LLDB_INVALID_CPUTYPE; 698 } 699 700 uint32_t ArchSpec::GetMachOCPUSubType() const { 701 const CoreDefinition *core_def = FindCoreDefinition(m_core); 702 if (core_def) { 703 const ArchDefinitionEntry *arch_def = 704 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 705 if (arch_def) { 706 return arch_def->sub; 707 } 708 } 709 return LLDB_INVALID_CPUTYPE; 710 } 711 712 uint32_t ArchSpec::GetDataByteSize() const { 713 return 1; 714 } 715 716 uint32_t ArchSpec::GetCodeByteSize() const { 717 return 1; 718 } 719 720 llvm::Triple::ArchType ArchSpec::GetMachine() const { 721 const CoreDefinition *core_def = FindCoreDefinition(m_core); 722 if (core_def) 723 return core_def->machine; 724 725 return llvm::Triple::UnknownArch; 726 } 727 728 ConstString ArchSpec::GetDistributionId() const { 729 return m_distribution_id; 730 } 731 732 void ArchSpec::SetDistributionId(const char *distribution_id) { 733 m_distribution_id.SetCString(distribution_id); 734 } 735 736 uint32_t ArchSpec::GetAddressByteSize() const { 737 const CoreDefinition *core_def = FindCoreDefinition(m_core); 738 if (core_def) { 739 if (core_def->machine == llvm::Triple::mips64 || 740 core_def->machine == llvm::Triple::mips64el) { 741 // For N32/O32 applications Address size is 4 bytes. 742 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 743 return 4; 744 } 745 return core_def->addr_byte_size; 746 } 747 return 0; 748 } 749 750 ByteOrder ArchSpec::GetDefaultEndian() const { 751 const CoreDefinition *core_def = FindCoreDefinition(m_core); 752 if (core_def) 753 return core_def->default_byte_order; 754 return eByteOrderInvalid; 755 } 756 757 bool ArchSpec::CharIsSignedByDefault() const { 758 switch (m_triple.getArch()) { 759 default: 760 return true; 761 762 case llvm::Triple::aarch64: 763 case llvm::Triple::aarch64_be: 764 case llvm::Triple::arm: 765 case llvm::Triple::armeb: 766 case llvm::Triple::thumb: 767 case llvm::Triple::thumbeb: 768 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 769 770 case llvm::Triple::ppc: 771 case llvm::Triple::ppc64: 772 return m_triple.isOSDarwin(); 773 774 case llvm::Triple::ppc64le: 775 case llvm::Triple::systemz: 776 case llvm::Triple::xcore: 777 case llvm::Triple::arc: 778 return false; 779 } 780 } 781 782 lldb::ByteOrder ArchSpec::GetByteOrder() const { 783 if (m_byte_order == eByteOrderInvalid) 784 return GetDefaultEndian(); 785 return m_byte_order; 786 } 787 788 //===----------------------------------------------------------------------===// 789 // Mutators. 790 791 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 792 m_triple = triple; 793 UpdateCore(); 794 return IsValid(); 795 } 796 797 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 798 ArchSpec &arch) { 799 // Accept "12-10" or "12.10" as cpu type/subtype 800 if (triple_str.empty()) 801 return false; 802 803 size_t pos = triple_str.find_first_of("-."); 804 if (pos == llvm::StringRef::npos) 805 return false; 806 807 llvm::StringRef cpu_str = triple_str.substr(0, pos); 808 llvm::StringRef remainder = triple_str.substr(pos + 1); 809 if (cpu_str.empty() || remainder.empty()) 810 return false; 811 812 llvm::StringRef sub_str; 813 llvm::StringRef vendor; 814 llvm::StringRef os; 815 std::tie(sub_str, remainder) = remainder.split('-'); 816 std::tie(vendor, os) = remainder.split('-'); 817 818 uint32_t cpu = 0; 819 uint32_t sub = 0; 820 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 821 return false; 822 823 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 824 return false; 825 if (!vendor.empty() && !os.empty()) { 826 arch.GetTriple().setVendorName(vendor); 827 arch.GetTriple().setOSName(os); 828 } 829 830 return true; 831 } 832 833 bool ArchSpec::SetTriple(llvm::StringRef triple) { 834 if (triple.empty()) { 835 Clear(); 836 return false; 837 } 838 839 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 840 return true; 841 842 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 843 return IsValid(); 844 } 845 846 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 847 return !normalized_triple.getArchName().empty() && 848 normalized_triple.getOSName().empty() && 849 normalized_triple.getVendorName().empty() && 850 normalized_triple.getEnvironmentName().empty(); 851 } 852 853 void ArchSpec::MergeFrom(const ArchSpec &other) { 854 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 855 GetTriple().setVendor(other.GetTriple().getVendor()); 856 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 857 GetTriple().setOS(other.GetTriple().getOS()); 858 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 859 GetTriple().setArch(other.GetTriple().getArch()); 860 861 // MachO unknown64 isn't really invalid as the debugger can still obtain 862 // information from the binary, e.g. line tables. As such, we don't update 863 // the core here. 864 if (other.GetCore() != eCore_uknownMach64) 865 UpdateCore(); 866 } 867 if (!TripleEnvironmentWasSpecified() && 868 other.TripleEnvironmentWasSpecified()) { 869 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 870 } 871 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 872 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 873 // adopt the specific arm core. 874 if (GetTriple().getArch() == llvm::Triple::arm && 875 other.GetTriple().getArch() == llvm::Triple::arm && 876 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 877 other.GetCore() != ArchSpec::eCore_arm_generic) { 878 m_core = other.GetCore(); 879 CoreUpdated(true); 880 } 881 if (GetFlags() == 0) { 882 SetFlags(other.GetFlags()); 883 } 884 } 885 886 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 887 uint32_t sub, uint32_t os) { 888 m_core = kCore_invalid; 889 bool update_triple = true; 890 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 891 if (arch_def) { 892 const ArchDefinitionEntry *arch_def_entry = 893 FindArchDefinitionEntry(arch_def, cpu, sub); 894 if (arch_def_entry) { 895 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 896 if (core_def) { 897 m_core = core_def->core; 898 update_triple = false; 899 // Always use the architecture name because it might be more 900 // descriptive than the architecture enum ("armv7" -> 901 // llvm::Triple::arm). 902 m_triple.setArchName(llvm::StringRef(core_def->name)); 903 if (arch_type == eArchTypeMachO) { 904 m_triple.setVendor(llvm::Triple::Apple); 905 906 // Don't set the OS. It could be simulator, macosx, ios, watchos, 907 // tvos, bridgeos. We could get close with the cpu type - but we 908 // can't get it right all of the time. Better to leave this unset 909 // so other sections of code will set it when they have more 910 // information. NB: don't call m_triple.setOS 911 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 912 // the ArchSpec::TripleVendorWasSpecified() method says that any 913 // OSName setting means it was specified. 914 } else if (arch_type == eArchTypeELF) { 915 switch (os) { 916 case llvm::ELF::ELFOSABI_AIX: 917 m_triple.setOS(llvm::Triple::OSType::AIX); 918 break; 919 case llvm::ELF::ELFOSABI_FREEBSD: 920 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 921 break; 922 case llvm::ELF::ELFOSABI_GNU: 923 m_triple.setOS(llvm::Triple::OSType::Linux); 924 break; 925 case llvm::ELF::ELFOSABI_NETBSD: 926 m_triple.setOS(llvm::Triple::OSType::NetBSD); 927 break; 928 case llvm::ELF::ELFOSABI_OPENBSD: 929 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 930 break; 931 case llvm::ELF::ELFOSABI_SOLARIS: 932 m_triple.setOS(llvm::Triple::OSType::Solaris); 933 break; 934 } 935 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 936 m_triple.setVendor(llvm::Triple::PC); 937 m_triple.setOS(llvm::Triple::Win32); 938 } else { 939 m_triple.setVendor(llvm::Triple::UnknownVendor); 940 m_triple.setOS(llvm::Triple::UnknownOS); 941 } 942 // Fall back onto setting the machine type if the arch by name 943 // failed... 944 if (m_triple.getArch() == llvm::Triple::UnknownArch) 945 m_triple.setArch(core_def->machine); 946 } 947 } else { 948 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 949 if (log) 950 log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub); 951 } 952 } 953 CoreUpdated(update_triple); 954 return IsValid(); 955 } 956 957 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 958 const CoreDefinition *core_def = FindCoreDefinition(m_core); 959 if (core_def) 960 return core_def->min_opcode_byte_size; 961 return 0; 962 } 963 964 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 965 const CoreDefinition *core_def = FindCoreDefinition(m_core); 966 if (core_def) 967 return core_def->max_opcode_byte_size; 968 return 0; 969 } 970 971 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 972 return IsEqualTo(rhs, true); 973 } 974 975 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 976 return IsEqualTo(rhs, false); 977 } 978 979 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 980 llvm::Triple::EnvironmentType rhs) { 981 if (lhs == rhs) 982 return true; 983 984 // If any of the environment is unknown then they are compatible 985 if (lhs == llvm::Triple::UnknownEnvironment || 986 rhs == llvm::Triple::UnknownEnvironment) 987 return true; 988 989 // If one of the environment is Android and the other one is EABI then they 990 // are considered to be compatible. This is required as a workaround for 991 // shared libraries compiled for Android without the NOTE section indicating 992 // that they are using the Android ABI. 993 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 994 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 995 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 996 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 997 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 998 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 999 return true; 1000 1001 return false; 1002 } 1003 1004 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1005 // explicitly ignoring m_distribution_id in this method. 1006 1007 if (GetByteOrder() != rhs.GetByteOrder()) 1008 return false; 1009 1010 const ArchSpec::Core lhs_core = GetCore(); 1011 const ArchSpec::Core rhs_core = rhs.GetCore(); 1012 1013 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1014 1015 if (core_match) { 1016 const llvm::Triple &lhs_triple = GetTriple(); 1017 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1018 1019 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1020 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1021 if (lhs_triple_vendor != rhs_triple_vendor) { 1022 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1023 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1024 // Both architectures had the vendor specified, so if they aren't equal 1025 // then we return false 1026 if (rhs_vendor_specified && lhs_vendor_specified) 1027 return false; 1028 1029 // Only fail if both vendor types are not unknown 1030 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1031 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1032 return false; 1033 } 1034 1035 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1036 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1037 if (lhs_triple_os != rhs_triple_os) { 1038 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1039 const bool lhs_os_specified = TripleOSWasSpecified(); 1040 // Both architectures had the OS specified, so if they aren't equal then 1041 // we return false 1042 if (rhs_os_specified && lhs_os_specified) 1043 return false; 1044 1045 // Only fail if both os types are not unknown 1046 if (lhs_triple_os != llvm::Triple::UnknownOS && 1047 rhs_triple_os != llvm::Triple::UnknownOS) 1048 return false; 1049 } 1050 1051 const llvm::Triple::EnvironmentType lhs_triple_env = 1052 lhs_triple.getEnvironment(); 1053 const llvm::Triple::EnvironmentType rhs_triple_env = 1054 rhs_triple.getEnvironment(); 1055 1056 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1057 } 1058 return false; 1059 } 1060 1061 void ArchSpec::UpdateCore() { 1062 llvm::StringRef arch_name(m_triple.getArchName()); 1063 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1064 if (core_def) { 1065 m_core = core_def->core; 1066 // Set the byte order to the default byte order for an architecture. This 1067 // can be modified if needed for cases when cores handle both big and 1068 // little endian 1069 m_byte_order = core_def->default_byte_order; 1070 } else { 1071 Clear(); 1072 } 1073 } 1074 1075 //===----------------------------------------------------------------------===// 1076 // Helper methods. 1077 1078 void ArchSpec::CoreUpdated(bool update_triple) { 1079 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1080 if (core_def) { 1081 if (update_triple) 1082 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1083 m_byte_order = core_def->default_byte_order; 1084 } else { 1085 if (update_triple) 1086 m_triple = llvm::Triple(); 1087 m_byte_order = eByteOrderInvalid; 1088 } 1089 } 1090 1091 //===----------------------------------------------------------------------===// 1092 // Operators. 1093 1094 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1095 bool try_inverse, bool enforce_exact_match) { 1096 if (core1 == core2) 1097 return true; 1098 1099 switch (core1) { 1100 case ArchSpec::kCore_any: 1101 return true; 1102 1103 case ArchSpec::eCore_arm_generic: 1104 if (enforce_exact_match) 1105 break; 1106 LLVM_FALLTHROUGH; 1107 case ArchSpec::kCore_arm_any: 1108 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1109 return true; 1110 if (core2 >= ArchSpec::kCore_thumb_first && 1111 core2 <= ArchSpec::kCore_thumb_last) 1112 return true; 1113 if (core2 == ArchSpec::kCore_arm_any) 1114 return true; 1115 break; 1116 1117 case ArchSpec::kCore_x86_32_any: 1118 if ((core2 >= ArchSpec::kCore_x86_32_first && 1119 core2 <= ArchSpec::kCore_x86_32_last) || 1120 (core2 == ArchSpec::kCore_x86_32_any)) 1121 return true; 1122 break; 1123 1124 case ArchSpec::kCore_x86_64_any: 1125 if ((core2 >= ArchSpec::kCore_x86_64_first && 1126 core2 <= ArchSpec::kCore_x86_64_last) || 1127 (core2 == ArchSpec::kCore_x86_64_any)) 1128 return true; 1129 break; 1130 1131 case ArchSpec::kCore_ppc_any: 1132 if ((core2 >= ArchSpec::kCore_ppc_first && 1133 core2 <= ArchSpec::kCore_ppc_last) || 1134 (core2 == ArchSpec::kCore_ppc_any)) 1135 return true; 1136 break; 1137 1138 case ArchSpec::kCore_ppc64_any: 1139 if ((core2 >= ArchSpec::kCore_ppc64_first && 1140 core2 <= ArchSpec::kCore_ppc64_last) || 1141 (core2 == ArchSpec::kCore_ppc64_any)) 1142 return true; 1143 break; 1144 1145 case ArchSpec::eCore_arm_armv6m: 1146 if (!enforce_exact_match) { 1147 if (core2 == ArchSpec::eCore_arm_generic) 1148 return true; 1149 try_inverse = false; 1150 if (core2 == ArchSpec::eCore_arm_armv7) 1151 return true; 1152 if (core2 == ArchSpec::eCore_arm_armv6m) 1153 return true; 1154 } 1155 break; 1156 1157 case ArchSpec::kCore_hexagon_any: 1158 if ((core2 >= ArchSpec::kCore_hexagon_first && 1159 core2 <= ArchSpec::kCore_hexagon_last) || 1160 (core2 == ArchSpec::kCore_hexagon_any)) 1161 return true; 1162 break; 1163 1164 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1165 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1166 // ARMv7E-M - armv7em 1167 case ArchSpec::eCore_arm_armv7em: 1168 if (!enforce_exact_match) { 1169 if (core2 == ArchSpec::eCore_arm_generic) 1170 return true; 1171 if (core2 == ArchSpec::eCore_arm_armv7m) 1172 return true; 1173 if (core2 == ArchSpec::eCore_arm_armv6m) 1174 return true; 1175 if (core2 == ArchSpec::eCore_arm_armv7) 1176 return true; 1177 try_inverse = true; 1178 } 1179 break; 1180 1181 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1182 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1183 // ARMv7E-M - armv7em 1184 case ArchSpec::eCore_arm_armv7m: 1185 if (!enforce_exact_match) { 1186 if (core2 == ArchSpec::eCore_arm_generic) 1187 return true; 1188 if (core2 == ArchSpec::eCore_arm_armv6m) 1189 return true; 1190 if (core2 == ArchSpec::eCore_arm_armv7) 1191 return true; 1192 if (core2 == ArchSpec::eCore_arm_armv7em) 1193 return true; 1194 try_inverse = true; 1195 } 1196 break; 1197 1198 case ArchSpec::eCore_arm_armv7f: 1199 case ArchSpec::eCore_arm_armv7k: 1200 case ArchSpec::eCore_arm_armv7s: 1201 if (!enforce_exact_match) { 1202 if (core2 == ArchSpec::eCore_arm_generic) 1203 return true; 1204 if (core2 == ArchSpec::eCore_arm_armv7) 1205 return true; 1206 try_inverse = false; 1207 } 1208 break; 1209 1210 case ArchSpec::eCore_x86_64_x86_64h: 1211 if (!enforce_exact_match) { 1212 try_inverse = false; 1213 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1214 return true; 1215 } 1216 break; 1217 1218 case ArchSpec::eCore_arm_armv8: 1219 if (!enforce_exact_match) { 1220 if (core2 == ArchSpec::eCore_arm_arm64) 1221 return true; 1222 if (core2 == ArchSpec::eCore_arm_aarch64) 1223 return true; 1224 try_inverse = false; 1225 } 1226 break; 1227 1228 case ArchSpec::eCore_arm_aarch64: 1229 if (!enforce_exact_match) { 1230 if (core2 == ArchSpec::eCore_arm_arm64) 1231 return true; 1232 if (core2 == ArchSpec::eCore_arm_armv8) 1233 return true; 1234 try_inverse = false; 1235 } 1236 break; 1237 1238 case ArchSpec::eCore_arm_arm64: 1239 if (!enforce_exact_match) { 1240 if (core2 == ArchSpec::eCore_arm_aarch64) 1241 return true; 1242 if (core2 == ArchSpec::eCore_arm_armv8) 1243 return true; 1244 try_inverse = false; 1245 } 1246 break; 1247 1248 case ArchSpec::eCore_mips32: 1249 if (!enforce_exact_match) { 1250 if (core2 >= ArchSpec::kCore_mips32_first && 1251 core2 <= ArchSpec::kCore_mips32_last) 1252 return true; 1253 try_inverse = false; 1254 } 1255 break; 1256 1257 case ArchSpec::eCore_mips32el: 1258 if (!enforce_exact_match) { 1259 if (core2 >= ArchSpec::kCore_mips32el_first && 1260 core2 <= ArchSpec::kCore_mips32el_last) 1261 return true; 1262 try_inverse = true; 1263 } 1264 break; 1265 1266 case ArchSpec::eCore_mips64: 1267 if (!enforce_exact_match) { 1268 if (core2 >= ArchSpec::kCore_mips32_first && 1269 core2 <= ArchSpec::kCore_mips32_last) 1270 return true; 1271 if (core2 >= ArchSpec::kCore_mips64_first && 1272 core2 <= ArchSpec::kCore_mips64_last) 1273 return true; 1274 try_inverse = false; 1275 } 1276 break; 1277 1278 case ArchSpec::eCore_mips64el: 1279 if (!enforce_exact_match) { 1280 if (core2 >= ArchSpec::kCore_mips32el_first && 1281 core2 <= ArchSpec::kCore_mips32el_last) 1282 return true; 1283 if (core2 >= ArchSpec::kCore_mips64el_first && 1284 core2 <= ArchSpec::kCore_mips64el_last) 1285 return true; 1286 try_inverse = false; 1287 } 1288 break; 1289 1290 case ArchSpec::eCore_mips64r2: 1291 case ArchSpec::eCore_mips64r3: 1292 case ArchSpec::eCore_mips64r5: 1293 if (!enforce_exact_match) { 1294 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1295 return true; 1296 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1297 return true; 1298 try_inverse = false; 1299 } 1300 break; 1301 1302 case ArchSpec::eCore_mips64r2el: 1303 case ArchSpec::eCore_mips64r3el: 1304 case ArchSpec::eCore_mips64r5el: 1305 if (!enforce_exact_match) { 1306 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1307 return true; 1308 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1309 return true; 1310 try_inverse = false; 1311 } 1312 break; 1313 1314 case ArchSpec::eCore_mips32r2: 1315 case ArchSpec::eCore_mips32r3: 1316 case ArchSpec::eCore_mips32r5: 1317 if (!enforce_exact_match) { 1318 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1319 return true; 1320 } 1321 break; 1322 1323 case ArchSpec::eCore_mips32r2el: 1324 case ArchSpec::eCore_mips32r3el: 1325 case ArchSpec::eCore_mips32r5el: 1326 if (!enforce_exact_match) { 1327 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1328 return true; 1329 } 1330 break; 1331 1332 case ArchSpec::eCore_mips32r6: 1333 if (!enforce_exact_match) { 1334 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1335 return true; 1336 } 1337 break; 1338 1339 case ArchSpec::eCore_mips32r6el: 1340 if (!enforce_exact_match) { 1341 if (core2 == ArchSpec::eCore_mips32el || 1342 core2 == ArchSpec::eCore_mips32r6el) 1343 return true; 1344 } 1345 break; 1346 1347 case ArchSpec::eCore_mips64r6: 1348 if (!enforce_exact_match) { 1349 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1350 return true; 1351 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1352 return true; 1353 } 1354 break; 1355 1356 case ArchSpec::eCore_mips64r6el: 1357 if (!enforce_exact_match) { 1358 if (core2 == ArchSpec::eCore_mips32el || 1359 core2 == ArchSpec::eCore_mips32r6el) 1360 return true; 1361 if (core2 == ArchSpec::eCore_mips64el || 1362 core2 == ArchSpec::eCore_mips64r6el) 1363 return true; 1364 } 1365 break; 1366 1367 default: 1368 break; 1369 } 1370 if (try_inverse) 1371 return cores_match(core2, core1, false, enforce_exact_match); 1372 return false; 1373 } 1374 1375 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1376 const ArchSpec::Core lhs_core = lhs.GetCore(); 1377 const ArchSpec::Core rhs_core = rhs.GetCore(); 1378 return lhs_core < rhs_core; 1379 } 1380 1381 1382 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1383 return lhs.GetCore() == rhs.GetCore(); 1384 } 1385 1386 bool ArchSpec::IsFullySpecifiedTriple() const { 1387 const auto &user_specified_triple = GetTriple(); 1388 1389 bool user_triple_fully_specified = false; 1390 1391 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1392 TripleOSWasSpecified()) { 1393 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1394 TripleVendorWasSpecified()) { 1395 const unsigned unspecified = 0; 1396 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1397 user_triple_fully_specified = true; 1398 } 1399 } 1400 } 1401 1402 return user_triple_fully_specified; 1403 } 1404 1405 void ArchSpec::PiecewiseTripleCompare( 1406 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1407 bool &os_different, bool &os_version_different, bool &env_different) const { 1408 const llvm::Triple &me(GetTriple()); 1409 const llvm::Triple &them(other.GetTriple()); 1410 1411 arch_different = (me.getArch() != them.getArch()); 1412 1413 vendor_different = (me.getVendor() != them.getVendor()); 1414 1415 os_different = (me.getOS() != them.getOS()); 1416 1417 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1418 1419 env_different = (me.getEnvironment() != them.getEnvironment()); 1420 } 1421 1422 bool ArchSpec::IsAlwaysThumbInstructions() const { 1423 std::string Status; 1424 if (GetTriple().getArch() == llvm::Triple::arm || 1425 GetTriple().getArch() == llvm::Triple::thumb) { 1426 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1427 // 1428 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1429 // execute thumb instructions. We map the cores to arch names like this: 1430 // 1431 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1432 // Cortex-M7: armv7em 1433 1434 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1435 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1436 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1437 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1438 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1439 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1440 return true; 1441 } 1442 } 1443 return false; 1444 } 1445 1446 void ArchSpec::DumpTriple(Stream &s) const { 1447 const llvm::Triple &triple = GetTriple(); 1448 llvm::StringRef arch_str = triple.getArchName(); 1449 llvm::StringRef vendor_str = triple.getVendorName(); 1450 llvm::StringRef os_str = triple.getOSName(); 1451 llvm::StringRef environ_str = triple.getEnvironmentName(); 1452 1453 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1454 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1455 os_str.empty() ? "*" : os_str.str().c_str()); 1456 1457 if (!environ_str.empty()) 1458 s.Printf("-%s", environ_str.str().c_str()); 1459 } 1460