10b57cec5SDimitry Andric //===-- x86AssemblyInspectionEngine.h ---------------------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 95ffd83dbSDimitry Andric #ifndef LLDB_SOURCE_PLUGINS_UNWINDASSEMBLY_X86_X86ASSEMBLYINSPECTIONENGINE_H 105ffd83dbSDimitry Andric #define LLDB_SOURCE_PLUGINS_UNWINDASSEMBLY_X86_X86ASSEMBLYINSPECTIONENGINE_H 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric #include "llvm-c/Disassembler.h" 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #include "lldb/Utility/ArchSpec.h" 150b57cec5SDimitry Andric #include "lldb/Utility/ConstString.h" 160b57cec5SDimitry Andric #include "lldb/lldb-enumerations.h" 170b57cec5SDimitry Andric #include "lldb/lldb-forward.h" 180b57cec5SDimitry Andric #include "lldb/lldb-private.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric #include <map> 210b57cec5SDimitry Andric #include <vector> 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric namespace lldb_private { 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric // x86AssemblyInspectionEngine - a class which will take a buffer of bytes 260b57cec5SDimitry Andric // of i386/x86_64 instructions and create an UnwindPlan based on those 270b57cec5SDimitry Andric // assembly instructions. 280b57cec5SDimitry Andric class x86AssemblyInspectionEngine { 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric public: 310b57cec5SDimitry Andric /// default ctor 320b57cec5SDimitry Andric x86AssemblyInspectionEngine(const lldb_private::ArchSpec &arch); 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric /// default dtor 350b57cec5SDimitry Andric ~x86AssemblyInspectionEngine(); 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric /// One of the two initialize methods that can be called on this object; 380b57cec5SDimitry Andric /// they must be called before any of the assembly inspection methods 390b57cec5SDimitry Andric /// are called. This one should be used if the caller has access to a 400b57cec5SDimitry Andric /// valid RegisterContext. 410b57cec5SDimitry Andric void Initialize(lldb::RegisterContextSP ®_ctx); 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric /// One of the two initialize methods that can be called on this object; 440b57cec5SDimitry Andric /// they must be called before any of the assembly inspection methods 450b57cec5SDimitry Andric /// are called. This one takes a vector of register name and lldb 460b57cec5SDimitry Andric /// register numbers. 470b57cec5SDimitry Andric struct lldb_reg_info { 48*fe6060f1SDimitry Andric const char *name = nullptr; 49*fe6060f1SDimitry Andric uint32_t lldb_regnum = LLDB_INVALID_REGNUM; 50*fe6060f1SDimitry Andric lldb_reg_info() = default; 510b57cec5SDimitry Andric }; 520b57cec5SDimitry Andric void Initialize(std::vector<lldb_reg_info> ®_info); 530b57cec5SDimitry Andric 540b57cec5SDimitry Andric /// Create an UnwindPlan for a "non-call site" stack frame situation. 550b57cec5SDimitry Andric /// This is usually when this function/method is currently executing, and may 560b57cec5SDimitry Andric /// be at 570b57cec5SDimitry Andric /// a location where exception-handling style unwind information (eh_frame, 580b57cec5SDimitry Andric /// compact unwind info, arm unwind info) 590b57cec5SDimitry Andric /// are not valid. 600b57cec5SDimitry Andric /// \p data is a pointer to the instructions for the function 610b57cec5SDimitry Andric /// \p size is the size of the instruction buffer above 620b57cec5SDimitry Andric /// \p func_range is the start Address and size of the function, to be 630b57cec5SDimitry Andric /// included in the UnwindPlan 640b57cec5SDimitry Andric /// \p unwind_plan is the unwind plan that this method creates 650b57cec5SDimitry Andric /// \returns true if it was able to create an UnwindPlan; false if not. 660b57cec5SDimitry Andric bool 670b57cec5SDimitry Andric GetNonCallSiteUnwindPlanFromAssembly(uint8_t *data, size_t size, 680b57cec5SDimitry Andric lldb_private::AddressRange &func_range, 690b57cec5SDimitry Andric lldb_private::UnwindPlan &unwind_plan); 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric /// Take an existing UnwindPlan, probably from eh_frame which may be missing 720b57cec5SDimitry Andric /// description 730b57cec5SDimitry Andric /// of the epilogue instructions, and add the epilogue description to it based 740b57cec5SDimitry Andric /// on the 750b57cec5SDimitry Andric /// instructions in the function. 760b57cec5SDimitry Andric /// 770b57cec5SDimitry Andric /// The \p unwind_plan 's register numbers must be converted into the lldb 780b57cec5SDimitry Andric /// register numbering 790b57cec5SDimitry Andric /// scheme OR a RegisterContext must be provided in \p reg_ctx. If the \p 800b57cec5SDimitry Andric /// unwind_plan 810b57cec5SDimitry Andric /// register numbers are already in lldb register numbering, \p reg_ctx may be 820b57cec5SDimitry Andric /// null. 830b57cec5SDimitry Andric /// \returns true if the \p unwind_plan was updated, false if it was not. 840b57cec5SDimitry Andric bool AugmentUnwindPlanFromCallSite(uint8_t *data, size_t size, 850b57cec5SDimitry Andric lldb_private::AddressRange &func_range, 860b57cec5SDimitry Andric lldb_private::UnwindPlan &unwind_plan, 870b57cec5SDimitry Andric lldb::RegisterContextSP ®_ctx); 880b57cec5SDimitry Andric 890b57cec5SDimitry Andric bool FindFirstNonPrologueInstruction(uint8_t *data, size_t size, 900b57cec5SDimitry Andric size_t &offset); 910b57cec5SDimitry Andric 920b57cec5SDimitry Andric private: 930b57cec5SDimitry Andric bool nonvolatile_reg_p(int machine_regno); 940b57cec5SDimitry Andric bool push_rbp_pattern_p(); 950b57cec5SDimitry Andric bool push_0_pattern_p(); 960b57cec5SDimitry Andric bool push_imm_pattern_p(); 970b57cec5SDimitry Andric bool push_extended_pattern_p(); 980b57cec5SDimitry Andric bool push_misc_reg_p(); 990b57cec5SDimitry Andric bool mov_rsp_rbp_pattern_p(); 1000b57cec5SDimitry Andric bool mov_rsp_rbx_pattern_p(); 1010b57cec5SDimitry Andric bool mov_rbp_rsp_pattern_p(); 1020b57cec5SDimitry Andric bool mov_rbx_rsp_pattern_p(); 1030b57cec5SDimitry Andric bool sub_rsp_pattern_p(int &amount); 1040b57cec5SDimitry Andric bool add_rsp_pattern_p(int &amount); 1050b57cec5SDimitry Andric bool lea_rsp_pattern_p(int &amount); 1060b57cec5SDimitry Andric bool lea_rbp_rsp_pattern_p(int &amount); 1070b57cec5SDimitry Andric bool lea_rbx_rsp_pattern_p(int &amount); 1080b57cec5SDimitry Andric bool and_rsp_pattern_p(); 1090b57cec5SDimitry Andric bool push_reg_p(int ®no); 1100b57cec5SDimitry Andric bool pop_reg_p(int ®no); 1110b57cec5SDimitry Andric bool pop_rbp_pattern_p(); 1120b57cec5SDimitry Andric bool pop_misc_reg_p(); 1130b57cec5SDimitry Andric bool leave_pattern_p(); 1140b57cec5SDimitry Andric bool call_next_insn_pattern_p(); 1150b57cec5SDimitry Andric bool mov_reg_to_local_stack_frame_p(int ®no, int &rbp_offset); 1160b57cec5SDimitry Andric bool ret_pattern_p(); 1170b57cec5SDimitry Andric bool jmp_to_reg_p(); 1180b57cec5SDimitry Andric bool pc_rel_branch_or_jump_p (const int instruction_length, int &offset); 1190b57cec5SDimitry Andric bool non_local_branch_p (const lldb::addr_t current_func_text_offset, 1200b57cec5SDimitry Andric const lldb_private::AddressRange &func_range, 1210b57cec5SDimitry Andric const int instruction_length); 1220b57cec5SDimitry Andric bool local_branch_p (const lldb::addr_t current_func_text_offset, 1230b57cec5SDimitry Andric const lldb_private::AddressRange &func_range, 1240b57cec5SDimitry Andric const int instruction_length, 1250b57cec5SDimitry Andric lldb::addr_t &target_insn_offset); 1260b57cec5SDimitry Andric uint16_t extract_2(uint8_t *b); 1270b57cec5SDimitry Andric int16_t extract_2_signed(uint8_t *b); 1280b57cec5SDimitry Andric uint32_t extract_4(uint8_t *b); 1290b57cec5SDimitry Andric int32_t extract_4_signed(uint8_t *b); 1300b57cec5SDimitry Andric 1310b57cec5SDimitry Andric bool instruction_length(uint8_t *insn, int &length, uint32_t buffer_remaining_bytes); 1320b57cec5SDimitry Andric 1330b57cec5SDimitry Andric bool machine_regno_to_lldb_regno(int machine_regno, uint32_t &lldb_regno); 1340b57cec5SDimitry Andric 1350b57cec5SDimitry Andric enum CPU { k_i386, k_x86_64, k_cpu_unspecified }; 1360b57cec5SDimitry Andric 1370b57cec5SDimitry Andric enum i386_register_numbers { 1380b57cec5SDimitry Andric k_machine_eax = 0, 1390b57cec5SDimitry Andric k_machine_ecx = 1, 1400b57cec5SDimitry Andric k_machine_edx = 2, 1410b57cec5SDimitry Andric k_machine_ebx = 3, 1420b57cec5SDimitry Andric k_machine_esp = 4, 1430b57cec5SDimitry Andric k_machine_ebp = 5, 1440b57cec5SDimitry Andric k_machine_esi = 6, 1450b57cec5SDimitry Andric k_machine_edi = 7, 1460b57cec5SDimitry Andric k_machine_eip = 8 1470b57cec5SDimitry Andric }; 1480b57cec5SDimitry Andric 1490b57cec5SDimitry Andric enum x86_64_register_numbers { 1500b57cec5SDimitry Andric k_machine_rax = 0, 1510b57cec5SDimitry Andric k_machine_rcx = 1, 1520b57cec5SDimitry Andric k_machine_rdx = 2, 1530b57cec5SDimitry Andric k_machine_rbx = 3, 1540b57cec5SDimitry Andric k_machine_rsp = 4, 1550b57cec5SDimitry Andric k_machine_rbp = 5, 1560b57cec5SDimitry Andric k_machine_rsi = 6, 1570b57cec5SDimitry Andric k_machine_rdi = 7, 1580b57cec5SDimitry Andric k_machine_r8 = 8, 1590b57cec5SDimitry Andric k_machine_r9 = 9, 1600b57cec5SDimitry Andric k_machine_r10 = 10, 1610b57cec5SDimitry Andric k_machine_r11 = 11, 1620b57cec5SDimitry Andric k_machine_r12 = 12, 1630b57cec5SDimitry Andric k_machine_r13 = 13, 1640b57cec5SDimitry Andric k_machine_r14 = 14, 1650b57cec5SDimitry Andric k_machine_r15 = 15, 1660b57cec5SDimitry Andric k_machine_rip = 16 1670b57cec5SDimitry Andric }; 1680b57cec5SDimitry Andric 1690b57cec5SDimitry Andric enum { kMaxInstructionByteSize = 32 }; 1700b57cec5SDimitry Andric 1710b57cec5SDimitry Andric uint8_t *m_cur_insn; 1720b57cec5SDimitry Andric 1730b57cec5SDimitry Andric uint32_t m_machine_ip_regnum; 1740b57cec5SDimitry Andric uint32_t m_machine_sp_regnum; 1750b57cec5SDimitry Andric uint32_t m_machine_fp_regnum; 1760b57cec5SDimitry Andric uint32_t m_machine_alt_fp_regnum; 1770b57cec5SDimitry Andric uint32_t m_lldb_ip_regnum; 1780b57cec5SDimitry Andric uint32_t m_lldb_sp_regnum; 1790b57cec5SDimitry Andric uint32_t m_lldb_fp_regnum; 1800b57cec5SDimitry Andric uint32_t m_lldb_alt_fp_regnum; 1810b57cec5SDimitry Andric 1820b57cec5SDimitry Andric typedef std::map<uint32_t, lldb_reg_info> MachineRegnumToNameAndLLDBRegnum; 1830b57cec5SDimitry Andric 1840b57cec5SDimitry Andric MachineRegnumToNameAndLLDBRegnum m_reg_map; 1850b57cec5SDimitry Andric 1860b57cec5SDimitry Andric lldb_private::ArchSpec m_arch; 1870b57cec5SDimitry Andric CPU m_cpu; 1880b57cec5SDimitry Andric int m_wordsize; 1890b57cec5SDimitry Andric 1900b57cec5SDimitry Andric bool m_register_map_initialized; 1910b57cec5SDimitry Andric 1920b57cec5SDimitry Andric ::LLVMDisasmContextRef m_disasm_context; 1930b57cec5SDimitry Andric 1945ffd83dbSDimitry Andric x86AssemblyInspectionEngine(const x86AssemblyInspectionEngine &) = delete; 1955ffd83dbSDimitry Andric const x86AssemblyInspectionEngine & 1965ffd83dbSDimitry Andric operator=(const x86AssemblyInspectionEngine &) = delete; 1970b57cec5SDimitry Andric }; 1980b57cec5SDimitry Andric 1990b57cec5SDimitry Andric } // namespace lldb_private 2000b57cec5SDimitry Andric 2015ffd83dbSDimitry Andric #endif // LLDB_SOURCE_PLUGINS_UNWINDASSEMBLY_X86_X86ASSEMBLYINSPECTIONENGINE_H 202