10b57cec5SDimitry Andric //===-- RegisterContext_mips.h --------------------------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 9*5ffd83dbSDimitry Andric #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H 10*5ffd83dbSDimitry Andric #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric #include <cstddef> 130b57cec5SDimitry Andric #include <cstdint> 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric // eh_frame and DWARF Register numbers (eRegisterKindEHFrame & 160b57cec5SDimitry Andric // eRegisterKindDWARF) 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric enum { 190b57cec5SDimitry Andric // GP Registers 200b57cec5SDimitry Andric dwarf_zero_mips = 0, 210b57cec5SDimitry Andric dwarf_r1_mips, 220b57cec5SDimitry Andric dwarf_r2_mips, 230b57cec5SDimitry Andric dwarf_r3_mips, 240b57cec5SDimitry Andric dwarf_r4_mips, 250b57cec5SDimitry Andric dwarf_r5_mips, 260b57cec5SDimitry Andric dwarf_r6_mips, 270b57cec5SDimitry Andric dwarf_r7_mips, 280b57cec5SDimitry Andric dwarf_r8_mips, 290b57cec5SDimitry Andric dwarf_r9_mips, 300b57cec5SDimitry Andric dwarf_r10_mips, 310b57cec5SDimitry Andric dwarf_r11_mips, 320b57cec5SDimitry Andric dwarf_r12_mips, 330b57cec5SDimitry Andric dwarf_r13_mips, 340b57cec5SDimitry Andric dwarf_r14_mips, 350b57cec5SDimitry Andric dwarf_r15_mips, 360b57cec5SDimitry Andric dwarf_r16_mips, 370b57cec5SDimitry Andric dwarf_r17_mips, 380b57cec5SDimitry Andric dwarf_r18_mips, 390b57cec5SDimitry Andric dwarf_r19_mips, 400b57cec5SDimitry Andric dwarf_r20_mips, 410b57cec5SDimitry Andric dwarf_r21_mips, 420b57cec5SDimitry Andric dwarf_r22_mips, 430b57cec5SDimitry Andric dwarf_r23_mips, 440b57cec5SDimitry Andric dwarf_r24_mips, 450b57cec5SDimitry Andric dwarf_r25_mips, 460b57cec5SDimitry Andric dwarf_r26_mips, 470b57cec5SDimitry Andric dwarf_r27_mips, 480b57cec5SDimitry Andric dwarf_gp_mips, 490b57cec5SDimitry Andric dwarf_sp_mips, 500b57cec5SDimitry Andric dwarf_r30_mips, 510b57cec5SDimitry Andric dwarf_ra_mips, 520b57cec5SDimitry Andric dwarf_sr_mips, 530b57cec5SDimitry Andric dwarf_lo_mips, 540b57cec5SDimitry Andric dwarf_hi_mips, 550b57cec5SDimitry Andric dwarf_bad_mips, 560b57cec5SDimitry Andric dwarf_cause_mips, 570b57cec5SDimitry Andric dwarf_pc_mips, 580b57cec5SDimitry Andric dwarf_f0_mips, 590b57cec5SDimitry Andric dwarf_f1_mips, 600b57cec5SDimitry Andric dwarf_f2_mips, 610b57cec5SDimitry Andric dwarf_f3_mips, 620b57cec5SDimitry Andric dwarf_f4_mips, 630b57cec5SDimitry Andric dwarf_f5_mips, 640b57cec5SDimitry Andric dwarf_f6_mips, 650b57cec5SDimitry Andric dwarf_f7_mips, 660b57cec5SDimitry Andric dwarf_f8_mips, 670b57cec5SDimitry Andric dwarf_f9_mips, 680b57cec5SDimitry Andric dwarf_f10_mips, 690b57cec5SDimitry Andric dwarf_f11_mips, 700b57cec5SDimitry Andric dwarf_f12_mips, 710b57cec5SDimitry Andric dwarf_f13_mips, 720b57cec5SDimitry Andric dwarf_f14_mips, 730b57cec5SDimitry Andric dwarf_f15_mips, 740b57cec5SDimitry Andric dwarf_f16_mips, 750b57cec5SDimitry Andric dwarf_f17_mips, 760b57cec5SDimitry Andric dwarf_f18_mips, 770b57cec5SDimitry Andric dwarf_f19_mips, 780b57cec5SDimitry Andric dwarf_f20_mips, 790b57cec5SDimitry Andric dwarf_f21_mips, 800b57cec5SDimitry Andric dwarf_f22_mips, 810b57cec5SDimitry Andric dwarf_f23_mips, 820b57cec5SDimitry Andric dwarf_f24_mips, 830b57cec5SDimitry Andric dwarf_f25_mips, 840b57cec5SDimitry Andric dwarf_f26_mips, 850b57cec5SDimitry Andric dwarf_f27_mips, 860b57cec5SDimitry Andric dwarf_f28_mips, 870b57cec5SDimitry Andric dwarf_f29_mips, 880b57cec5SDimitry Andric dwarf_f30_mips, 890b57cec5SDimitry Andric dwarf_f31_mips, 900b57cec5SDimitry Andric dwarf_fcsr_mips, 910b57cec5SDimitry Andric dwarf_fir_mips, 920b57cec5SDimitry Andric dwarf_w0_mips, 930b57cec5SDimitry Andric dwarf_w1_mips, 940b57cec5SDimitry Andric dwarf_w2_mips, 950b57cec5SDimitry Andric dwarf_w3_mips, 960b57cec5SDimitry Andric dwarf_w4_mips, 970b57cec5SDimitry Andric dwarf_w5_mips, 980b57cec5SDimitry Andric dwarf_w6_mips, 990b57cec5SDimitry Andric dwarf_w7_mips, 1000b57cec5SDimitry Andric dwarf_w8_mips, 1010b57cec5SDimitry Andric dwarf_w9_mips, 1020b57cec5SDimitry Andric dwarf_w10_mips, 1030b57cec5SDimitry Andric dwarf_w11_mips, 1040b57cec5SDimitry Andric dwarf_w12_mips, 1050b57cec5SDimitry Andric dwarf_w13_mips, 1060b57cec5SDimitry Andric dwarf_w14_mips, 1070b57cec5SDimitry Andric dwarf_w15_mips, 1080b57cec5SDimitry Andric dwarf_w16_mips, 1090b57cec5SDimitry Andric dwarf_w17_mips, 1100b57cec5SDimitry Andric dwarf_w18_mips, 1110b57cec5SDimitry Andric dwarf_w19_mips, 1120b57cec5SDimitry Andric dwarf_w20_mips, 1130b57cec5SDimitry Andric dwarf_w21_mips, 1140b57cec5SDimitry Andric dwarf_w22_mips, 1150b57cec5SDimitry Andric dwarf_w23_mips, 1160b57cec5SDimitry Andric dwarf_w24_mips, 1170b57cec5SDimitry Andric dwarf_w25_mips, 1180b57cec5SDimitry Andric dwarf_w26_mips, 1190b57cec5SDimitry Andric dwarf_w27_mips, 1200b57cec5SDimitry Andric dwarf_w28_mips, 1210b57cec5SDimitry Andric dwarf_w29_mips, 1220b57cec5SDimitry Andric dwarf_w30_mips, 1230b57cec5SDimitry Andric dwarf_w31_mips, 1240b57cec5SDimitry Andric dwarf_mcsr_mips, 1250b57cec5SDimitry Andric dwarf_mir_mips, 1260b57cec5SDimitry Andric dwarf_config5_mips, 1270b57cec5SDimitry Andric dwarf_ic_mips, 1280b57cec5SDimitry Andric dwarf_dummy_mips 1290b57cec5SDimitry Andric }; 1300b57cec5SDimitry Andric 1310b57cec5SDimitry Andric enum { 1320b57cec5SDimitry Andric dwarf_zero_mips64 = 0, 1330b57cec5SDimitry Andric dwarf_r1_mips64, 1340b57cec5SDimitry Andric dwarf_r2_mips64, 1350b57cec5SDimitry Andric dwarf_r3_mips64, 1360b57cec5SDimitry Andric dwarf_r4_mips64, 1370b57cec5SDimitry Andric dwarf_r5_mips64, 1380b57cec5SDimitry Andric dwarf_r6_mips64, 1390b57cec5SDimitry Andric dwarf_r7_mips64, 1400b57cec5SDimitry Andric dwarf_r8_mips64, 1410b57cec5SDimitry Andric dwarf_r9_mips64, 1420b57cec5SDimitry Andric dwarf_r10_mips64, 1430b57cec5SDimitry Andric dwarf_r11_mips64, 1440b57cec5SDimitry Andric dwarf_r12_mips64, 1450b57cec5SDimitry Andric dwarf_r13_mips64, 1460b57cec5SDimitry Andric dwarf_r14_mips64, 1470b57cec5SDimitry Andric dwarf_r15_mips64, 1480b57cec5SDimitry Andric dwarf_r16_mips64, 1490b57cec5SDimitry Andric dwarf_r17_mips64, 1500b57cec5SDimitry Andric dwarf_r18_mips64, 1510b57cec5SDimitry Andric dwarf_r19_mips64, 1520b57cec5SDimitry Andric dwarf_r20_mips64, 1530b57cec5SDimitry Andric dwarf_r21_mips64, 1540b57cec5SDimitry Andric dwarf_r22_mips64, 1550b57cec5SDimitry Andric dwarf_r23_mips64, 1560b57cec5SDimitry Andric dwarf_r24_mips64, 1570b57cec5SDimitry Andric dwarf_r25_mips64, 1580b57cec5SDimitry Andric dwarf_r26_mips64, 1590b57cec5SDimitry Andric dwarf_r27_mips64, 1600b57cec5SDimitry Andric dwarf_gp_mips64, 1610b57cec5SDimitry Andric dwarf_sp_mips64, 1620b57cec5SDimitry Andric dwarf_r30_mips64, 1630b57cec5SDimitry Andric dwarf_ra_mips64, 1640b57cec5SDimitry Andric dwarf_sr_mips64, 1650b57cec5SDimitry Andric dwarf_lo_mips64, 1660b57cec5SDimitry Andric dwarf_hi_mips64, 1670b57cec5SDimitry Andric dwarf_bad_mips64, 1680b57cec5SDimitry Andric dwarf_cause_mips64, 1690b57cec5SDimitry Andric dwarf_pc_mips64, 1700b57cec5SDimitry Andric dwarf_f0_mips64, 1710b57cec5SDimitry Andric dwarf_f1_mips64, 1720b57cec5SDimitry Andric dwarf_f2_mips64, 1730b57cec5SDimitry Andric dwarf_f3_mips64, 1740b57cec5SDimitry Andric dwarf_f4_mips64, 1750b57cec5SDimitry Andric dwarf_f5_mips64, 1760b57cec5SDimitry Andric dwarf_f6_mips64, 1770b57cec5SDimitry Andric dwarf_f7_mips64, 1780b57cec5SDimitry Andric dwarf_f8_mips64, 1790b57cec5SDimitry Andric dwarf_f9_mips64, 1800b57cec5SDimitry Andric dwarf_f10_mips64, 1810b57cec5SDimitry Andric dwarf_f11_mips64, 1820b57cec5SDimitry Andric dwarf_f12_mips64, 1830b57cec5SDimitry Andric dwarf_f13_mips64, 1840b57cec5SDimitry Andric dwarf_f14_mips64, 1850b57cec5SDimitry Andric dwarf_f15_mips64, 1860b57cec5SDimitry Andric dwarf_f16_mips64, 1870b57cec5SDimitry Andric dwarf_f17_mips64, 1880b57cec5SDimitry Andric dwarf_f18_mips64, 1890b57cec5SDimitry Andric dwarf_f19_mips64, 1900b57cec5SDimitry Andric dwarf_f20_mips64, 1910b57cec5SDimitry Andric dwarf_f21_mips64, 1920b57cec5SDimitry Andric dwarf_f22_mips64, 1930b57cec5SDimitry Andric dwarf_f23_mips64, 1940b57cec5SDimitry Andric dwarf_f24_mips64, 1950b57cec5SDimitry Andric dwarf_f25_mips64, 1960b57cec5SDimitry Andric dwarf_f26_mips64, 1970b57cec5SDimitry Andric dwarf_f27_mips64, 1980b57cec5SDimitry Andric dwarf_f28_mips64, 1990b57cec5SDimitry Andric dwarf_f29_mips64, 2000b57cec5SDimitry Andric dwarf_f30_mips64, 2010b57cec5SDimitry Andric dwarf_f31_mips64, 2020b57cec5SDimitry Andric dwarf_fcsr_mips64, 2030b57cec5SDimitry Andric dwarf_fir_mips64, 2040b57cec5SDimitry Andric dwarf_ic_mips64, 2050b57cec5SDimitry Andric dwarf_dummy_mips64, 2060b57cec5SDimitry Andric dwarf_w0_mips64, 2070b57cec5SDimitry Andric dwarf_w1_mips64, 2080b57cec5SDimitry Andric dwarf_w2_mips64, 2090b57cec5SDimitry Andric dwarf_w3_mips64, 2100b57cec5SDimitry Andric dwarf_w4_mips64, 2110b57cec5SDimitry Andric dwarf_w5_mips64, 2120b57cec5SDimitry Andric dwarf_w6_mips64, 2130b57cec5SDimitry Andric dwarf_w7_mips64, 2140b57cec5SDimitry Andric dwarf_w8_mips64, 2150b57cec5SDimitry Andric dwarf_w9_mips64, 2160b57cec5SDimitry Andric dwarf_w10_mips64, 2170b57cec5SDimitry Andric dwarf_w11_mips64, 2180b57cec5SDimitry Andric dwarf_w12_mips64, 2190b57cec5SDimitry Andric dwarf_w13_mips64, 2200b57cec5SDimitry Andric dwarf_w14_mips64, 2210b57cec5SDimitry Andric dwarf_w15_mips64, 2220b57cec5SDimitry Andric dwarf_w16_mips64, 2230b57cec5SDimitry Andric dwarf_w17_mips64, 2240b57cec5SDimitry Andric dwarf_w18_mips64, 2250b57cec5SDimitry Andric dwarf_w19_mips64, 2260b57cec5SDimitry Andric dwarf_w20_mips64, 2270b57cec5SDimitry Andric dwarf_w21_mips64, 2280b57cec5SDimitry Andric dwarf_w22_mips64, 2290b57cec5SDimitry Andric dwarf_w23_mips64, 2300b57cec5SDimitry Andric dwarf_w24_mips64, 2310b57cec5SDimitry Andric dwarf_w25_mips64, 2320b57cec5SDimitry Andric dwarf_w26_mips64, 2330b57cec5SDimitry Andric dwarf_w27_mips64, 2340b57cec5SDimitry Andric dwarf_w28_mips64, 2350b57cec5SDimitry Andric dwarf_w29_mips64, 2360b57cec5SDimitry Andric dwarf_w30_mips64, 2370b57cec5SDimitry Andric dwarf_w31_mips64, 2380b57cec5SDimitry Andric dwarf_mcsr_mips64, 2390b57cec5SDimitry Andric dwarf_mir_mips64, 2400b57cec5SDimitry Andric dwarf_config5_mips64, 2410b57cec5SDimitry Andric }; 2420b57cec5SDimitry Andric 2430b57cec5SDimitry Andric // GP registers 2440b57cec5SDimitry Andric struct GPR_linux_mips { 2450b57cec5SDimitry Andric uint64_t zero; 2460b57cec5SDimitry Andric uint64_t r1; 2470b57cec5SDimitry Andric uint64_t r2; 2480b57cec5SDimitry Andric uint64_t r3; 2490b57cec5SDimitry Andric uint64_t r4; 2500b57cec5SDimitry Andric uint64_t r5; 2510b57cec5SDimitry Andric uint64_t r6; 2520b57cec5SDimitry Andric uint64_t r7; 2530b57cec5SDimitry Andric uint64_t r8; 2540b57cec5SDimitry Andric uint64_t r9; 2550b57cec5SDimitry Andric uint64_t r10; 2560b57cec5SDimitry Andric uint64_t r11; 2570b57cec5SDimitry Andric uint64_t r12; 2580b57cec5SDimitry Andric uint64_t r13; 2590b57cec5SDimitry Andric uint64_t r14; 2600b57cec5SDimitry Andric uint64_t r15; 2610b57cec5SDimitry Andric uint64_t r16; 2620b57cec5SDimitry Andric uint64_t r17; 2630b57cec5SDimitry Andric uint64_t r18; 2640b57cec5SDimitry Andric uint64_t r19; 2650b57cec5SDimitry Andric uint64_t r20; 2660b57cec5SDimitry Andric uint64_t r21; 2670b57cec5SDimitry Andric uint64_t r22; 2680b57cec5SDimitry Andric uint64_t r23; 2690b57cec5SDimitry Andric uint64_t r24; 2700b57cec5SDimitry Andric uint64_t r25; 2710b57cec5SDimitry Andric uint64_t r26; 2720b57cec5SDimitry Andric uint64_t r27; 2730b57cec5SDimitry Andric uint64_t gp; 2740b57cec5SDimitry Andric uint64_t sp; 2750b57cec5SDimitry Andric uint64_t r30; 2760b57cec5SDimitry Andric uint64_t ra; 2770b57cec5SDimitry Andric uint64_t mullo; 2780b57cec5SDimitry Andric uint64_t mulhi; 2790b57cec5SDimitry Andric uint64_t pc; 2800b57cec5SDimitry Andric uint64_t badvaddr; 2810b57cec5SDimitry Andric uint64_t sr; 2820b57cec5SDimitry Andric uint64_t cause; 2830b57cec5SDimitry Andric uint64_t config5; 2840b57cec5SDimitry Andric }; 2850b57cec5SDimitry Andric 2860b57cec5SDimitry Andric struct FPR_linux_mips { 2870b57cec5SDimitry Andric uint64_t f0; 2880b57cec5SDimitry Andric uint64_t f1; 2890b57cec5SDimitry Andric uint64_t f2; 2900b57cec5SDimitry Andric uint64_t f3; 2910b57cec5SDimitry Andric uint64_t f4; 2920b57cec5SDimitry Andric uint64_t f5; 2930b57cec5SDimitry Andric uint64_t f6; 2940b57cec5SDimitry Andric uint64_t f7; 2950b57cec5SDimitry Andric uint64_t f8; 2960b57cec5SDimitry Andric uint64_t f9; 2970b57cec5SDimitry Andric uint64_t f10; 2980b57cec5SDimitry Andric uint64_t f11; 2990b57cec5SDimitry Andric uint64_t f12; 3000b57cec5SDimitry Andric uint64_t f13; 3010b57cec5SDimitry Andric uint64_t f14; 3020b57cec5SDimitry Andric uint64_t f15; 3030b57cec5SDimitry Andric uint64_t f16; 3040b57cec5SDimitry Andric uint64_t f17; 3050b57cec5SDimitry Andric uint64_t f18; 3060b57cec5SDimitry Andric uint64_t f19; 3070b57cec5SDimitry Andric uint64_t f20; 3080b57cec5SDimitry Andric uint64_t f21; 3090b57cec5SDimitry Andric uint64_t f22; 3100b57cec5SDimitry Andric uint64_t f23; 3110b57cec5SDimitry Andric uint64_t f24; 3120b57cec5SDimitry Andric uint64_t f25; 3130b57cec5SDimitry Andric uint64_t f26; 3140b57cec5SDimitry Andric uint64_t f27; 3150b57cec5SDimitry Andric uint64_t f28; 3160b57cec5SDimitry Andric uint64_t f29; 3170b57cec5SDimitry Andric uint64_t f30; 3180b57cec5SDimitry Andric uint64_t f31; 3190b57cec5SDimitry Andric uint32_t fcsr; 3200b57cec5SDimitry Andric uint32_t fir; 3210b57cec5SDimitry Andric uint32_t config5; 3220b57cec5SDimitry Andric }; 3230b57cec5SDimitry Andric 3240b57cec5SDimitry Andric struct MSAReg { 3250b57cec5SDimitry Andric uint8_t byte[16]; 3260b57cec5SDimitry Andric }; 3270b57cec5SDimitry Andric 3280b57cec5SDimitry Andric struct MSA_linux_mips { 3290b57cec5SDimitry Andric MSAReg w0; 3300b57cec5SDimitry Andric MSAReg w1; 3310b57cec5SDimitry Andric MSAReg w2; 3320b57cec5SDimitry Andric MSAReg w3; 3330b57cec5SDimitry Andric MSAReg w4; 3340b57cec5SDimitry Andric MSAReg w5; 3350b57cec5SDimitry Andric MSAReg w6; 3360b57cec5SDimitry Andric MSAReg w7; 3370b57cec5SDimitry Andric MSAReg w8; 3380b57cec5SDimitry Andric MSAReg w9; 3390b57cec5SDimitry Andric MSAReg w10; 3400b57cec5SDimitry Andric MSAReg w11; 3410b57cec5SDimitry Andric MSAReg w12; 3420b57cec5SDimitry Andric MSAReg w13; 3430b57cec5SDimitry Andric MSAReg w14; 3440b57cec5SDimitry Andric MSAReg w15; 3450b57cec5SDimitry Andric MSAReg w16; 3460b57cec5SDimitry Andric MSAReg w17; 3470b57cec5SDimitry Andric MSAReg w18; 3480b57cec5SDimitry Andric MSAReg w19; 3490b57cec5SDimitry Andric MSAReg w20; 3500b57cec5SDimitry Andric MSAReg w21; 3510b57cec5SDimitry Andric MSAReg w22; 3520b57cec5SDimitry Andric MSAReg w23; 3530b57cec5SDimitry Andric MSAReg w24; 3540b57cec5SDimitry Andric MSAReg w25; 3550b57cec5SDimitry Andric MSAReg w26; 3560b57cec5SDimitry Andric MSAReg w27; 3570b57cec5SDimitry Andric MSAReg w28; 3580b57cec5SDimitry Andric MSAReg w29; 3590b57cec5SDimitry Andric MSAReg w30; 3600b57cec5SDimitry Andric MSAReg w31; 3610b57cec5SDimitry Andric uint32_t fcsr; /* FPU control status register */ 3620b57cec5SDimitry Andric uint32_t fir; /* FPU implementaion revision */ 3630b57cec5SDimitry Andric uint32_t mcsr; /* MSA control status register */ 3640b57cec5SDimitry Andric uint32_t mir; /* MSA implementation revision */ 3650b57cec5SDimitry Andric uint32_t config5; /* Config5 register */ 3660b57cec5SDimitry Andric }; 3670b57cec5SDimitry Andric 3680b57cec5SDimitry Andric struct UserArea { 3690b57cec5SDimitry Andric GPR_linux_mips gpr; // General purpose registers. 3700b57cec5SDimitry Andric FPR_linux_mips fpr; // Floating point registers. 3710b57cec5SDimitry Andric MSA_linux_mips msa; // MSA registers. 3720b57cec5SDimitry Andric }; 3730b57cec5SDimitry Andric 374*5ffd83dbSDimitry Andric #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H 375