1349cc55cSDimitry Andric //===----------------------------------------------------------------------===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric // 80b57cec5SDimitry Andric // Compatible with libunwind API documented at: 90b57cec5SDimitry Andric // http://www.nongnu.org/libunwind/man/libunwind(3).html 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef __LIBUNWIND__ 140b57cec5SDimitry Andric #define __LIBUNWIND__ 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include <__libunwind_config.h> 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include <stdint.h> 190b57cec5SDimitry Andric #include <stddef.h> 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric #ifdef __APPLE__ 220b57cec5SDimitry Andric #if __clang__ 230b57cec5SDimitry Andric #if __has_include(<Availability.h>) 240b57cec5SDimitry Andric #include <Availability.h> 250b57cec5SDimitry Andric #endif 260b57cec5SDimitry Andric #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050 270b57cec5SDimitry Andric #include <Availability.h> 280b57cec5SDimitry Andric #endif 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric #ifdef __arm__ 310b57cec5SDimitry Andric #define LIBUNWIND_AVAIL __attribute__((unavailable)) 320b57cec5SDimitry Andric #elif defined(__OSX_AVAILABLE_STARTING) 330b57cec5SDimitry Andric #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0) 340b57cec5SDimitry Andric #else 350b57cec5SDimitry Andric #include <AvailabilityMacros.h> 360b57cec5SDimitry Andric #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 370b57cec5SDimitry Andric #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 380b57cec5SDimitry Andric #else 390b57cec5SDimitry Andric #define LIBUNWIND_AVAIL __attribute__((unavailable)) 400b57cec5SDimitry Andric #endif 410b57cec5SDimitry Andric #endif 420b57cec5SDimitry Andric #else 430b57cec5SDimitry Andric #define LIBUNWIND_AVAIL 440b57cec5SDimitry Andric #endif 450b57cec5SDimitry Andric 46e8d8bef9SDimitry Andric #if defined(_WIN32) && defined(__SEH__) 47e8d8bef9SDimitry Andric #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR __attribute__((__aligned__(16))) 48e8d8bef9SDimitry Andric #else 49e8d8bef9SDimitry Andric #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR 50e8d8bef9SDimitry Andric #endif 51e8d8bef9SDimitry Andric 520b57cec5SDimitry Andric /* error codes */ 530b57cec5SDimitry Andric enum { 540b57cec5SDimitry Andric UNW_ESUCCESS = 0, /* no error */ 550b57cec5SDimitry Andric UNW_EUNSPEC = -6540, /* unspecified (general) error */ 560b57cec5SDimitry Andric UNW_ENOMEM = -6541, /* out of memory */ 570b57cec5SDimitry Andric UNW_EBADREG = -6542, /* bad register number */ 580b57cec5SDimitry Andric UNW_EREADONLYREG = -6543, /* attempt to write read-only register */ 590b57cec5SDimitry Andric UNW_ESTOPUNWIND = -6544, /* stop unwinding */ 600b57cec5SDimitry Andric UNW_EINVALIDIP = -6545, /* invalid IP */ 610b57cec5SDimitry Andric UNW_EBADFRAME = -6546, /* bad frame */ 620b57cec5SDimitry Andric UNW_EINVAL = -6547, /* unsupported operation or bad value */ 630b57cec5SDimitry Andric UNW_EBADVERSION = -6548, /* unwind info has unsupported version */ 640b57cec5SDimitry Andric UNW_ENOINFO = -6549 /* no unwind info found */ 650b57cec5SDimitry Andric #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY) 660b57cec5SDimitry Andric , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */ 670b57cec5SDimitry Andric #endif 680b57cec5SDimitry Andric }; 690b57cec5SDimitry Andric 700b57cec5SDimitry Andric struct unw_context_t { 710b57cec5SDimitry Andric uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; 720b57cec5SDimitry Andric }; 730b57cec5SDimitry Andric typedef struct unw_context_t unw_context_t; 740b57cec5SDimitry Andric 750b57cec5SDimitry Andric struct unw_cursor_t { 760b57cec5SDimitry Andric uint64_t data[_LIBUNWIND_CURSOR_SIZE]; 77e8d8bef9SDimitry Andric } LIBUNWIND_CURSOR_ALIGNMENT_ATTR; 780b57cec5SDimitry Andric typedef struct unw_cursor_t unw_cursor_t; 790b57cec5SDimitry Andric 800b57cec5SDimitry Andric typedef struct unw_addr_space *unw_addr_space_t; 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric typedef int unw_regnum_t; 830b57cec5SDimitry Andric typedef uintptr_t unw_word_t; 8481ad6265SDimitry Andric #if defined(__arm__) && !defined(__ARM_DWARF_EH__) && !defined(__SEH__) 850b57cec5SDimitry Andric typedef uint64_t unw_fpreg_t; 860b57cec5SDimitry Andric #else 870b57cec5SDimitry Andric typedef double unw_fpreg_t; 880b57cec5SDimitry Andric #endif 890b57cec5SDimitry Andric 900b57cec5SDimitry Andric struct unw_proc_info_t { 910b57cec5SDimitry Andric unw_word_t start_ip; /* start address of function */ 920b57cec5SDimitry Andric unw_word_t end_ip; /* address after end of function */ 930b57cec5SDimitry Andric unw_word_t lsda; /* address of language specific data area, */ 940b57cec5SDimitry Andric /* or zero if not used */ 950b57cec5SDimitry Andric unw_word_t handler; /* personality routine, or zero if not used */ 960b57cec5SDimitry Andric unw_word_t gp; /* not used */ 970b57cec5SDimitry Andric unw_word_t flags; /* not used */ 980b57cec5SDimitry Andric uint32_t format; /* compact unwind encoding, or zero if none */ 990b57cec5SDimitry Andric uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */ 1000b57cec5SDimitry Andric unw_word_t unwind_info; /* address of DWARF unwind info, or zero */ 1010b57cec5SDimitry Andric unw_word_t extra; /* mach_header of mach-o image containing func */ 1020b57cec5SDimitry Andric }; 1030b57cec5SDimitry Andric typedef struct unw_proc_info_t unw_proc_info_t; 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric #ifdef __cplusplus 1060b57cec5SDimitry Andric extern "C" { 1070b57cec5SDimitry Andric #endif 1080b57cec5SDimitry Andric 1090b57cec5SDimitry Andric extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL; 1100b57cec5SDimitry Andric extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL; 1110b57cec5SDimitry Andric extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL; 1120b57cec5SDimitry Andric extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL; 1130b57cec5SDimitry Andric extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL; 1140b57cec5SDimitry Andric extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL; 1150b57cec5SDimitry Andric extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL; 1160b57cec5SDimitry Andric extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL; 1170b57cec5SDimitry Andric 1180b57cec5SDimitry Andric #ifdef __arm__ 1190b57cec5SDimitry Andric /* Save VFP registers in FSTMX format (instead of FSTMD). */ 1200b57cec5SDimitry Andric extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL; 1210b57cec5SDimitry Andric #endif 1220b57cec5SDimitry Andric 12381ad6265SDimitry Andric #ifdef _AIX 12481ad6265SDimitry Andric extern uintptr_t unw_get_data_rel_base(unw_cursor_t *) LIBUNWIND_AVAIL; 12581ad6265SDimitry Andric #endif 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 1280b57cec5SDimitry Andric extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL; 1290b57cec5SDimitry Andric extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 1300b57cec5SDimitry Andric extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL; 1310b57cec5SDimitry Andric extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL; 1320b57cec5SDimitry Andric //extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*); 1330b57cec5SDimitry Andric 1340b57cec5SDimitry Andric extern unw_addr_space_t unw_local_addr_space; 1350b57cec5SDimitry Andric 1360b57cec5SDimitry Andric #ifdef __cplusplus 1370b57cec5SDimitry Andric } 1380b57cec5SDimitry Andric #endif 1390b57cec5SDimitry Andric 1400b57cec5SDimitry Andric // architecture independent register numbers 1410b57cec5SDimitry Andric enum { 1420b57cec5SDimitry Andric UNW_REG_IP = -1, // instruction pointer 1430b57cec5SDimitry Andric UNW_REG_SP = -2, // stack pointer 1440b57cec5SDimitry Andric }; 1450b57cec5SDimitry Andric 1460b57cec5SDimitry Andric // 32-bit x86 registers 1470b57cec5SDimitry Andric enum { 1480b57cec5SDimitry Andric UNW_X86_EAX = 0, 1490b57cec5SDimitry Andric UNW_X86_ECX = 1, 1500b57cec5SDimitry Andric UNW_X86_EDX = 2, 1510b57cec5SDimitry Andric UNW_X86_EBX = 3, 1520b57cec5SDimitry Andric UNW_X86_EBP = 4, 1530b57cec5SDimitry Andric UNW_X86_ESP = 5, 1540b57cec5SDimitry Andric UNW_X86_ESI = 6, 1550b57cec5SDimitry Andric UNW_X86_EDI = 7 1560b57cec5SDimitry Andric }; 1570b57cec5SDimitry Andric 1580b57cec5SDimitry Andric // 64-bit x86_64 registers 1590b57cec5SDimitry Andric enum { 1600b57cec5SDimitry Andric UNW_X86_64_RAX = 0, 1610b57cec5SDimitry Andric UNW_X86_64_RDX = 1, 1620b57cec5SDimitry Andric UNW_X86_64_RCX = 2, 1630b57cec5SDimitry Andric UNW_X86_64_RBX = 3, 1640b57cec5SDimitry Andric UNW_X86_64_RSI = 4, 1650b57cec5SDimitry Andric UNW_X86_64_RDI = 5, 1660b57cec5SDimitry Andric UNW_X86_64_RBP = 6, 1670b57cec5SDimitry Andric UNW_X86_64_RSP = 7, 1680b57cec5SDimitry Andric UNW_X86_64_R8 = 8, 1690b57cec5SDimitry Andric UNW_X86_64_R9 = 9, 1700b57cec5SDimitry Andric UNW_X86_64_R10 = 10, 1710b57cec5SDimitry Andric UNW_X86_64_R11 = 11, 1720b57cec5SDimitry Andric UNW_X86_64_R12 = 12, 1730b57cec5SDimitry Andric UNW_X86_64_R13 = 13, 1740b57cec5SDimitry Andric UNW_X86_64_R14 = 14, 1750b57cec5SDimitry Andric UNW_X86_64_R15 = 15, 1760b57cec5SDimitry Andric UNW_X86_64_RIP = 16, 1770b57cec5SDimitry Andric UNW_X86_64_XMM0 = 17, 1780b57cec5SDimitry Andric UNW_X86_64_XMM1 = 18, 1790b57cec5SDimitry Andric UNW_X86_64_XMM2 = 19, 1800b57cec5SDimitry Andric UNW_X86_64_XMM3 = 20, 1810b57cec5SDimitry Andric UNW_X86_64_XMM4 = 21, 1820b57cec5SDimitry Andric UNW_X86_64_XMM5 = 22, 1830b57cec5SDimitry Andric UNW_X86_64_XMM6 = 23, 1840b57cec5SDimitry Andric UNW_X86_64_XMM7 = 24, 1850b57cec5SDimitry Andric UNW_X86_64_XMM8 = 25, 1860b57cec5SDimitry Andric UNW_X86_64_XMM9 = 26, 1870b57cec5SDimitry Andric UNW_X86_64_XMM10 = 27, 1880b57cec5SDimitry Andric UNW_X86_64_XMM11 = 28, 1890b57cec5SDimitry Andric UNW_X86_64_XMM12 = 29, 1900b57cec5SDimitry Andric UNW_X86_64_XMM13 = 30, 1910b57cec5SDimitry Andric UNW_X86_64_XMM14 = 31, 1920b57cec5SDimitry Andric UNW_X86_64_XMM15 = 32, 1930b57cec5SDimitry Andric }; 1940b57cec5SDimitry Andric 1950b57cec5SDimitry Andric 1960b57cec5SDimitry Andric // 32-bit ppc register numbers 1970b57cec5SDimitry Andric enum { 1980b57cec5SDimitry Andric UNW_PPC_R0 = 0, 1990b57cec5SDimitry Andric UNW_PPC_R1 = 1, 2000b57cec5SDimitry Andric UNW_PPC_R2 = 2, 2010b57cec5SDimitry Andric UNW_PPC_R3 = 3, 2020b57cec5SDimitry Andric UNW_PPC_R4 = 4, 2030b57cec5SDimitry Andric UNW_PPC_R5 = 5, 2040b57cec5SDimitry Andric UNW_PPC_R6 = 6, 2050b57cec5SDimitry Andric UNW_PPC_R7 = 7, 2060b57cec5SDimitry Andric UNW_PPC_R8 = 8, 2070b57cec5SDimitry Andric UNW_PPC_R9 = 9, 2080b57cec5SDimitry Andric UNW_PPC_R10 = 10, 2090b57cec5SDimitry Andric UNW_PPC_R11 = 11, 2100b57cec5SDimitry Andric UNW_PPC_R12 = 12, 2110b57cec5SDimitry Andric UNW_PPC_R13 = 13, 2120b57cec5SDimitry Andric UNW_PPC_R14 = 14, 2130b57cec5SDimitry Andric UNW_PPC_R15 = 15, 2140b57cec5SDimitry Andric UNW_PPC_R16 = 16, 2150b57cec5SDimitry Andric UNW_PPC_R17 = 17, 2160b57cec5SDimitry Andric UNW_PPC_R18 = 18, 2170b57cec5SDimitry Andric UNW_PPC_R19 = 19, 2180b57cec5SDimitry Andric UNW_PPC_R20 = 20, 2190b57cec5SDimitry Andric UNW_PPC_R21 = 21, 2200b57cec5SDimitry Andric UNW_PPC_R22 = 22, 2210b57cec5SDimitry Andric UNW_PPC_R23 = 23, 2220b57cec5SDimitry Andric UNW_PPC_R24 = 24, 2230b57cec5SDimitry Andric UNW_PPC_R25 = 25, 2240b57cec5SDimitry Andric UNW_PPC_R26 = 26, 2250b57cec5SDimitry Andric UNW_PPC_R27 = 27, 2260b57cec5SDimitry Andric UNW_PPC_R28 = 28, 2270b57cec5SDimitry Andric UNW_PPC_R29 = 29, 2280b57cec5SDimitry Andric UNW_PPC_R30 = 30, 2290b57cec5SDimitry Andric UNW_PPC_R31 = 31, 2300b57cec5SDimitry Andric UNW_PPC_F0 = 32, 2310b57cec5SDimitry Andric UNW_PPC_F1 = 33, 2320b57cec5SDimitry Andric UNW_PPC_F2 = 34, 2330b57cec5SDimitry Andric UNW_PPC_F3 = 35, 2340b57cec5SDimitry Andric UNW_PPC_F4 = 36, 2350b57cec5SDimitry Andric UNW_PPC_F5 = 37, 2360b57cec5SDimitry Andric UNW_PPC_F6 = 38, 2370b57cec5SDimitry Andric UNW_PPC_F7 = 39, 2380b57cec5SDimitry Andric UNW_PPC_F8 = 40, 2390b57cec5SDimitry Andric UNW_PPC_F9 = 41, 2400b57cec5SDimitry Andric UNW_PPC_F10 = 42, 2410b57cec5SDimitry Andric UNW_PPC_F11 = 43, 2420b57cec5SDimitry Andric UNW_PPC_F12 = 44, 2430b57cec5SDimitry Andric UNW_PPC_F13 = 45, 2440b57cec5SDimitry Andric UNW_PPC_F14 = 46, 2450b57cec5SDimitry Andric UNW_PPC_F15 = 47, 2460b57cec5SDimitry Andric UNW_PPC_F16 = 48, 2470b57cec5SDimitry Andric UNW_PPC_F17 = 49, 2480b57cec5SDimitry Andric UNW_PPC_F18 = 50, 2490b57cec5SDimitry Andric UNW_PPC_F19 = 51, 2500b57cec5SDimitry Andric UNW_PPC_F20 = 52, 2510b57cec5SDimitry Andric UNW_PPC_F21 = 53, 2520b57cec5SDimitry Andric UNW_PPC_F22 = 54, 2530b57cec5SDimitry Andric UNW_PPC_F23 = 55, 2540b57cec5SDimitry Andric UNW_PPC_F24 = 56, 2550b57cec5SDimitry Andric UNW_PPC_F25 = 57, 2560b57cec5SDimitry Andric UNW_PPC_F26 = 58, 2570b57cec5SDimitry Andric UNW_PPC_F27 = 59, 2580b57cec5SDimitry Andric UNW_PPC_F28 = 60, 2590b57cec5SDimitry Andric UNW_PPC_F29 = 61, 2600b57cec5SDimitry Andric UNW_PPC_F30 = 62, 2610b57cec5SDimitry Andric UNW_PPC_F31 = 63, 2620b57cec5SDimitry Andric UNW_PPC_MQ = 64, 2630b57cec5SDimitry Andric UNW_PPC_LR = 65, 2640b57cec5SDimitry Andric UNW_PPC_CTR = 66, 2650b57cec5SDimitry Andric UNW_PPC_AP = 67, 2660b57cec5SDimitry Andric UNW_PPC_CR0 = 68, 2670b57cec5SDimitry Andric UNW_PPC_CR1 = 69, 2680b57cec5SDimitry Andric UNW_PPC_CR2 = 70, 2690b57cec5SDimitry Andric UNW_PPC_CR3 = 71, 2700b57cec5SDimitry Andric UNW_PPC_CR4 = 72, 2710b57cec5SDimitry Andric UNW_PPC_CR5 = 73, 2720b57cec5SDimitry Andric UNW_PPC_CR6 = 74, 2730b57cec5SDimitry Andric UNW_PPC_CR7 = 75, 2740b57cec5SDimitry Andric UNW_PPC_XER = 76, 2750b57cec5SDimitry Andric UNW_PPC_V0 = 77, 2760b57cec5SDimitry Andric UNW_PPC_V1 = 78, 2770b57cec5SDimitry Andric UNW_PPC_V2 = 79, 2780b57cec5SDimitry Andric UNW_PPC_V3 = 80, 2790b57cec5SDimitry Andric UNW_PPC_V4 = 81, 2800b57cec5SDimitry Andric UNW_PPC_V5 = 82, 2810b57cec5SDimitry Andric UNW_PPC_V6 = 83, 2820b57cec5SDimitry Andric UNW_PPC_V7 = 84, 2830b57cec5SDimitry Andric UNW_PPC_V8 = 85, 2840b57cec5SDimitry Andric UNW_PPC_V9 = 86, 2850b57cec5SDimitry Andric UNW_PPC_V10 = 87, 2860b57cec5SDimitry Andric UNW_PPC_V11 = 88, 2870b57cec5SDimitry Andric UNW_PPC_V12 = 89, 2880b57cec5SDimitry Andric UNW_PPC_V13 = 90, 2890b57cec5SDimitry Andric UNW_PPC_V14 = 91, 2900b57cec5SDimitry Andric UNW_PPC_V15 = 92, 2910b57cec5SDimitry Andric UNW_PPC_V16 = 93, 2920b57cec5SDimitry Andric UNW_PPC_V17 = 94, 2930b57cec5SDimitry Andric UNW_PPC_V18 = 95, 2940b57cec5SDimitry Andric UNW_PPC_V19 = 96, 2950b57cec5SDimitry Andric UNW_PPC_V20 = 97, 2960b57cec5SDimitry Andric UNW_PPC_V21 = 98, 2970b57cec5SDimitry Andric UNW_PPC_V22 = 99, 2980b57cec5SDimitry Andric UNW_PPC_V23 = 100, 2990b57cec5SDimitry Andric UNW_PPC_V24 = 101, 3000b57cec5SDimitry Andric UNW_PPC_V25 = 102, 3010b57cec5SDimitry Andric UNW_PPC_V26 = 103, 3020b57cec5SDimitry Andric UNW_PPC_V27 = 104, 3030b57cec5SDimitry Andric UNW_PPC_V28 = 105, 3040b57cec5SDimitry Andric UNW_PPC_V29 = 106, 3050b57cec5SDimitry Andric UNW_PPC_V30 = 107, 3060b57cec5SDimitry Andric UNW_PPC_V31 = 108, 3070b57cec5SDimitry Andric UNW_PPC_VRSAVE = 109, 3080b57cec5SDimitry Andric UNW_PPC_VSCR = 110, 3090b57cec5SDimitry Andric UNW_PPC_SPE_ACC = 111, 3100b57cec5SDimitry Andric UNW_PPC_SPEFSCR = 112 3110b57cec5SDimitry Andric }; 3120b57cec5SDimitry Andric 3130b57cec5SDimitry Andric // 64-bit ppc register numbers 3140b57cec5SDimitry Andric enum { 3150b57cec5SDimitry Andric UNW_PPC64_R0 = 0, 3160b57cec5SDimitry Andric UNW_PPC64_R1 = 1, 3170b57cec5SDimitry Andric UNW_PPC64_R2 = 2, 3180b57cec5SDimitry Andric UNW_PPC64_R3 = 3, 3190b57cec5SDimitry Andric UNW_PPC64_R4 = 4, 3200b57cec5SDimitry Andric UNW_PPC64_R5 = 5, 3210b57cec5SDimitry Andric UNW_PPC64_R6 = 6, 3220b57cec5SDimitry Andric UNW_PPC64_R7 = 7, 3230b57cec5SDimitry Andric UNW_PPC64_R8 = 8, 3240b57cec5SDimitry Andric UNW_PPC64_R9 = 9, 3250b57cec5SDimitry Andric UNW_PPC64_R10 = 10, 3260b57cec5SDimitry Andric UNW_PPC64_R11 = 11, 3270b57cec5SDimitry Andric UNW_PPC64_R12 = 12, 3280b57cec5SDimitry Andric UNW_PPC64_R13 = 13, 3290b57cec5SDimitry Andric UNW_PPC64_R14 = 14, 3300b57cec5SDimitry Andric UNW_PPC64_R15 = 15, 3310b57cec5SDimitry Andric UNW_PPC64_R16 = 16, 3320b57cec5SDimitry Andric UNW_PPC64_R17 = 17, 3330b57cec5SDimitry Andric UNW_PPC64_R18 = 18, 3340b57cec5SDimitry Andric UNW_PPC64_R19 = 19, 3350b57cec5SDimitry Andric UNW_PPC64_R20 = 20, 3360b57cec5SDimitry Andric UNW_PPC64_R21 = 21, 3370b57cec5SDimitry Andric UNW_PPC64_R22 = 22, 3380b57cec5SDimitry Andric UNW_PPC64_R23 = 23, 3390b57cec5SDimitry Andric UNW_PPC64_R24 = 24, 3400b57cec5SDimitry Andric UNW_PPC64_R25 = 25, 3410b57cec5SDimitry Andric UNW_PPC64_R26 = 26, 3420b57cec5SDimitry Andric UNW_PPC64_R27 = 27, 3430b57cec5SDimitry Andric UNW_PPC64_R28 = 28, 3440b57cec5SDimitry Andric UNW_PPC64_R29 = 29, 3450b57cec5SDimitry Andric UNW_PPC64_R30 = 30, 3460b57cec5SDimitry Andric UNW_PPC64_R31 = 31, 3470b57cec5SDimitry Andric UNW_PPC64_F0 = 32, 3480b57cec5SDimitry Andric UNW_PPC64_F1 = 33, 3490b57cec5SDimitry Andric UNW_PPC64_F2 = 34, 3500b57cec5SDimitry Andric UNW_PPC64_F3 = 35, 3510b57cec5SDimitry Andric UNW_PPC64_F4 = 36, 3520b57cec5SDimitry Andric UNW_PPC64_F5 = 37, 3530b57cec5SDimitry Andric UNW_PPC64_F6 = 38, 3540b57cec5SDimitry Andric UNW_PPC64_F7 = 39, 3550b57cec5SDimitry Andric UNW_PPC64_F8 = 40, 3560b57cec5SDimitry Andric UNW_PPC64_F9 = 41, 3570b57cec5SDimitry Andric UNW_PPC64_F10 = 42, 3580b57cec5SDimitry Andric UNW_PPC64_F11 = 43, 3590b57cec5SDimitry Andric UNW_PPC64_F12 = 44, 3600b57cec5SDimitry Andric UNW_PPC64_F13 = 45, 3610b57cec5SDimitry Andric UNW_PPC64_F14 = 46, 3620b57cec5SDimitry Andric UNW_PPC64_F15 = 47, 3630b57cec5SDimitry Andric UNW_PPC64_F16 = 48, 3640b57cec5SDimitry Andric UNW_PPC64_F17 = 49, 3650b57cec5SDimitry Andric UNW_PPC64_F18 = 50, 3660b57cec5SDimitry Andric UNW_PPC64_F19 = 51, 3670b57cec5SDimitry Andric UNW_PPC64_F20 = 52, 3680b57cec5SDimitry Andric UNW_PPC64_F21 = 53, 3690b57cec5SDimitry Andric UNW_PPC64_F22 = 54, 3700b57cec5SDimitry Andric UNW_PPC64_F23 = 55, 3710b57cec5SDimitry Andric UNW_PPC64_F24 = 56, 3720b57cec5SDimitry Andric UNW_PPC64_F25 = 57, 3730b57cec5SDimitry Andric UNW_PPC64_F26 = 58, 3740b57cec5SDimitry Andric UNW_PPC64_F27 = 59, 3750b57cec5SDimitry Andric UNW_PPC64_F28 = 60, 3760b57cec5SDimitry Andric UNW_PPC64_F29 = 61, 3770b57cec5SDimitry Andric UNW_PPC64_F30 = 62, 3780b57cec5SDimitry Andric UNW_PPC64_F31 = 63, 3790b57cec5SDimitry Andric // 64: reserved 3800b57cec5SDimitry Andric UNW_PPC64_LR = 65, 3810b57cec5SDimitry Andric UNW_PPC64_CTR = 66, 3820b57cec5SDimitry Andric // 67: reserved 3830b57cec5SDimitry Andric UNW_PPC64_CR0 = 68, 3840b57cec5SDimitry Andric UNW_PPC64_CR1 = 69, 3850b57cec5SDimitry Andric UNW_PPC64_CR2 = 70, 3860b57cec5SDimitry Andric UNW_PPC64_CR3 = 71, 3870b57cec5SDimitry Andric UNW_PPC64_CR4 = 72, 3880b57cec5SDimitry Andric UNW_PPC64_CR5 = 73, 3890b57cec5SDimitry Andric UNW_PPC64_CR6 = 74, 3900b57cec5SDimitry Andric UNW_PPC64_CR7 = 75, 3910b57cec5SDimitry Andric UNW_PPC64_XER = 76, 3920b57cec5SDimitry Andric UNW_PPC64_V0 = 77, 3930b57cec5SDimitry Andric UNW_PPC64_V1 = 78, 3940b57cec5SDimitry Andric UNW_PPC64_V2 = 79, 3950b57cec5SDimitry Andric UNW_PPC64_V3 = 80, 3960b57cec5SDimitry Andric UNW_PPC64_V4 = 81, 3970b57cec5SDimitry Andric UNW_PPC64_V5 = 82, 3980b57cec5SDimitry Andric UNW_PPC64_V6 = 83, 3990b57cec5SDimitry Andric UNW_PPC64_V7 = 84, 4000b57cec5SDimitry Andric UNW_PPC64_V8 = 85, 4010b57cec5SDimitry Andric UNW_PPC64_V9 = 86, 4020b57cec5SDimitry Andric UNW_PPC64_V10 = 87, 4030b57cec5SDimitry Andric UNW_PPC64_V11 = 88, 4040b57cec5SDimitry Andric UNW_PPC64_V12 = 89, 4050b57cec5SDimitry Andric UNW_PPC64_V13 = 90, 4060b57cec5SDimitry Andric UNW_PPC64_V14 = 91, 4070b57cec5SDimitry Andric UNW_PPC64_V15 = 92, 4080b57cec5SDimitry Andric UNW_PPC64_V16 = 93, 4090b57cec5SDimitry Andric UNW_PPC64_V17 = 94, 4100b57cec5SDimitry Andric UNW_PPC64_V18 = 95, 4110b57cec5SDimitry Andric UNW_PPC64_V19 = 96, 4120b57cec5SDimitry Andric UNW_PPC64_V20 = 97, 4130b57cec5SDimitry Andric UNW_PPC64_V21 = 98, 4140b57cec5SDimitry Andric UNW_PPC64_V22 = 99, 4150b57cec5SDimitry Andric UNW_PPC64_V23 = 100, 4160b57cec5SDimitry Andric UNW_PPC64_V24 = 101, 4170b57cec5SDimitry Andric UNW_PPC64_V25 = 102, 4180b57cec5SDimitry Andric UNW_PPC64_V26 = 103, 4190b57cec5SDimitry Andric UNW_PPC64_V27 = 104, 4200b57cec5SDimitry Andric UNW_PPC64_V28 = 105, 4210b57cec5SDimitry Andric UNW_PPC64_V29 = 106, 4220b57cec5SDimitry Andric UNW_PPC64_V30 = 107, 4230b57cec5SDimitry Andric UNW_PPC64_V31 = 108, 4240b57cec5SDimitry Andric // 109, 111-113: OpenPOWER ELF V2 ABI: reserved 4250b57cec5SDimitry Andric // Borrowing VRSAVE number from PPC32. 4260b57cec5SDimitry Andric UNW_PPC64_VRSAVE = 109, 4270b57cec5SDimitry Andric UNW_PPC64_VSCR = 110, 4280b57cec5SDimitry Andric UNW_PPC64_TFHAR = 114, 4290b57cec5SDimitry Andric UNW_PPC64_TFIAR = 115, 4300b57cec5SDimitry Andric UNW_PPC64_TEXASR = 116, 4310b57cec5SDimitry Andric UNW_PPC64_VS0 = UNW_PPC64_F0, 4320b57cec5SDimitry Andric UNW_PPC64_VS1 = UNW_PPC64_F1, 4330b57cec5SDimitry Andric UNW_PPC64_VS2 = UNW_PPC64_F2, 4340b57cec5SDimitry Andric UNW_PPC64_VS3 = UNW_PPC64_F3, 4350b57cec5SDimitry Andric UNW_PPC64_VS4 = UNW_PPC64_F4, 4360b57cec5SDimitry Andric UNW_PPC64_VS5 = UNW_PPC64_F5, 4370b57cec5SDimitry Andric UNW_PPC64_VS6 = UNW_PPC64_F6, 4380b57cec5SDimitry Andric UNW_PPC64_VS7 = UNW_PPC64_F7, 4390b57cec5SDimitry Andric UNW_PPC64_VS8 = UNW_PPC64_F8, 4400b57cec5SDimitry Andric UNW_PPC64_VS9 = UNW_PPC64_F9, 4410b57cec5SDimitry Andric UNW_PPC64_VS10 = UNW_PPC64_F10, 4420b57cec5SDimitry Andric UNW_PPC64_VS11 = UNW_PPC64_F11, 4430b57cec5SDimitry Andric UNW_PPC64_VS12 = UNW_PPC64_F12, 4440b57cec5SDimitry Andric UNW_PPC64_VS13 = UNW_PPC64_F13, 4450b57cec5SDimitry Andric UNW_PPC64_VS14 = UNW_PPC64_F14, 4460b57cec5SDimitry Andric UNW_PPC64_VS15 = UNW_PPC64_F15, 4470b57cec5SDimitry Andric UNW_PPC64_VS16 = UNW_PPC64_F16, 4480b57cec5SDimitry Andric UNW_PPC64_VS17 = UNW_PPC64_F17, 4490b57cec5SDimitry Andric UNW_PPC64_VS18 = UNW_PPC64_F18, 4500b57cec5SDimitry Andric UNW_PPC64_VS19 = UNW_PPC64_F19, 4510b57cec5SDimitry Andric UNW_PPC64_VS20 = UNW_PPC64_F20, 4520b57cec5SDimitry Andric UNW_PPC64_VS21 = UNW_PPC64_F21, 4530b57cec5SDimitry Andric UNW_PPC64_VS22 = UNW_PPC64_F22, 4540b57cec5SDimitry Andric UNW_PPC64_VS23 = UNW_PPC64_F23, 4550b57cec5SDimitry Andric UNW_PPC64_VS24 = UNW_PPC64_F24, 4560b57cec5SDimitry Andric UNW_PPC64_VS25 = UNW_PPC64_F25, 4570b57cec5SDimitry Andric UNW_PPC64_VS26 = UNW_PPC64_F26, 4580b57cec5SDimitry Andric UNW_PPC64_VS27 = UNW_PPC64_F27, 4590b57cec5SDimitry Andric UNW_PPC64_VS28 = UNW_PPC64_F28, 4600b57cec5SDimitry Andric UNW_PPC64_VS29 = UNW_PPC64_F29, 4610b57cec5SDimitry Andric UNW_PPC64_VS30 = UNW_PPC64_F30, 4620b57cec5SDimitry Andric UNW_PPC64_VS31 = UNW_PPC64_F31, 4630b57cec5SDimitry Andric UNW_PPC64_VS32 = UNW_PPC64_V0, 4640b57cec5SDimitry Andric UNW_PPC64_VS33 = UNW_PPC64_V1, 4650b57cec5SDimitry Andric UNW_PPC64_VS34 = UNW_PPC64_V2, 4660b57cec5SDimitry Andric UNW_PPC64_VS35 = UNW_PPC64_V3, 4670b57cec5SDimitry Andric UNW_PPC64_VS36 = UNW_PPC64_V4, 4680b57cec5SDimitry Andric UNW_PPC64_VS37 = UNW_PPC64_V5, 4690b57cec5SDimitry Andric UNW_PPC64_VS38 = UNW_PPC64_V6, 4700b57cec5SDimitry Andric UNW_PPC64_VS39 = UNW_PPC64_V7, 4710b57cec5SDimitry Andric UNW_PPC64_VS40 = UNW_PPC64_V8, 4720b57cec5SDimitry Andric UNW_PPC64_VS41 = UNW_PPC64_V9, 4730b57cec5SDimitry Andric UNW_PPC64_VS42 = UNW_PPC64_V10, 4740b57cec5SDimitry Andric UNW_PPC64_VS43 = UNW_PPC64_V11, 4750b57cec5SDimitry Andric UNW_PPC64_VS44 = UNW_PPC64_V12, 4760b57cec5SDimitry Andric UNW_PPC64_VS45 = UNW_PPC64_V13, 4770b57cec5SDimitry Andric UNW_PPC64_VS46 = UNW_PPC64_V14, 4780b57cec5SDimitry Andric UNW_PPC64_VS47 = UNW_PPC64_V15, 4790b57cec5SDimitry Andric UNW_PPC64_VS48 = UNW_PPC64_V16, 4800b57cec5SDimitry Andric UNW_PPC64_VS49 = UNW_PPC64_V17, 4810b57cec5SDimitry Andric UNW_PPC64_VS50 = UNW_PPC64_V18, 4820b57cec5SDimitry Andric UNW_PPC64_VS51 = UNW_PPC64_V19, 4830b57cec5SDimitry Andric UNW_PPC64_VS52 = UNW_PPC64_V20, 4840b57cec5SDimitry Andric UNW_PPC64_VS53 = UNW_PPC64_V21, 4850b57cec5SDimitry Andric UNW_PPC64_VS54 = UNW_PPC64_V22, 4860b57cec5SDimitry Andric UNW_PPC64_VS55 = UNW_PPC64_V23, 4870b57cec5SDimitry Andric UNW_PPC64_VS56 = UNW_PPC64_V24, 4880b57cec5SDimitry Andric UNW_PPC64_VS57 = UNW_PPC64_V25, 4890b57cec5SDimitry Andric UNW_PPC64_VS58 = UNW_PPC64_V26, 4900b57cec5SDimitry Andric UNW_PPC64_VS59 = UNW_PPC64_V27, 4910b57cec5SDimitry Andric UNW_PPC64_VS60 = UNW_PPC64_V28, 4920b57cec5SDimitry Andric UNW_PPC64_VS61 = UNW_PPC64_V29, 4930b57cec5SDimitry Andric UNW_PPC64_VS62 = UNW_PPC64_V30, 4940b57cec5SDimitry Andric UNW_PPC64_VS63 = UNW_PPC64_V31 4950b57cec5SDimitry Andric }; 4960b57cec5SDimitry Andric 4970b57cec5SDimitry Andric // 64-bit ARM64 registers 4980b57cec5SDimitry Andric enum { 499349cc55cSDimitry Andric UNW_AARCH64_X0 = 0, 500349cc55cSDimitry Andric UNW_AARCH64_X1 = 1, 501349cc55cSDimitry Andric UNW_AARCH64_X2 = 2, 502349cc55cSDimitry Andric UNW_AARCH64_X3 = 3, 503349cc55cSDimitry Andric UNW_AARCH64_X4 = 4, 504349cc55cSDimitry Andric UNW_AARCH64_X5 = 5, 505349cc55cSDimitry Andric UNW_AARCH64_X6 = 6, 506349cc55cSDimitry Andric UNW_AARCH64_X7 = 7, 507349cc55cSDimitry Andric UNW_AARCH64_X8 = 8, 508349cc55cSDimitry Andric UNW_AARCH64_X9 = 9, 509349cc55cSDimitry Andric UNW_AARCH64_X10 = 10, 510349cc55cSDimitry Andric UNW_AARCH64_X11 = 11, 511349cc55cSDimitry Andric UNW_AARCH64_X12 = 12, 512349cc55cSDimitry Andric UNW_AARCH64_X13 = 13, 513349cc55cSDimitry Andric UNW_AARCH64_X14 = 14, 514349cc55cSDimitry Andric UNW_AARCH64_X15 = 15, 515349cc55cSDimitry Andric UNW_AARCH64_X16 = 16, 516349cc55cSDimitry Andric UNW_AARCH64_X17 = 17, 517349cc55cSDimitry Andric UNW_AARCH64_X18 = 18, 518349cc55cSDimitry Andric UNW_AARCH64_X19 = 19, 519349cc55cSDimitry Andric UNW_AARCH64_X20 = 20, 520349cc55cSDimitry Andric UNW_AARCH64_X21 = 21, 521349cc55cSDimitry Andric UNW_AARCH64_X22 = 22, 522349cc55cSDimitry Andric UNW_AARCH64_X23 = 23, 523349cc55cSDimitry Andric UNW_AARCH64_X24 = 24, 524349cc55cSDimitry Andric UNW_AARCH64_X25 = 25, 525349cc55cSDimitry Andric UNW_AARCH64_X26 = 26, 526349cc55cSDimitry Andric UNW_AARCH64_X27 = 27, 527349cc55cSDimitry Andric UNW_AARCH64_X28 = 28, 528349cc55cSDimitry Andric UNW_AARCH64_X29 = 29, 529349cc55cSDimitry Andric UNW_AARCH64_FP = 29, 530349cc55cSDimitry Andric UNW_AARCH64_X30 = 30, 531349cc55cSDimitry Andric UNW_AARCH64_LR = 30, 532349cc55cSDimitry Andric UNW_AARCH64_X31 = 31, 533349cc55cSDimitry Andric UNW_AARCH64_SP = 31, 534349cc55cSDimitry Andric UNW_AARCH64_PC = 32, 535349cc55cSDimitry Andric 5360b57cec5SDimitry Andric // reserved block 537349cc55cSDimitry Andric UNW_AARCH64_RA_SIGN_STATE = 34, 538349cc55cSDimitry Andric 539349cc55cSDimitry Andric // FP/vector registers 540349cc55cSDimitry Andric UNW_AARCH64_V0 = 64, 541349cc55cSDimitry Andric UNW_AARCH64_V1 = 65, 542349cc55cSDimitry Andric UNW_AARCH64_V2 = 66, 543349cc55cSDimitry Andric UNW_AARCH64_V3 = 67, 544349cc55cSDimitry Andric UNW_AARCH64_V4 = 68, 545349cc55cSDimitry Andric UNW_AARCH64_V5 = 69, 546349cc55cSDimitry Andric UNW_AARCH64_V6 = 70, 547349cc55cSDimitry Andric UNW_AARCH64_V7 = 71, 548349cc55cSDimitry Andric UNW_AARCH64_V8 = 72, 549349cc55cSDimitry Andric UNW_AARCH64_V9 = 73, 550349cc55cSDimitry Andric UNW_AARCH64_V10 = 74, 551349cc55cSDimitry Andric UNW_AARCH64_V11 = 75, 552349cc55cSDimitry Andric UNW_AARCH64_V12 = 76, 553349cc55cSDimitry Andric UNW_AARCH64_V13 = 77, 554349cc55cSDimitry Andric UNW_AARCH64_V14 = 78, 555349cc55cSDimitry Andric UNW_AARCH64_V15 = 79, 556349cc55cSDimitry Andric UNW_AARCH64_V16 = 80, 557349cc55cSDimitry Andric UNW_AARCH64_V17 = 81, 558349cc55cSDimitry Andric UNW_AARCH64_V18 = 82, 559349cc55cSDimitry Andric UNW_AARCH64_V19 = 83, 560349cc55cSDimitry Andric UNW_AARCH64_V20 = 84, 561349cc55cSDimitry Andric UNW_AARCH64_V21 = 85, 562349cc55cSDimitry Andric UNW_AARCH64_V22 = 86, 563349cc55cSDimitry Andric UNW_AARCH64_V23 = 87, 564349cc55cSDimitry Andric UNW_AARCH64_V24 = 88, 565349cc55cSDimitry Andric UNW_AARCH64_V25 = 89, 566349cc55cSDimitry Andric UNW_AARCH64_V26 = 90, 567349cc55cSDimitry Andric UNW_AARCH64_V27 = 91, 568349cc55cSDimitry Andric UNW_AARCH64_V28 = 92, 569349cc55cSDimitry Andric UNW_AARCH64_V29 = 93, 570349cc55cSDimitry Andric UNW_AARCH64_V30 = 94, 571349cc55cSDimitry Andric UNW_AARCH64_V31 = 95, 572349cc55cSDimitry Andric 573349cc55cSDimitry Andric // Compatibility aliases 574349cc55cSDimitry Andric UNW_ARM64_X0 = UNW_AARCH64_X0, 575349cc55cSDimitry Andric UNW_ARM64_X1 = UNW_AARCH64_X1, 576349cc55cSDimitry Andric UNW_ARM64_X2 = UNW_AARCH64_X2, 577349cc55cSDimitry Andric UNW_ARM64_X3 = UNW_AARCH64_X3, 578349cc55cSDimitry Andric UNW_ARM64_X4 = UNW_AARCH64_X4, 579349cc55cSDimitry Andric UNW_ARM64_X5 = UNW_AARCH64_X5, 580349cc55cSDimitry Andric UNW_ARM64_X6 = UNW_AARCH64_X6, 581349cc55cSDimitry Andric UNW_ARM64_X7 = UNW_AARCH64_X7, 582349cc55cSDimitry Andric UNW_ARM64_X8 = UNW_AARCH64_X8, 583349cc55cSDimitry Andric UNW_ARM64_X9 = UNW_AARCH64_X9, 584349cc55cSDimitry Andric UNW_ARM64_X10 = UNW_AARCH64_X10, 585349cc55cSDimitry Andric UNW_ARM64_X11 = UNW_AARCH64_X11, 586349cc55cSDimitry Andric UNW_ARM64_X12 = UNW_AARCH64_X12, 587349cc55cSDimitry Andric UNW_ARM64_X13 = UNW_AARCH64_X13, 588349cc55cSDimitry Andric UNW_ARM64_X14 = UNW_AARCH64_X14, 589349cc55cSDimitry Andric UNW_ARM64_X15 = UNW_AARCH64_X15, 590349cc55cSDimitry Andric UNW_ARM64_X16 = UNW_AARCH64_X16, 591349cc55cSDimitry Andric UNW_ARM64_X17 = UNW_AARCH64_X17, 592349cc55cSDimitry Andric UNW_ARM64_X18 = UNW_AARCH64_X18, 593349cc55cSDimitry Andric UNW_ARM64_X19 = UNW_AARCH64_X19, 594349cc55cSDimitry Andric UNW_ARM64_X20 = UNW_AARCH64_X20, 595349cc55cSDimitry Andric UNW_ARM64_X21 = UNW_AARCH64_X21, 596349cc55cSDimitry Andric UNW_ARM64_X22 = UNW_AARCH64_X22, 597349cc55cSDimitry Andric UNW_ARM64_X23 = UNW_AARCH64_X23, 598349cc55cSDimitry Andric UNW_ARM64_X24 = UNW_AARCH64_X24, 599349cc55cSDimitry Andric UNW_ARM64_X25 = UNW_AARCH64_X25, 600349cc55cSDimitry Andric UNW_ARM64_X26 = UNW_AARCH64_X26, 601349cc55cSDimitry Andric UNW_ARM64_X27 = UNW_AARCH64_X27, 602349cc55cSDimitry Andric UNW_ARM64_X28 = UNW_AARCH64_X28, 603349cc55cSDimitry Andric UNW_ARM64_X29 = UNW_AARCH64_X29, 604349cc55cSDimitry Andric UNW_ARM64_FP = UNW_AARCH64_FP, 605349cc55cSDimitry Andric UNW_ARM64_X30 = UNW_AARCH64_X30, 606349cc55cSDimitry Andric UNW_ARM64_LR = UNW_AARCH64_LR, 607349cc55cSDimitry Andric UNW_ARM64_X31 = UNW_AARCH64_X31, 608349cc55cSDimitry Andric UNW_ARM64_SP = UNW_AARCH64_SP, 609349cc55cSDimitry Andric UNW_ARM64_PC = UNW_AARCH64_PC, 610349cc55cSDimitry Andric UNW_ARM64_RA_SIGN_STATE = UNW_AARCH64_RA_SIGN_STATE, 611349cc55cSDimitry Andric UNW_ARM64_D0 = UNW_AARCH64_V0, 612349cc55cSDimitry Andric UNW_ARM64_D1 = UNW_AARCH64_V1, 613349cc55cSDimitry Andric UNW_ARM64_D2 = UNW_AARCH64_V2, 614349cc55cSDimitry Andric UNW_ARM64_D3 = UNW_AARCH64_V3, 615349cc55cSDimitry Andric UNW_ARM64_D4 = UNW_AARCH64_V4, 616349cc55cSDimitry Andric UNW_ARM64_D5 = UNW_AARCH64_V5, 617349cc55cSDimitry Andric UNW_ARM64_D6 = UNW_AARCH64_V6, 618349cc55cSDimitry Andric UNW_ARM64_D7 = UNW_AARCH64_V7, 619349cc55cSDimitry Andric UNW_ARM64_D8 = UNW_AARCH64_V8, 620349cc55cSDimitry Andric UNW_ARM64_D9 = UNW_AARCH64_V9, 621349cc55cSDimitry Andric UNW_ARM64_D10 = UNW_AARCH64_V10, 622349cc55cSDimitry Andric UNW_ARM64_D11 = UNW_AARCH64_V11, 623349cc55cSDimitry Andric UNW_ARM64_D12 = UNW_AARCH64_V12, 624349cc55cSDimitry Andric UNW_ARM64_D13 = UNW_AARCH64_V13, 625349cc55cSDimitry Andric UNW_ARM64_D14 = UNW_AARCH64_V14, 626349cc55cSDimitry Andric UNW_ARM64_D15 = UNW_AARCH64_V15, 627349cc55cSDimitry Andric UNW_ARM64_D16 = UNW_AARCH64_V16, 628349cc55cSDimitry Andric UNW_ARM64_D17 = UNW_AARCH64_V17, 629349cc55cSDimitry Andric UNW_ARM64_D18 = UNW_AARCH64_V18, 630349cc55cSDimitry Andric UNW_ARM64_D19 = UNW_AARCH64_V19, 631349cc55cSDimitry Andric UNW_ARM64_D20 = UNW_AARCH64_V20, 632349cc55cSDimitry Andric UNW_ARM64_D21 = UNW_AARCH64_V21, 633349cc55cSDimitry Andric UNW_ARM64_D22 = UNW_AARCH64_V22, 634349cc55cSDimitry Andric UNW_ARM64_D23 = UNW_AARCH64_V23, 635349cc55cSDimitry Andric UNW_ARM64_D24 = UNW_AARCH64_V24, 636349cc55cSDimitry Andric UNW_ARM64_D25 = UNW_AARCH64_V25, 637349cc55cSDimitry Andric UNW_ARM64_D26 = UNW_AARCH64_V26, 638349cc55cSDimitry Andric UNW_ARM64_D27 = UNW_AARCH64_V27, 639349cc55cSDimitry Andric UNW_ARM64_D28 = UNW_AARCH64_V28, 640349cc55cSDimitry Andric UNW_ARM64_D29 = UNW_AARCH64_V29, 641349cc55cSDimitry Andric UNW_ARM64_D30 = UNW_AARCH64_V30, 642349cc55cSDimitry Andric UNW_ARM64_D31 = UNW_AARCH64_V31, 6430b57cec5SDimitry Andric }; 6440b57cec5SDimitry Andric 6450b57cec5SDimitry Andric // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1. 6460b57cec5SDimitry Andric // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3. 6470b57cec5SDimitry Andric // In this scheme, even though the 64-bit floating point registers D0-D31 6480b57cec5SDimitry Andric // overlap physically with the 32-bit floating pointer registers S0-S31, 6490b57cec5SDimitry Andric // they are given a non-overlapping range of register numbers. 6500b57cec5SDimitry Andric // 6510b57cec5SDimitry Andric // Commented out ranges are not preserved during unwinding. 6520b57cec5SDimitry Andric enum { 6530b57cec5SDimitry Andric UNW_ARM_R0 = 0, 6540b57cec5SDimitry Andric UNW_ARM_R1 = 1, 6550b57cec5SDimitry Andric UNW_ARM_R2 = 2, 6560b57cec5SDimitry Andric UNW_ARM_R3 = 3, 6570b57cec5SDimitry Andric UNW_ARM_R4 = 4, 6580b57cec5SDimitry Andric UNW_ARM_R5 = 5, 6590b57cec5SDimitry Andric UNW_ARM_R6 = 6, 6600b57cec5SDimitry Andric UNW_ARM_R7 = 7, 6610b57cec5SDimitry Andric UNW_ARM_R8 = 8, 6620b57cec5SDimitry Andric UNW_ARM_R9 = 9, 6630b57cec5SDimitry Andric UNW_ARM_R10 = 10, 6640b57cec5SDimitry Andric UNW_ARM_R11 = 11, 6650b57cec5SDimitry Andric UNW_ARM_R12 = 12, 6660b57cec5SDimitry Andric UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP 6670b57cec5SDimitry Andric UNW_ARM_R13 = 13, 6680b57cec5SDimitry Andric UNW_ARM_LR = 14, 6690b57cec5SDimitry Andric UNW_ARM_R14 = 14, 6700b57cec5SDimitry Andric UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP 6710b57cec5SDimitry Andric UNW_ARM_R15 = 15, 6720b57cec5SDimitry Andric // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31. 6730b57cec5SDimitry Andric UNW_ARM_S0 = 64, 6740b57cec5SDimitry Andric UNW_ARM_S1 = 65, 6750b57cec5SDimitry Andric UNW_ARM_S2 = 66, 6760b57cec5SDimitry Andric UNW_ARM_S3 = 67, 6770b57cec5SDimitry Andric UNW_ARM_S4 = 68, 6780b57cec5SDimitry Andric UNW_ARM_S5 = 69, 6790b57cec5SDimitry Andric UNW_ARM_S6 = 70, 6800b57cec5SDimitry Andric UNW_ARM_S7 = 71, 6810b57cec5SDimitry Andric UNW_ARM_S8 = 72, 6820b57cec5SDimitry Andric UNW_ARM_S9 = 73, 6830b57cec5SDimitry Andric UNW_ARM_S10 = 74, 6840b57cec5SDimitry Andric UNW_ARM_S11 = 75, 6850b57cec5SDimitry Andric UNW_ARM_S12 = 76, 6860b57cec5SDimitry Andric UNW_ARM_S13 = 77, 6870b57cec5SDimitry Andric UNW_ARM_S14 = 78, 6880b57cec5SDimitry Andric UNW_ARM_S15 = 79, 6890b57cec5SDimitry Andric UNW_ARM_S16 = 80, 6900b57cec5SDimitry Andric UNW_ARM_S17 = 81, 6910b57cec5SDimitry Andric UNW_ARM_S18 = 82, 6920b57cec5SDimitry Andric UNW_ARM_S19 = 83, 6930b57cec5SDimitry Andric UNW_ARM_S20 = 84, 6940b57cec5SDimitry Andric UNW_ARM_S21 = 85, 6950b57cec5SDimitry Andric UNW_ARM_S22 = 86, 6960b57cec5SDimitry Andric UNW_ARM_S23 = 87, 6970b57cec5SDimitry Andric UNW_ARM_S24 = 88, 6980b57cec5SDimitry Andric UNW_ARM_S25 = 89, 6990b57cec5SDimitry Andric UNW_ARM_S26 = 90, 7000b57cec5SDimitry Andric UNW_ARM_S27 = 91, 7010b57cec5SDimitry Andric UNW_ARM_S28 = 92, 7020b57cec5SDimitry Andric UNW_ARM_S29 = 93, 7030b57cec5SDimitry Andric UNW_ARM_S30 = 94, 7040b57cec5SDimitry Andric UNW_ARM_S31 = 95, 7050b57cec5SDimitry Andric // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP. 7060b57cec5SDimitry Andric // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX) 7070b57cec5SDimitry Andric UNW_ARM_WR0 = 112, 7080b57cec5SDimitry Andric UNW_ARM_WR1 = 113, 7090b57cec5SDimitry Andric UNW_ARM_WR2 = 114, 7100b57cec5SDimitry Andric UNW_ARM_WR3 = 115, 7110b57cec5SDimitry Andric UNW_ARM_WR4 = 116, 7120b57cec5SDimitry Andric UNW_ARM_WR5 = 117, 7130b57cec5SDimitry Andric UNW_ARM_WR6 = 118, 7140b57cec5SDimitry Andric UNW_ARM_WR7 = 119, 7150b57cec5SDimitry Andric UNW_ARM_WR8 = 120, 7160b57cec5SDimitry Andric UNW_ARM_WR9 = 121, 7170b57cec5SDimitry Andric UNW_ARM_WR10 = 122, 7180b57cec5SDimitry Andric UNW_ARM_WR11 = 123, 7190b57cec5SDimitry Andric UNW_ARM_WR12 = 124, 7200b57cec5SDimitry Andric UNW_ARM_WR13 = 125, 7210b57cec5SDimitry Andric UNW_ARM_WR14 = 126, 7220b57cec5SDimitry Andric UNW_ARM_WR15 = 127, 7230b57cec5SDimitry Andric // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC} 7240eae32dcSDimitry Andric // 134-142 -- Reserved 7250eae32dcSDimitry Andric UNW_ARM_RA_AUTH_CODE = 143, 7260b57cec5SDimitry Andric // 144-150 -- R8_USR-R14_USR 7270b57cec5SDimitry Andric // 151-157 -- R8_FIQ-R14_FIQ 7280b57cec5SDimitry Andric // 158-159 -- R13_IRQ-R14_IRQ 7290b57cec5SDimitry Andric // 160-161 -- R13_ABT-R14_ABT 7300b57cec5SDimitry Andric // 162-163 -- R13_UND-R14_UND 7310b57cec5SDimitry Andric // 164-165 -- R13_SVC-R14_SVC 7320b57cec5SDimitry Andric // 166-191 -- Reserved 7330b57cec5SDimitry Andric UNW_ARM_WC0 = 192, 7340b57cec5SDimitry Andric UNW_ARM_WC1 = 193, 7350b57cec5SDimitry Andric UNW_ARM_WC2 = 194, 7360b57cec5SDimitry Andric UNW_ARM_WC3 = 195, 7370b57cec5SDimitry Andric // 196-199 -- wC4-wC7 (Intel wireless MMX control) 7380b57cec5SDimitry Andric // 200-255 -- Reserved 7390b57cec5SDimitry Andric UNW_ARM_D0 = 256, 7400b57cec5SDimitry Andric UNW_ARM_D1 = 257, 7410b57cec5SDimitry Andric UNW_ARM_D2 = 258, 7420b57cec5SDimitry Andric UNW_ARM_D3 = 259, 7430b57cec5SDimitry Andric UNW_ARM_D4 = 260, 7440b57cec5SDimitry Andric UNW_ARM_D5 = 261, 7450b57cec5SDimitry Andric UNW_ARM_D6 = 262, 7460b57cec5SDimitry Andric UNW_ARM_D7 = 263, 7470b57cec5SDimitry Andric UNW_ARM_D8 = 264, 7480b57cec5SDimitry Andric UNW_ARM_D9 = 265, 7490b57cec5SDimitry Andric UNW_ARM_D10 = 266, 7500b57cec5SDimitry Andric UNW_ARM_D11 = 267, 7510b57cec5SDimitry Andric UNW_ARM_D12 = 268, 7520b57cec5SDimitry Andric UNW_ARM_D13 = 269, 7530b57cec5SDimitry Andric UNW_ARM_D14 = 270, 7540b57cec5SDimitry Andric UNW_ARM_D15 = 271, 7550b57cec5SDimitry Andric UNW_ARM_D16 = 272, 7560b57cec5SDimitry Andric UNW_ARM_D17 = 273, 7570b57cec5SDimitry Andric UNW_ARM_D18 = 274, 7580b57cec5SDimitry Andric UNW_ARM_D19 = 275, 7590b57cec5SDimitry Andric UNW_ARM_D20 = 276, 7600b57cec5SDimitry Andric UNW_ARM_D21 = 277, 7610b57cec5SDimitry Andric UNW_ARM_D22 = 278, 7620b57cec5SDimitry Andric UNW_ARM_D23 = 279, 7630b57cec5SDimitry Andric UNW_ARM_D24 = 280, 7640b57cec5SDimitry Andric UNW_ARM_D25 = 281, 7650b57cec5SDimitry Andric UNW_ARM_D26 = 282, 7660b57cec5SDimitry Andric UNW_ARM_D27 = 283, 7670b57cec5SDimitry Andric UNW_ARM_D28 = 284, 7680b57cec5SDimitry Andric UNW_ARM_D29 = 285, 7690b57cec5SDimitry Andric UNW_ARM_D30 = 286, 7700b57cec5SDimitry Andric UNW_ARM_D31 = 287, 7710b57cec5SDimitry Andric // 288-319 -- Reserved for VFP/Neon 7720b57cec5SDimitry Andric // 320-8191 -- Reserved 7730b57cec5SDimitry Andric // 8192-16383 -- Unspecified vendor co-processor register. 7740b57cec5SDimitry Andric }; 7750b57cec5SDimitry Andric 7760b57cec5SDimitry Andric // OpenRISC1000 register numbers 7770b57cec5SDimitry Andric enum { 7780b57cec5SDimitry Andric UNW_OR1K_R0 = 0, 7790b57cec5SDimitry Andric UNW_OR1K_R1 = 1, 7800b57cec5SDimitry Andric UNW_OR1K_R2 = 2, 7810b57cec5SDimitry Andric UNW_OR1K_R3 = 3, 7820b57cec5SDimitry Andric UNW_OR1K_R4 = 4, 7830b57cec5SDimitry Andric UNW_OR1K_R5 = 5, 7840b57cec5SDimitry Andric UNW_OR1K_R6 = 6, 7850b57cec5SDimitry Andric UNW_OR1K_R7 = 7, 7860b57cec5SDimitry Andric UNW_OR1K_R8 = 8, 7870b57cec5SDimitry Andric UNW_OR1K_R9 = 9, 7880b57cec5SDimitry Andric UNW_OR1K_R10 = 10, 7890b57cec5SDimitry Andric UNW_OR1K_R11 = 11, 7900b57cec5SDimitry Andric UNW_OR1K_R12 = 12, 7910b57cec5SDimitry Andric UNW_OR1K_R13 = 13, 7920b57cec5SDimitry Andric UNW_OR1K_R14 = 14, 7930b57cec5SDimitry Andric UNW_OR1K_R15 = 15, 7940b57cec5SDimitry Andric UNW_OR1K_R16 = 16, 7950b57cec5SDimitry Andric UNW_OR1K_R17 = 17, 7960b57cec5SDimitry Andric UNW_OR1K_R18 = 18, 7970b57cec5SDimitry Andric UNW_OR1K_R19 = 19, 7980b57cec5SDimitry Andric UNW_OR1K_R20 = 20, 7990b57cec5SDimitry Andric UNW_OR1K_R21 = 21, 8000b57cec5SDimitry Andric UNW_OR1K_R22 = 22, 8010b57cec5SDimitry Andric UNW_OR1K_R23 = 23, 8020b57cec5SDimitry Andric UNW_OR1K_R24 = 24, 8030b57cec5SDimitry Andric UNW_OR1K_R25 = 25, 8040b57cec5SDimitry Andric UNW_OR1K_R26 = 26, 8050b57cec5SDimitry Andric UNW_OR1K_R27 = 27, 8060b57cec5SDimitry Andric UNW_OR1K_R28 = 28, 8070b57cec5SDimitry Andric UNW_OR1K_R29 = 29, 8080b57cec5SDimitry Andric UNW_OR1K_R30 = 30, 8090b57cec5SDimitry Andric UNW_OR1K_R31 = 31, 8100b57cec5SDimitry Andric UNW_OR1K_EPCR = 32, 8110b57cec5SDimitry Andric }; 8120b57cec5SDimitry Andric 8130b57cec5SDimitry Andric // MIPS registers 8140b57cec5SDimitry Andric enum { 8150b57cec5SDimitry Andric UNW_MIPS_R0 = 0, 8160b57cec5SDimitry Andric UNW_MIPS_R1 = 1, 8170b57cec5SDimitry Andric UNW_MIPS_R2 = 2, 8180b57cec5SDimitry Andric UNW_MIPS_R3 = 3, 8190b57cec5SDimitry Andric UNW_MIPS_R4 = 4, 8200b57cec5SDimitry Andric UNW_MIPS_R5 = 5, 8210b57cec5SDimitry Andric UNW_MIPS_R6 = 6, 8220b57cec5SDimitry Andric UNW_MIPS_R7 = 7, 8230b57cec5SDimitry Andric UNW_MIPS_R8 = 8, 8240b57cec5SDimitry Andric UNW_MIPS_R9 = 9, 8250b57cec5SDimitry Andric UNW_MIPS_R10 = 10, 8260b57cec5SDimitry Andric UNW_MIPS_R11 = 11, 8270b57cec5SDimitry Andric UNW_MIPS_R12 = 12, 8280b57cec5SDimitry Andric UNW_MIPS_R13 = 13, 8290b57cec5SDimitry Andric UNW_MIPS_R14 = 14, 8300b57cec5SDimitry Andric UNW_MIPS_R15 = 15, 8310b57cec5SDimitry Andric UNW_MIPS_R16 = 16, 8320b57cec5SDimitry Andric UNW_MIPS_R17 = 17, 8330b57cec5SDimitry Andric UNW_MIPS_R18 = 18, 8340b57cec5SDimitry Andric UNW_MIPS_R19 = 19, 8350b57cec5SDimitry Andric UNW_MIPS_R20 = 20, 8360b57cec5SDimitry Andric UNW_MIPS_R21 = 21, 8370b57cec5SDimitry Andric UNW_MIPS_R22 = 22, 8380b57cec5SDimitry Andric UNW_MIPS_R23 = 23, 8390b57cec5SDimitry Andric UNW_MIPS_R24 = 24, 8400b57cec5SDimitry Andric UNW_MIPS_R25 = 25, 8410b57cec5SDimitry Andric UNW_MIPS_R26 = 26, 8420b57cec5SDimitry Andric UNW_MIPS_R27 = 27, 8430b57cec5SDimitry Andric UNW_MIPS_R28 = 28, 8440b57cec5SDimitry Andric UNW_MIPS_R29 = 29, 8450b57cec5SDimitry Andric UNW_MIPS_R30 = 30, 8460b57cec5SDimitry Andric UNW_MIPS_R31 = 31, 8470b57cec5SDimitry Andric UNW_MIPS_F0 = 32, 8480b57cec5SDimitry Andric UNW_MIPS_F1 = 33, 8490b57cec5SDimitry Andric UNW_MIPS_F2 = 34, 8500b57cec5SDimitry Andric UNW_MIPS_F3 = 35, 8510b57cec5SDimitry Andric UNW_MIPS_F4 = 36, 8520b57cec5SDimitry Andric UNW_MIPS_F5 = 37, 8530b57cec5SDimitry Andric UNW_MIPS_F6 = 38, 8540b57cec5SDimitry Andric UNW_MIPS_F7 = 39, 8550b57cec5SDimitry Andric UNW_MIPS_F8 = 40, 8560b57cec5SDimitry Andric UNW_MIPS_F9 = 41, 8570b57cec5SDimitry Andric UNW_MIPS_F10 = 42, 8580b57cec5SDimitry Andric UNW_MIPS_F11 = 43, 8590b57cec5SDimitry Andric UNW_MIPS_F12 = 44, 8600b57cec5SDimitry Andric UNW_MIPS_F13 = 45, 8610b57cec5SDimitry Andric UNW_MIPS_F14 = 46, 8620b57cec5SDimitry Andric UNW_MIPS_F15 = 47, 8630b57cec5SDimitry Andric UNW_MIPS_F16 = 48, 8640b57cec5SDimitry Andric UNW_MIPS_F17 = 49, 8650b57cec5SDimitry Andric UNW_MIPS_F18 = 50, 8660b57cec5SDimitry Andric UNW_MIPS_F19 = 51, 8670b57cec5SDimitry Andric UNW_MIPS_F20 = 52, 8680b57cec5SDimitry Andric UNW_MIPS_F21 = 53, 8690b57cec5SDimitry Andric UNW_MIPS_F22 = 54, 8700b57cec5SDimitry Andric UNW_MIPS_F23 = 55, 8710b57cec5SDimitry Andric UNW_MIPS_F24 = 56, 8720b57cec5SDimitry Andric UNW_MIPS_F25 = 57, 8730b57cec5SDimitry Andric UNW_MIPS_F26 = 58, 8740b57cec5SDimitry Andric UNW_MIPS_F27 = 59, 8750b57cec5SDimitry Andric UNW_MIPS_F28 = 60, 8760b57cec5SDimitry Andric UNW_MIPS_F29 = 61, 8770b57cec5SDimitry Andric UNW_MIPS_F30 = 62, 8780b57cec5SDimitry Andric UNW_MIPS_F31 = 63, 879*5f757f3fSDimitry Andric // HI,LO have been dropped since r6, we keep them here. 880*5f757f3fSDimitry Andric // So, when we add DSP/MSA etc, we can use the same register indexes 881*5f757f3fSDimitry Andric // for r6 and pre-r6. 8820b57cec5SDimitry Andric UNW_MIPS_HI = 64, 8830b57cec5SDimitry Andric UNW_MIPS_LO = 65, 8840b57cec5SDimitry Andric }; 8850b57cec5SDimitry Andric 8860b57cec5SDimitry Andric // SPARC registers 8870b57cec5SDimitry Andric enum { 8880b57cec5SDimitry Andric UNW_SPARC_G0 = 0, 8890b57cec5SDimitry Andric UNW_SPARC_G1 = 1, 8900b57cec5SDimitry Andric UNW_SPARC_G2 = 2, 8910b57cec5SDimitry Andric UNW_SPARC_G3 = 3, 8920b57cec5SDimitry Andric UNW_SPARC_G4 = 4, 8930b57cec5SDimitry Andric UNW_SPARC_G5 = 5, 8940b57cec5SDimitry Andric UNW_SPARC_G6 = 6, 8950b57cec5SDimitry Andric UNW_SPARC_G7 = 7, 8960b57cec5SDimitry Andric UNW_SPARC_O0 = 8, 8970b57cec5SDimitry Andric UNW_SPARC_O1 = 9, 8980b57cec5SDimitry Andric UNW_SPARC_O2 = 10, 8990b57cec5SDimitry Andric UNW_SPARC_O3 = 11, 9000b57cec5SDimitry Andric UNW_SPARC_O4 = 12, 9010b57cec5SDimitry Andric UNW_SPARC_O5 = 13, 9020b57cec5SDimitry Andric UNW_SPARC_O6 = 14, 9030b57cec5SDimitry Andric UNW_SPARC_O7 = 15, 9040b57cec5SDimitry Andric UNW_SPARC_L0 = 16, 9050b57cec5SDimitry Andric UNW_SPARC_L1 = 17, 9060b57cec5SDimitry Andric UNW_SPARC_L2 = 18, 9070b57cec5SDimitry Andric UNW_SPARC_L3 = 19, 9080b57cec5SDimitry Andric UNW_SPARC_L4 = 20, 9090b57cec5SDimitry Andric UNW_SPARC_L5 = 21, 9100b57cec5SDimitry Andric UNW_SPARC_L6 = 22, 9110b57cec5SDimitry Andric UNW_SPARC_L7 = 23, 9120b57cec5SDimitry Andric UNW_SPARC_I0 = 24, 9130b57cec5SDimitry Andric UNW_SPARC_I1 = 25, 9140b57cec5SDimitry Andric UNW_SPARC_I2 = 26, 9150b57cec5SDimitry Andric UNW_SPARC_I3 = 27, 9160b57cec5SDimitry Andric UNW_SPARC_I4 = 28, 9170b57cec5SDimitry Andric UNW_SPARC_I5 = 29, 9180b57cec5SDimitry Andric UNW_SPARC_I6 = 30, 9190b57cec5SDimitry Andric UNW_SPARC_I7 = 31, 9200b57cec5SDimitry Andric }; 9210b57cec5SDimitry Andric 9225ffd83dbSDimitry Andric // Hexagon register numbers 9235ffd83dbSDimitry Andric enum { 9245ffd83dbSDimitry Andric UNW_HEXAGON_R0, 9255ffd83dbSDimitry Andric UNW_HEXAGON_R1, 9265ffd83dbSDimitry Andric UNW_HEXAGON_R2, 9275ffd83dbSDimitry Andric UNW_HEXAGON_R3, 9285ffd83dbSDimitry Andric UNW_HEXAGON_R4, 9295ffd83dbSDimitry Andric UNW_HEXAGON_R5, 9305ffd83dbSDimitry Andric UNW_HEXAGON_R6, 9315ffd83dbSDimitry Andric UNW_HEXAGON_R7, 9325ffd83dbSDimitry Andric UNW_HEXAGON_R8, 9335ffd83dbSDimitry Andric UNW_HEXAGON_R9, 9345ffd83dbSDimitry Andric UNW_HEXAGON_R10, 9355ffd83dbSDimitry Andric UNW_HEXAGON_R11, 9365ffd83dbSDimitry Andric UNW_HEXAGON_R12, 9375ffd83dbSDimitry Andric UNW_HEXAGON_R13, 9385ffd83dbSDimitry Andric UNW_HEXAGON_R14, 9395ffd83dbSDimitry Andric UNW_HEXAGON_R15, 9405ffd83dbSDimitry Andric UNW_HEXAGON_R16, 9415ffd83dbSDimitry Andric UNW_HEXAGON_R17, 9425ffd83dbSDimitry Andric UNW_HEXAGON_R18, 9435ffd83dbSDimitry Andric UNW_HEXAGON_R19, 9445ffd83dbSDimitry Andric UNW_HEXAGON_R20, 9455ffd83dbSDimitry Andric UNW_HEXAGON_R21, 9465ffd83dbSDimitry Andric UNW_HEXAGON_R22, 9475ffd83dbSDimitry Andric UNW_HEXAGON_R23, 9485ffd83dbSDimitry Andric UNW_HEXAGON_R24, 9495ffd83dbSDimitry Andric UNW_HEXAGON_R25, 9505ffd83dbSDimitry Andric UNW_HEXAGON_R26, 9515ffd83dbSDimitry Andric UNW_HEXAGON_R27, 9525ffd83dbSDimitry Andric UNW_HEXAGON_R28, 9535ffd83dbSDimitry Andric UNW_HEXAGON_R29, 9545ffd83dbSDimitry Andric UNW_HEXAGON_R30, 9555ffd83dbSDimitry Andric UNW_HEXAGON_R31, 9565ffd83dbSDimitry Andric UNW_HEXAGON_P3_0, 9575ffd83dbSDimitry Andric UNW_HEXAGON_PC, 9585ffd83dbSDimitry Andric }; 9595ffd83dbSDimitry Andric 960480093f4SDimitry Andric // RISC-V registers. These match the DWARF register numbers defined by section 961480093f4SDimitry Andric // 4 of the RISC-V ELF psABI specification, which can be found at: 962480093f4SDimitry Andric // 963480093f4SDimitry Andric // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md 964480093f4SDimitry Andric enum { 965480093f4SDimitry Andric UNW_RISCV_X0 = 0, 966480093f4SDimitry Andric UNW_RISCV_X1 = 1, 967480093f4SDimitry Andric UNW_RISCV_X2 = 2, 968480093f4SDimitry Andric UNW_RISCV_X3 = 3, 969480093f4SDimitry Andric UNW_RISCV_X4 = 4, 970480093f4SDimitry Andric UNW_RISCV_X5 = 5, 971480093f4SDimitry Andric UNW_RISCV_X6 = 6, 972480093f4SDimitry Andric UNW_RISCV_X7 = 7, 973480093f4SDimitry Andric UNW_RISCV_X8 = 8, 974480093f4SDimitry Andric UNW_RISCV_X9 = 9, 975480093f4SDimitry Andric UNW_RISCV_X10 = 10, 976480093f4SDimitry Andric UNW_RISCV_X11 = 11, 977480093f4SDimitry Andric UNW_RISCV_X12 = 12, 978480093f4SDimitry Andric UNW_RISCV_X13 = 13, 979480093f4SDimitry Andric UNW_RISCV_X14 = 14, 980480093f4SDimitry Andric UNW_RISCV_X15 = 15, 981480093f4SDimitry Andric UNW_RISCV_X16 = 16, 982480093f4SDimitry Andric UNW_RISCV_X17 = 17, 983480093f4SDimitry Andric UNW_RISCV_X18 = 18, 984480093f4SDimitry Andric UNW_RISCV_X19 = 19, 985480093f4SDimitry Andric UNW_RISCV_X20 = 20, 986480093f4SDimitry Andric UNW_RISCV_X21 = 21, 987480093f4SDimitry Andric UNW_RISCV_X22 = 22, 988480093f4SDimitry Andric UNW_RISCV_X23 = 23, 989480093f4SDimitry Andric UNW_RISCV_X24 = 24, 990480093f4SDimitry Andric UNW_RISCV_X25 = 25, 991480093f4SDimitry Andric UNW_RISCV_X26 = 26, 992480093f4SDimitry Andric UNW_RISCV_X27 = 27, 993480093f4SDimitry Andric UNW_RISCV_X28 = 28, 994480093f4SDimitry Andric UNW_RISCV_X29 = 29, 995480093f4SDimitry Andric UNW_RISCV_X30 = 30, 996480093f4SDimitry Andric UNW_RISCV_X31 = 31, 997480093f4SDimitry Andric UNW_RISCV_F0 = 32, 998480093f4SDimitry Andric UNW_RISCV_F1 = 33, 999480093f4SDimitry Andric UNW_RISCV_F2 = 34, 1000480093f4SDimitry Andric UNW_RISCV_F3 = 35, 1001480093f4SDimitry Andric UNW_RISCV_F4 = 36, 1002480093f4SDimitry Andric UNW_RISCV_F5 = 37, 1003480093f4SDimitry Andric UNW_RISCV_F6 = 38, 1004480093f4SDimitry Andric UNW_RISCV_F7 = 39, 1005480093f4SDimitry Andric UNW_RISCV_F8 = 40, 1006480093f4SDimitry Andric UNW_RISCV_F9 = 41, 1007480093f4SDimitry Andric UNW_RISCV_F10 = 42, 1008480093f4SDimitry Andric UNW_RISCV_F11 = 43, 1009480093f4SDimitry Andric UNW_RISCV_F12 = 44, 1010480093f4SDimitry Andric UNW_RISCV_F13 = 45, 1011480093f4SDimitry Andric UNW_RISCV_F14 = 46, 1012480093f4SDimitry Andric UNW_RISCV_F15 = 47, 1013480093f4SDimitry Andric UNW_RISCV_F16 = 48, 1014480093f4SDimitry Andric UNW_RISCV_F17 = 49, 1015480093f4SDimitry Andric UNW_RISCV_F18 = 50, 1016480093f4SDimitry Andric UNW_RISCV_F19 = 51, 1017480093f4SDimitry Andric UNW_RISCV_F20 = 52, 1018480093f4SDimitry Andric UNW_RISCV_F21 = 53, 1019480093f4SDimitry Andric UNW_RISCV_F22 = 54, 1020480093f4SDimitry Andric UNW_RISCV_F23 = 55, 1021480093f4SDimitry Andric UNW_RISCV_F24 = 56, 1022480093f4SDimitry Andric UNW_RISCV_F25 = 57, 1023480093f4SDimitry Andric UNW_RISCV_F26 = 58, 1024480093f4SDimitry Andric UNW_RISCV_F27 = 59, 1025480093f4SDimitry Andric UNW_RISCV_F28 = 60, 1026480093f4SDimitry Andric UNW_RISCV_F29 = 61, 1027480093f4SDimitry Andric UNW_RISCV_F30 = 62, 1028480093f4SDimitry Andric UNW_RISCV_F31 = 63, 1029bdd1243dSDimitry Andric // 65-95 -- Reserved for future standard extensions 1030bdd1243dSDimitry Andric // 96-127 -- v0-v31 (Vector registers) 1031bdd1243dSDimitry Andric // 128-3071 -- Reserved for future standard extensions 1032bdd1243dSDimitry Andric // 3072-4095 -- Reserved for custom extensions 1033bdd1243dSDimitry Andric // 4096-8191 -- CSRs 1034bdd1243dSDimitry Andric // 1035bdd1243dSDimitry Andric // VLENB CSR number: 0xC22 -- defined by section 3 of v-spec: 1036bdd1243dSDimitry Andric // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model 1037bdd1243dSDimitry Andric // VLENB DWARF number: 0x1000 + 0xC22 1038bdd1243dSDimitry Andric UNW_RISCV_VLENB = 0x1C22, 1039480093f4SDimitry Andric }; 1040480093f4SDimitry Andric 1041e8d8bef9SDimitry Andric // VE register numbers 1042e8d8bef9SDimitry Andric enum { 1043e8d8bef9SDimitry Andric UNW_VE_S0 = 0, 1044e8d8bef9SDimitry Andric UNW_VE_S1 = 1, 1045e8d8bef9SDimitry Andric UNW_VE_S2 = 2, 1046e8d8bef9SDimitry Andric UNW_VE_S3 = 3, 1047e8d8bef9SDimitry Andric UNW_VE_S4 = 4, 1048e8d8bef9SDimitry Andric UNW_VE_S5 = 5, 1049e8d8bef9SDimitry Andric UNW_VE_S6 = 6, 1050e8d8bef9SDimitry Andric UNW_VE_S7 = 7, 1051e8d8bef9SDimitry Andric UNW_VE_S8 = 8, 1052e8d8bef9SDimitry Andric UNW_VE_S9 = 9, 1053e8d8bef9SDimitry Andric UNW_VE_S10 = 10, 1054e8d8bef9SDimitry Andric UNW_VE_S11 = 11, 1055e8d8bef9SDimitry Andric UNW_VE_S12 = 12, 1056e8d8bef9SDimitry Andric UNW_VE_S13 = 13, 1057e8d8bef9SDimitry Andric UNW_VE_S14 = 14, 1058e8d8bef9SDimitry Andric UNW_VE_S15 = 15, 1059e8d8bef9SDimitry Andric UNW_VE_S16 = 16, 1060e8d8bef9SDimitry Andric UNW_VE_S17 = 17, 1061e8d8bef9SDimitry Andric UNW_VE_S18 = 18, 1062e8d8bef9SDimitry Andric UNW_VE_S19 = 19, 1063e8d8bef9SDimitry Andric UNW_VE_S20 = 20, 1064e8d8bef9SDimitry Andric UNW_VE_S21 = 21, 1065e8d8bef9SDimitry Andric UNW_VE_S22 = 22, 1066e8d8bef9SDimitry Andric UNW_VE_S23 = 23, 1067e8d8bef9SDimitry Andric UNW_VE_S24 = 24, 1068e8d8bef9SDimitry Andric UNW_VE_S25 = 25, 1069e8d8bef9SDimitry Andric UNW_VE_S26 = 26, 1070e8d8bef9SDimitry Andric UNW_VE_S27 = 27, 1071e8d8bef9SDimitry Andric UNW_VE_S28 = 28, 1072e8d8bef9SDimitry Andric UNW_VE_S29 = 29, 1073e8d8bef9SDimitry Andric UNW_VE_S30 = 30, 1074e8d8bef9SDimitry Andric UNW_VE_S31 = 31, 1075e8d8bef9SDimitry Andric UNW_VE_S32 = 32, 1076e8d8bef9SDimitry Andric UNW_VE_S33 = 33, 1077e8d8bef9SDimitry Andric UNW_VE_S34 = 34, 1078e8d8bef9SDimitry Andric UNW_VE_S35 = 35, 1079e8d8bef9SDimitry Andric UNW_VE_S36 = 36, 1080e8d8bef9SDimitry Andric UNW_VE_S37 = 37, 1081e8d8bef9SDimitry Andric UNW_VE_S38 = 38, 1082e8d8bef9SDimitry Andric UNW_VE_S39 = 39, 1083e8d8bef9SDimitry Andric UNW_VE_S40 = 40, 1084e8d8bef9SDimitry Andric UNW_VE_S41 = 41, 1085e8d8bef9SDimitry Andric UNW_VE_S42 = 42, 1086e8d8bef9SDimitry Andric UNW_VE_S43 = 43, 1087e8d8bef9SDimitry Andric UNW_VE_S44 = 44, 1088e8d8bef9SDimitry Andric UNW_VE_S45 = 45, 1089e8d8bef9SDimitry Andric UNW_VE_S46 = 46, 1090e8d8bef9SDimitry Andric UNW_VE_S47 = 47, 1091e8d8bef9SDimitry Andric UNW_VE_S48 = 48, 1092e8d8bef9SDimitry Andric UNW_VE_S49 = 49, 1093e8d8bef9SDimitry Andric UNW_VE_S50 = 50, 1094e8d8bef9SDimitry Andric UNW_VE_S51 = 51, 1095e8d8bef9SDimitry Andric UNW_VE_S52 = 52, 1096e8d8bef9SDimitry Andric UNW_VE_S53 = 53, 1097e8d8bef9SDimitry Andric UNW_VE_S54 = 54, 1098e8d8bef9SDimitry Andric UNW_VE_S55 = 55, 1099e8d8bef9SDimitry Andric UNW_VE_S56 = 56, 1100e8d8bef9SDimitry Andric UNW_VE_S57 = 57, 1101e8d8bef9SDimitry Andric UNW_VE_S58 = 58, 1102e8d8bef9SDimitry Andric UNW_VE_S59 = 59, 1103e8d8bef9SDimitry Andric UNW_VE_S60 = 60, 1104e8d8bef9SDimitry Andric UNW_VE_S61 = 61, 1105e8d8bef9SDimitry Andric UNW_VE_S62 = 62, 1106e8d8bef9SDimitry Andric UNW_VE_S63 = 63, 1107e8d8bef9SDimitry Andric UNW_VE_V0 = 64 + 0, 1108e8d8bef9SDimitry Andric UNW_VE_V1 = 64 + 1, 1109e8d8bef9SDimitry Andric UNW_VE_V2 = 64 + 2, 1110e8d8bef9SDimitry Andric UNW_VE_V3 = 64 + 3, 1111e8d8bef9SDimitry Andric UNW_VE_V4 = 64 + 4, 1112e8d8bef9SDimitry Andric UNW_VE_V5 = 64 + 5, 1113e8d8bef9SDimitry Andric UNW_VE_V6 = 64 + 6, 1114e8d8bef9SDimitry Andric UNW_VE_V7 = 64 + 7, 1115e8d8bef9SDimitry Andric UNW_VE_V8 = 64 + 8, 1116e8d8bef9SDimitry Andric UNW_VE_V9 = 64 + 9, 1117e8d8bef9SDimitry Andric UNW_VE_V10 = 64 + 10, 1118e8d8bef9SDimitry Andric UNW_VE_V11 = 64 + 11, 1119e8d8bef9SDimitry Andric UNW_VE_V12 = 64 + 12, 1120e8d8bef9SDimitry Andric UNW_VE_V13 = 64 + 13, 1121e8d8bef9SDimitry Andric UNW_VE_V14 = 64 + 14, 1122e8d8bef9SDimitry Andric UNW_VE_V15 = 64 + 15, 1123e8d8bef9SDimitry Andric UNW_VE_V16 = 64 + 16, 1124e8d8bef9SDimitry Andric UNW_VE_V17 = 64 + 17, 1125e8d8bef9SDimitry Andric UNW_VE_V18 = 64 + 18, 1126e8d8bef9SDimitry Andric UNW_VE_V19 = 64 + 19, 1127e8d8bef9SDimitry Andric UNW_VE_V20 = 64 + 20, 1128e8d8bef9SDimitry Andric UNW_VE_V21 = 64 + 21, 1129e8d8bef9SDimitry Andric UNW_VE_V22 = 64 + 22, 1130e8d8bef9SDimitry Andric UNW_VE_V23 = 64 + 23, 1131e8d8bef9SDimitry Andric UNW_VE_V24 = 64 + 24, 1132e8d8bef9SDimitry Andric UNW_VE_V25 = 64 + 25, 1133e8d8bef9SDimitry Andric UNW_VE_V26 = 64 + 26, 1134e8d8bef9SDimitry Andric UNW_VE_V27 = 64 + 27, 1135e8d8bef9SDimitry Andric UNW_VE_V28 = 64 + 28, 1136e8d8bef9SDimitry Andric UNW_VE_V29 = 64 + 29, 1137e8d8bef9SDimitry Andric UNW_VE_V30 = 64 + 30, 1138e8d8bef9SDimitry Andric UNW_VE_V31 = 64 + 31, 1139e8d8bef9SDimitry Andric UNW_VE_V32 = 64 + 32, 1140e8d8bef9SDimitry Andric UNW_VE_V33 = 64 + 33, 1141e8d8bef9SDimitry Andric UNW_VE_V34 = 64 + 34, 1142e8d8bef9SDimitry Andric UNW_VE_V35 = 64 + 35, 1143e8d8bef9SDimitry Andric UNW_VE_V36 = 64 + 36, 1144e8d8bef9SDimitry Andric UNW_VE_V37 = 64 + 37, 1145e8d8bef9SDimitry Andric UNW_VE_V38 = 64 + 38, 1146e8d8bef9SDimitry Andric UNW_VE_V39 = 64 + 39, 1147e8d8bef9SDimitry Andric UNW_VE_V40 = 64 + 40, 1148e8d8bef9SDimitry Andric UNW_VE_V41 = 64 + 41, 1149e8d8bef9SDimitry Andric UNW_VE_V42 = 64 + 42, 1150e8d8bef9SDimitry Andric UNW_VE_V43 = 64 + 43, 1151e8d8bef9SDimitry Andric UNW_VE_V44 = 64 + 44, 1152e8d8bef9SDimitry Andric UNW_VE_V45 = 64 + 45, 1153e8d8bef9SDimitry Andric UNW_VE_V46 = 64 + 46, 1154e8d8bef9SDimitry Andric UNW_VE_V47 = 64 + 47, 1155e8d8bef9SDimitry Andric UNW_VE_V48 = 64 + 48, 1156e8d8bef9SDimitry Andric UNW_VE_V49 = 64 + 49, 1157e8d8bef9SDimitry Andric UNW_VE_V50 = 64 + 50, 1158e8d8bef9SDimitry Andric UNW_VE_V51 = 64 + 51, 1159e8d8bef9SDimitry Andric UNW_VE_V52 = 64 + 52, 1160e8d8bef9SDimitry Andric UNW_VE_V53 = 64 + 53, 1161e8d8bef9SDimitry Andric UNW_VE_V54 = 64 + 54, 1162e8d8bef9SDimitry Andric UNW_VE_V55 = 64 + 55, 1163e8d8bef9SDimitry Andric UNW_VE_V56 = 64 + 56, 1164e8d8bef9SDimitry Andric UNW_VE_V57 = 64 + 57, 1165e8d8bef9SDimitry Andric UNW_VE_V58 = 64 + 58, 1166e8d8bef9SDimitry Andric UNW_VE_V59 = 64 + 59, 1167e8d8bef9SDimitry Andric UNW_VE_V60 = 64 + 60, 1168e8d8bef9SDimitry Andric UNW_VE_V61 = 64 + 61, 1169e8d8bef9SDimitry Andric UNW_VE_V62 = 64 + 62, 1170e8d8bef9SDimitry Andric UNW_VE_V63 = 64 + 63, 1171e8d8bef9SDimitry Andric UNW_VE_VM0 = 128 + 0, 1172e8d8bef9SDimitry Andric UNW_VE_VM1 = 128 + 1, 1173e8d8bef9SDimitry Andric UNW_VE_VM2 = 128 + 2, 1174e8d8bef9SDimitry Andric UNW_VE_VM3 = 128 + 3, 1175e8d8bef9SDimitry Andric UNW_VE_VM4 = 128 + 4, 1176e8d8bef9SDimitry Andric UNW_VE_VM5 = 128 + 5, 1177e8d8bef9SDimitry Andric UNW_VE_VM6 = 128 + 6, 1178e8d8bef9SDimitry Andric UNW_VE_VM7 = 128 + 7, 1179e8d8bef9SDimitry Andric UNW_VE_VM8 = 128 + 8, 1180e8d8bef9SDimitry Andric UNW_VE_VM9 = 128 + 9, 1181e8d8bef9SDimitry Andric UNW_VE_VM10 = 128 + 10, 1182e8d8bef9SDimitry Andric UNW_VE_VM11 = 128 + 11, 1183e8d8bef9SDimitry Andric UNW_VE_VM12 = 128 + 12, 1184e8d8bef9SDimitry Andric UNW_VE_VM13 = 128 + 13, 1185e8d8bef9SDimitry Andric UNW_VE_VM14 = 128 + 14, 1186e8d8bef9SDimitry Andric UNW_VE_VM15 = 128 + 15, // = 143 1187e8d8bef9SDimitry Andric 1188e8d8bef9SDimitry Andric // Following registers don't have DWARF register numbers. 1189e8d8bef9SDimitry Andric UNW_VE_VIXR = 144, 1190e8d8bef9SDimitry Andric UNW_VE_VL = 145, 1191e8d8bef9SDimitry Andric }; 1192e8d8bef9SDimitry Andric 119381ad6265SDimitry Andric // s390x register numbers 119481ad6265SDimitry Andric enum { 119581ad6265SDimitry Andric UNW_S390X_R0 = 0, 119681ad6265SDimitry Andric UNW_S390X_R1 = 1, 119781ad6265SDimitry Andric UNW_S390X_R2 = 2, 119881ad6265SDimitry Andric UNW_S390X_R3 = 3, 119981ad6265SDimitry Andric UNW_S390X_R4 = 4, 120081ad6265SDimitry Andric UNW_S390X_R5 = 5, 120181ad6265SDimitry Andric UNW_S390X_R6 = 6, 120281ad6265SDimitry Andric UNW_S390X_R7 = 7, 120381ad6265SDimitry Andric UNW_S390X_R8 = 8, 120481ad6265SDimitry Andric UNW_S390X_R9 = 9, 120581ad6265SDimitry Andric UNW_S390X_R10 = 10, 120681ad6265SDimitry Andric UNW_S390X_R11 = 11, 120781ad6265SDimitry Andric UNW_S390X_R12 = 12, 120881ad6265SDimitry Andric UNW_S390X_R13 = 13, 120981ad6265SDimitry Andric UNW_S390X_R14 = 14, 121081ad6265SDimitry Andric UNW_S390X_R15 = 15, 121181ad6265SDimitry Andric UNW_S390X_F0 = 16, 121281ad6265SDimitry Andric UNW_S390X_F2 = 17, 121381ad6265SDimitry Andric UNW_S390X_F4 = 18, 121481ad6265SDimitry Andric UNW_S390X_F6 = 19, 121581ad6265SDimitry Andric UNW_S390X_F1 = 20, 121681ad6265SDimitry Andric UNW_S390X_F3 = 21, 121781ad6265SDimitry Andric UNW_S390X_F5 = 22, 121881ad6265SDimitry Andric UNW_S390X_F7 = 23, 121981ad6265SDimitry Andric UNW_S390X_F8 = 24, 122081ad6265SDimitry Andric UNW_S390X_F10 = 25, 122181ad6265SDimitry Andric UNW_S390X_F12 = 26, 122281ad6265SDimitry Andric UNW_S390X_F14 = 27, 122381ad6265SDimitry Andric UNW_S390X_F9 = 28, 122481ad6265SDimitry Andric UNW_S390X_F11 = 29, 122581ad6265SDimitry Andric UNW_S390X_F13 = 30, 122681ad6265SDimitry Andric UNW_S390X_F15 = 31, 122781ad6265SDimitry Andric // 32-47 Control Registers 122881ad6265SDimitry Andric // 48-63 Access Registers 122981ad6265SDimitry Andric UNW_S390X_PSWM = 64, 123081ad6265SDimitry Andric UNW_S390X_PSWA = 65, 123181ad6265SDimitry Andric // 66-67 Reserved 123281ad6265SDimitry Andric // 68-83 Vector Registers %v16-%v31 123381ad6265SDimitry Andric }; 123481ad6265SDimitry Andric 1235bdd1243dSDimitry Andric // LoongArch registers. 1236bdd1243dSDimitry Andric enum { 1237bdd1243dSDimitry Andric UNW_LOONGARCH_R0 = 0, 1238bdd1243dSDimitry Andric UNW_LOONGARCH_R1 = 1, 1239bdd1243dSDimitry Andric UNW_LOONGARCH_R2 = 2, 1240bdd1243dSDimitry Andric UNW_LOONGARCH_R3 = 3, 1241bdd1243dSDimitry Andric UNW_LOONGARCH_R4 = 4, 1242bdd1243dSDimitry Andric UNW_LOONGARCH_R5 = 5, 1243bdd1243dSDimitry Andric UNW_LOONGARCH_R6 = 6, 1244bdd1243dSDimitry Andric UNW_LOONGARCH_R7 = 7, 1245bdd1243dSDimitry Andric UNW_LOONGARCH_R8 = 8, 1246bdd1243dSDimitry Andric UNW_LOONGARCH_R9 = 9, 1247bdd1243dSDimitry Andric UNW_LOONGARCH_R10 = 10, 1248bdd1243dSDimitry Andric UNW_LOONGARCH_R11 = 11, 1249bdd1243dSDimitry Andric UNW_LOONGARCH_R12 = 12, 1250bdd1243dSDimitry Andric UNW_LOONGARCH_R13 = 13, 1251bdd1243dSDimitry Andric UNW_LOONGARCH_R14 = 14, 1252bdd1243dSDimitry Andric UNW_LOONGARCH_R15 = 15, 1253bdd1243dSDimitry Andric UNW_LOONGARCH_R16 = 16, 1254bdd1243dSDimitry Andric UNW_LOONGARCH_R17 = 17, 1255bdd1243dSDimitry Andric UNW_LOONGARCH_R18 = 18, 1256bdd1243dSDimitry Andric UNW_LOONGARCH_R19 = 19, 1257bdd1243dSDimitry Andric UNW_LOONGARCH_R20 = 20, 1258bdd1243dSDimitry Andric UNW_LOONGARCH_R21 = 21, 1259bdd1243dSDimitry Andric UNW_LOONGARCH_R22 = 22, 1260bdd1243dSDimitry Andric UNW_LOONGARCH_R23 = 23, 1261bdd1243dSDimitry Andric UNW_LOONGARCH_R24 = 24, 1262bdd1243dSDimitry Andric UNW_LOONGARCH_R25 = 25, 1263bdd1243dSDimitry Andric UNW_LOONGARCH_R26 = 26, 1264bdd1243dSDimitry Andric UNW_LOONGARCH_R27 = 27, 1265bdd1243dSDimitry Andric UNW_LOONGARCH_R28 = 28, 1266bdd1243dSDimitry Andric UNW_LOONGARCH_R29 = 29, 1267bdd1243dSDimitry Andric UNW_LOONGARCH_R30 = 30, 1268bdd1243dSDimitry Andric UNW_LOONGARCH_R31 = 31, 1269bdd1243dSDimitry Andric UNW_LOONGARCH_F0 = 32, 1270bdd1243dSDimitry Andric UNW_LOONGARCH_F1 = 33, 1271bdd1243dSDimitry Andric UNW_LOONGARCH_F2 = 34, 1272bdd1243dSDimitry Andric UNW_LOONGARCH_F3 = 35, 1273bdd1243dSDimitry Andric UNW_LOONGARCH_F4 = 36, 1274bdd1243dSDimitry Andric UNW_LOONGARCH_F5 = 37, 1275bdd1243dSDimitry Andric UNW_LOONGARCH_F6 = 38, 1276bdd1243dSDimitry Andric UNW_LOONGARCH_F7 = 39, 1277bdd1243dSDimitry Andric UNW_LOONGARCH_F8 = 40, 1278bdd1243dSDimitry Andric UNW_LOONGARCH_F9 = 41, 1279bdd1243dSDimitry Andric UNW_LOONGARCH_F10 = 42, 1280bdd1243dSDimitry Andric UNW_LOONGARCH_F11 = 43, 1281bdd1243dSDimitry Andric UNW_LOONGARCH_F12 = 44, 1282bdd1243dSDimitry Andric UNW_LOONGARCH_F13 = 45, 1283bdd1243dSDimitry Andric UNW_LOONGARCH_F14 = 46, 1284bdd1243dSDimitry Andric UNW_LOONGARCH_F15 = 47, 1285bdd1243dSDimitry Andric UNW_LOONGARCH_F16 = 48, 1286bdd1243dSDimitry Andric UNW_LOONGARCH_F17 = 49, 1287bdd1243dSDimitry Andric UNW_LOONGARCH_F18 = 50, 1288bdd1243dSDimitry Andric UNW_LOONGARCH_F19 = 51, 1289bdd1243dSDimitry Andric UNW_LOONGARCH_F20 = 52, 1290bdd1243dSDimitry Andric UNW_LOONGARCH_F21 = 53, 1291bdd1243dSDimitry Andric UNW_LOONGARCH_F22 = 54, 1292bdd1243dSDimitry Andric UNW_LOONGARCH_F23 = 55, 1293bdd1243dSDimitry Andric UNW_LOONGARCH_F24 = 56, 1294bdd1243dSDimitry Andric UNW_LOONGARCH_F25 = 57, 1295bdd1243dSDimitry Andric UNW_LOONGARCH_F26 = 58, 1296bdd1243dSDimitry Andric UNW_LOONGARCH_F27 = 59, 1297bdd1243dSDimitry Andric UNW_LOONGARCH_F28 = 60, 1298bdd1243dSDimitry Andric UNW_LOONGARCH_F29 = 61, 1299bdd1243dSDimitry Andric UNW_LOONGARCH_F30 = 62, 1300bdd1243dSDimitry Andric UNW_LOONGARCH_F31 = 63, 1301bdd1243dSDimitry Andric }; 1302bdd1243dSDimitry Andric 13030b57cec5SDimitry Andric #endif 1304