1*753f127fSDimitry Andric//===-- elfnix_tlv.aarch64.s ---------------------------------------*- ASM -*-===// 2*753f127fSDimitry Andric// 3*753f127fSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*753f127fSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*753f127fSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*753f127fSDimitry Andric// 7*753f127fSDimitry Andric//===----------------------------------------------------------------------===// 8*753f127fSDimitry Andric// 9*753f127fSDimitry Andric// This file is a part of the ORC runtime support library. 10*753f127fSDimitry Andric// 11*753f127fSDimitry Andric//===----------------------------------------------------------------------===// 12*753f127fSDimitry Andric 13*753f127fSDimitry Andric// The content of this file is aarch64-only 14*753f127fSDimitry Andric#if defined(__arm64__) || defined(__aarch64__) 15*753f127fSDimitry Andric 16*753f127fSDimitry Andric#define REGISTER_SAVE_SPACE_SIZE 32 * 24 17*753f127fSDimitry Andric 18*753f127fSDimitry Andric .text 19*753f127fSDimitry Andric 20*753f127fSDimitry Andric // returns address of TLV in x0, all other registers preserved 21*753f127fSDimitry Andric // TODO: add fast-path for repeat access 22*753f127fSDimitry Andric .globl ___orc_rt_elfnix_tlsdesc_resolver 23*753f127fSDimitry Andric___orc_rt_elfnix_tlsdesc_resolver: 24*753f127fSDimitry Andric sub sp, sp, #REGISTER_SAVE_SPACE_SIZE 25*753f127fSDimitry Andric stp x29, x30, [sp, #16 * 1] 26*753f127fSDimitry Andric stp x27, x28, [sp, #16 * 2] 27*753f127fSDimitry Andric stp x25, x26, [sp, #16 * 3] 28*753f127fSDimitry Andric stp x23, x24, [sp, #16 * 4] 29*753f127fSDimitry Andric stp x21, x22, [sp, #16 * 5] 30*753f127fSDimitry Andric stp x19, x20, [sp, #16 * 6] 31*753f127fSDimitry Andric stp x17, x18, [sp, #16 * 7] 32*753f127fSDimitry Andric stp x15, x16, [sp, #16 * 8] 33*753f127fSDimitry Andric stp x13, x14, [sp, #16 * 9] 34*753f127fSDimitry Andric stp x11, x12, [sp, #16 * 10] 35*753f127fSDimitry Andric stp x9, x10, [sp, #16 * 11] 36*753f127fSDimitry Andric stp x7, x8, [sp, #16 * 12] 37*753f127fSDimitry Andric stp x5, x6, [sp, #16 * 13] 38*753f127fSDimitry Andric stp x3, x4, [sp, #16 * 14] 39*753f127fSDimitry Andric stp x1, x2, [sp, #16 * 15] 40*753f127fSDimitry Andric stp q30, q31, [sp, #32 * 8] 41*753f127fSDimitry Andric stp q28, q29, [sp, #32 * 9] 42*753f127fSDimitry Andric stp q26, q27, [sp, #32 * 10] 43*753f127fSDimitry Andric stp q24, q25, [sp, #32 * 11] 44*753f127fSDimitry Andric stp q22, q23, [sp, #32 * 12] 45*753f127fSDimitry Andric stp q20, q21, [sp, #32 * 13] 46*753f127fSDimitry Andric stp q18, q19, [sp, #32 * 14] 47*753f127fSDimitry Andric stp q16, q17, [sp, #32 * 15] 48*753f127fSDimitry Andric stp q14, q15, [sp, #32 * 16] 49*753f127fSDimitry Andric stp q12, q13, [sp, #32 * 17] 50*753f127fSDimitry Andric stp q10, q11, [sp, #32 * 18] 51*753f127fSDimitry Andric stp q8, q9, [sp, #32 * 19] 52*753f127fSDimitry Andric stp q6, q7, [sp, #32 * 20] 53*753f127fSDimitry Andric stp q4, q5, [sp, #32 * 21] 54*753f127fSDimitry Andric stp q2, q3, [sp, #32 * 22] 55*753f127fSDimitry Andric stp q0, q1, [sp, #32 * 23] 56*753f127fSDimitry Andric 57*753f127fSDimitry Andric mrs x1, TPIDR_EL0 // get thread pointer 58*753f127fSDimitry Andric bl ___orc_rt_elfnix_tlsdesc_resolver_impl 59*753f127fSDimitry Andric 60*753f127fSDimitry Andric ldp q0, q1, [sp, #32 * 23] 61*753f127fSDimitry Andric ldp q2, q3, [sp, #32 * 22] 62*753f127fSDimitry Andric ldp q4, q5, [sp, #32 * 21] 63*753f127fSDimitry Andric ldp q6, q7, [sp, #32 * 20] 64*753f127fSDimitry Andric ldp q8, q9, [sp, #32 * 19] 65*753f127fSDimitry Andric ldp q10, q11, [sp, #32 * 18] 66*753f127fSDimitry Andric ldp q12, q13, [sp, #32 * 17] 67*753f127fSDimitry Andric ldp q14, q15, [sp, #32 * 16] 68*753f127fSDimitry Andric ldp q16, q17, [sp, #32 * 15] 69*753f127fSDimitry Andric ldp q18, q19, [sp, #32 * 14] 70*753f127fSDimitry Andric ldp q20, q21, [sp, #32 * 13] 71*753f127fSDimitry Andric ldp q22, q23, [sp, #32 * 12] 72*753f127fSDimitry Andric ldp q24, q25, [sp, #32 * 11] 73*753f127fSDimitry Andric ldp q26, q27, [sp, #32 * 10] 74*753f127fSDimitry Andric ldp q28, q29, [sp, #32 * 9] 75*753f127fSDimitry Andric ldp q30, q31, [sp, #32 * 8] 76*753f127fSDimitry Andric ldp x1, x2, [sp, #16 * 15] 77*753f127fSDimitry Andric ldp x3, x4, [sp, #16 * 14] 78*753f127fSDimitry Andric ldp x5, x6, [sp, #16 * 13] 79*753f127fSDimitry Andric ldp x7, x8, [sp, #16 * 12] 80*753f127fSDimitry Andric ldp x9, x10, [sp, #16 * 11] 81*753f127fSDimitry Andric ldp x11, x12, [sp, #16 * 10] 82*753f127fSDimitry Andric ldp x13, x14, [sp, #16 * 9] 83*753f127fSDimitry Andric ldp x15, x16, [sp, #16 * 8] 84*753f127fSDimitry Andric ldp x17, x18, [sp, #16 * 7] 85*753f127fSDimitry Andric ldp x19, x20, [sp, #16 * 6] 86*753f127fSDimitry Andric ldp x21, x22, [sp, #16 * 5] 87*753f127fSDimitry Andric ldp x23, x24, [sp, #16 * 4] 88*753f127fSDimitry Andric ldp x25, x26, [sp, #16 * 3] 89*753f127fSDimitry Andric ldp x27, x28, [sp, #16 * 2] 90*753f127fSDimitry Andric ldp x29, x30, [sp, #16 * 1] 91*753f127fSDimitry Andric add sp, sp, #REGISTER_SAVE_SPACE_SIZE 92*753f127fSDimitry Andric ret 93*753f127fSDimitry Andric 94*753f127fSDimitry Andric#endif // defined(__arm64__) || defined(__aarch64__) 95