xref: /freebsd-src/contrib/llvm-project/compiler-rt/lib/builtins/riscv/save.S (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583)
1fe6060f1SDimitry Andric//===-- save.S - save up to 12 callee-saved registers ---------------------===//
2fe6060f1SDimitry Andric//
3fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
5fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6fe6060f1SDimitry Andric//
7fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
8fe6060f1SDimitry Andric//
9fe6060f1SDimitry Andric// Multiple entry points depending on number of registers to save
10fe6060f1SDimitry Andric//
11fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
12fe6060f1SDimitry Andric
13fe6060f1SDimitry Andric// The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
14fe6060f1SDimitry Andric// is the minimum grouping which will maintain the required 16-byte stack
15fe6060f1SDimitry Andric// alignment.
16fe6060f1SDimitry Andric
17fe6060f1SDimitry Andric  .text
18fe6060f1SDimitry Andric
19fe6060f1SDimitry Andric#if __riscv_xlen == 32
20fe6060f1SDimitry Andric
21*0fca6ea1SDimitry Andric#ifndef __riscv_abi_rve
22dfa39133SDimitry Andric
23fe6060f1SDimitry Andric  .globl  __riscv_save_12
24fe6060f1SDimitry Andric  .type   __riscv_save_12,@function
25fe6060f1SDimitry Andric__riscv_save_12:
26fe6060f1SDimitry Andric  addi   sp, sp, -64
27fe6060f1SDimitry Andric  mv     t1, zero
28fe6060f1SDimitry Andric  sw     s11, 12(sp)
29fe6060f1SDimitry Andric  j      .Lriscv_save_11_8
30fe6060f1SDimitry Andric
31fe6060f1SDimitry Andric  .globl  __riscv_save_11
32fe6060f1SDimitry Andric  .type   __riscv_save_11,@function
33fe6060f1SDimitry Andric  .globl  __riscv_save_10
34fe6060f1SDimitry Andric  .type   __riscv_save_10,@function
35fe6060f1SDimitry Andric  .globl  __riscv_save_9
36fe6060f1SDimitry Andric  .type   __riscv_save_9,@function
37fe6060f1SDimitry Andric  .globl  __riscv_save_8
38fe6060f1SDimitry Andric  .type   __riscv_save_8,@function
39fe6060f1SDimitry Andric__riscv_save_11:
40fe6060f1SDimitry Andric__riscv_save_10:
41fe6060f1SDimitry Andric__riscv_save_9:
42fe6060f1SDimitry Andric__riscv_save_8:
43fe6060f1SDimitry Andric  addi   sp, sp, -64
44fe6060f1SDimitry Andric  li     t1, 16
45fe6060f1SDimitry Andric.Lriscv_save_11_8:
46fe6060f1SDimitry Andric  sw     s10, 16(sp)
47fe6060f1SDimitry Andric  sw     s9,  20(sp)
48fe6060f1SDimitry Andric  sw     s8,  24(sp)
49fe6060f1SDimitry Andric  sw     s7,  28(sp)
50fe6060f1SDimitry Andric  j      .Lriscv_save_7_4
51fe6060f1SDimitry Andric
52fe6060f1SDimitry Andric  .globl  __riscv_save_7
53fe6060f1SDimitry Andric  .type   __riscv_save_7,@function
54fe6060f1SDimitry Andric  .globl  __riscv_save_6
55fe6060f1SDimitry Andric  .type   __riscv_save_6,@function
56fe6060f1SDimitry Andric  .globl  __riscv_save_5
57fe6060f1SDimitry Andric  .type   __riscv_save_5,@function
58fe6060f1SDimitry Andric  .globl  __riscv_save_4
59fe6060f1SDimitry Andric  .type   __riscv_save_4,@function
60fe6060f1SDimitry Andric__riscv_save_7:
61fe6060f1SDimitry Andric__riscv_save_6:
62fe6060f1SDimitry Andric__riscv_save_5:
63fe6060f1SDimitry Andric__riscv_save_4:
64fe6060f1SDimitry Andric  addi   sp, sp, -64
65fe6060f1SDimitry Andric  li     t1, 32
66fe6060f1SDimitry Andric.Lriscv_save_7_4:
67fe6060f1SDimitry Andric  sw     s6, 32(sp)
68fe6060f1SDimitry Andric  sw     s5, 36(sp)
69fe6060f1SDimitry Andric  sw     s4, 40(sp)
70fe6060f1SDimitry Andric  sw     s3, 44(sp)
71fe6060f1SDimitry Andric  sw     s2, 48(sp)
72fe6060f1SDimitry Andric  sw     s1, 52(sp)
73fe6060f1SDimitry Andric  sw     s0, 56(sp)
74fe6060f1SDimitry Andric  sw     ra, 60(sp)
75fe6060f1SDimitry Andric  add    sp, sp, t1
76fe6060f1SDimitry Andric  jr     t0
77fe6060f1SDimitry Andric
78fe6060f1SDimitry Andric  .globl  __riscv_save_3
79fe6060f1SDimitry Andric  .type   __riscv_save_3,@function
80fe6060f1SDimitry Andric  .globl  __riscv_save_2
81fe6060f1SDimitry Andric  .type   __riscv_save_2,@function
82fe6060f1SDimitry Andric  .globl  __riscv_save_1
83fe6060f1SDimitry Andric  .type   __riscv_save_1,@function
84fe6060f1SDimitry Andric  .globl  __riscv_save_0
85fe6060f1SDimitry Andric  .type   __riscv_save_0,@function
86fe6060f1SDimitry Andric__riscv_save_3:
87fe6060f1SDimitry Andric__riscv_save_2:
88fe6060f1SDimitry Andric__riscv_save_1:
89fe6060f1SDimitry Andric__riscv_save_0:
90fe6060f1SDimitry Andric  addi    sp, sp, -16
91fe6060f1SDimitry Andric  sw      s2,  0(sp)
92fe6060f1SDimitry Andric  sw      s1,  4(sp)
93fe6060f1SDimitry Andric  sw      s0,  8(sp)
94fe6060f1SDimitry Andric  sw      ra,  12(sp)
95fe6060f1SDimitry Andric  jr      t0
96fe6060f1SDimitry Andric
97dfa39133SDimitry Andric#else
98dfa39133SDimitry Andric
99dfa39133SDimitry Andric  .globl  __riscv_save_2
100dfa39133SDimitry Andric  .type   __riscv_save_2,@function
101dfa39133SDimitry Andric  .globl  __riscv_save_1
102dfa39133SDimitry Andric  .type   __riscv_save_1,@function
103dfa39133SDimitry Andric  .globl  __riscv_save_0
104dfa39133SDimitry Andric  .type   __riscv_save_0,@function
105dfa39133SDimitry Andric__riscv_save_2:
106dfa39133SDimitry Andric__riscv_save_1:
107dfa39133SDimitry Andric__riscv_save_0:
108dfa39133SDimitry Andric  addi    sp, sp, -12
109dfa39133SDimitry Andric  sw      s1,  0(sp)
110dfa39133SDimitry Andric  sw      s0,  4(sp)
111dfa39133SDimitry Andric  sw      ra,  8(sp)
112dfa39133SDimitry Andric  jr      t0
113dfa39133SDimitry Andric
114dfa39133SDimitry Andric#endif
115dfa39133SDimitry Andric
116fe6060f1SDimitry Andric#elif __riscv_xlen == 64
117fe6060f1SDimitry Andric
118*0fca6ea1SDimitry Andric#ifndef __riscv_abi_rve
119dfa39133SDimitry Andric
120fe6060f1SDimitry Andric  .globl  __riscv_save_12
121fe6060f1SDimitry Andric  .type   __riscv_save_12,@function
122fe6060f1SDimitry Andric__riscv_save_12:
123fe6060f1SDimitry Andric  addi   sp, sp, -112
124fe6060f1SDimitry Andric  mv     t1, zero
125fe6060f1SDimitry Andric  sd     s11, 8(sp)
126fe6060f1SDimitry Andric  j      .Lriscv_save_11_10
127fe6060f1SDimitry Andric
128fe6060f1SDimitry Andric  .globl  __riscv_save_11
129fe6060f1SDimitry Andric  .type   __riscv_save_11,@function
130fe6060f1SDimitry Andric  .globl  __riscv_save_10
131fe6060f1SDimitry Andric  .type   __riscv_save_10,@function
132fe6060f1SDimitry Andric__riscv_save_11:
133fe6060f1SDimitry Andric__riscv_save_10:
134fe6060f1SDimitry Andric  addi   sp, sp, -112
135fe6060f1SDimitry Andric  li     t1, 16
136fe6060f1SDimitry Andric.Lriscv_save_11_10:
137fe6060f1SDimitry Andric  sd     s10, 16(sp)
138fe6060f1SDimitry Andric  sd     s9,  24(sp)
139fe6060f1SDimitry Andric  j      .Lriscv_save_9_8
140fe6060f1SDimitry Andric
141fe6060f1SDimitry Andric  .globl  __riscv_save_9
142fe6060f1SDimitry Andric  .type   __riscv_save_9,@function
143fe6060f1SDimitry Andric  .globl  __riscv_save_8
144fe6060f1SDimitry Andric  .type   __riscv_save_8,@function
145fe6060f1SDimitry Andric__riscv_save_9:
146fe6060f1SDimitry Andric__riscv_save_8:
147fe6060f1SDimitry Andric  addi   sp, sp, -112
148fe6060f1SDimitry Andric  li     t1, 32
149fe6060f1SDimitry Andric.Lriscv_save_9_8:
150fe6060f1SDimitry Andric  sd     s8,  32(sp)
151fe6060f1SDimitry Andric  sd     s7,  40(sp)
152fe6060f1SDimitry Andric  j      .Lriscv_save_7_6
153fe6060f1SDimitry Andric
154fe6060f1SDimitry Andric  .globl  __riscv_save_7
155fe6060f1SDimitry Andric  .type   __riscv_save_7,@function
156fe6060f1SDimitry Andric  .globl  __riscv_save_6
157fe6060f1SDimitry Andric  .type   __riscv_save_6,@function
158fe6060f1SDimitry Andric__riscv_save_7:
159fe6060f1SDimitry Andric__riscv_save_6:
160fe6060f1SDimitry Andric  addi   sp, sp, -112
161fe6060f1SDimitry Andric  li     t1, 48
162fe6060f1SDimitry Andric.Lriscv_save_7_6:
163fe6060f1SDimitry Andric  sd     s6,  48(sp)
164fe6060f1SDimitry Andric  sd     s5,  56(sp)
165fe6060f1SDimitry Andric  j      .Lriscv_save_5_4
166fe6060f1SDimitry Andric
167fe6060f1SDimitry Andric  .globl  __riscv_save_5
168fe6060f1SDimitry Andric  .type   __riscv_save_5,@function
169fe6060f1SDimitry Andric  .globl  __riscv_save_4
170fe6060f1SDimitry Andric  .type   __riscv_save_4,@function
171fe6060f1SDimitry Andric__riscv_save_5:
172fe6060f1SDimitry Andric__riscv_save_4:
173fe6060f1SDimitry Andric  addi   sp, sp, -112
174fe6060f1SDimitry Andric  li     t1, 64
175fe6060f1SDimitry Andric.Lriscv_save_5_4:
176fe6060f1SDimitry Andric  sd     s4, 64(sp)
177fe6060f1SDimitry Andric  sd     s3, 72(sp)
178fe6060f1SDimitry Andric  j      .Lriscv_save_3_2
179fe6060f1SDimitry Andric
180fe6060f1SDimitry Andric  .globl  __riscv_save_3
181fe6060f1SDimitry Andric  .type   __riscv_save_3,@function
182fe6060f1SDimitry Andric  .globl  __riscv_save_2
183fe6060f1SDimitry Andric  .type   __riscv_save_2,@function
184fe6060f1SDimitry Andric__riscv_save_3:
185fe6060f1SDimitry Andric__riscv_save_2:
186fe6060f1SDimitry Andric  addi   sp, sp, -112
187fe6060f1SDimitry Andric  li     t1, 80
188fe6060f1SDimitry Andric.Lriscv_save_3_2:
189fe6060f1SDimitry Andric  sd     s2, 80(sp)
190fe6060f1SDimitry Andric  sd     s1, 88(sp)
191fe6060f1SDimitry Andric  sd     s0, 96(sp)
192fe6060f1SDimitry Andric  sd     ra, 104(sp)
193fe6060f1SDimitry Andric  add    sp, sp, t1
194fe6060f1SDimitry Andric  jr     t0
195fe6060f1SDimitry Andric
196fe6060f1SDimitry Andric  .globl  __riscv_save_1
197fe6060f1SDimitry Andric  .type   __riscv_save_1,@function
198fe6060f1SDimitry Andric  .globl  __riscv_save_0
199fe6060f1SDimitry Andric  .type   __riscv_save_0,@function
200349cc55cSDimitry Andric__riscv_save_1:
201349cc55cSDimitry Andric__riscv_save_0:
202fe6060f1SDimitry Andric  addi   sp, sp, -16
203fe6060f1SDimitry Andric  sd     s0, 0(sp)
204fe6060f1SDimitry Andric  sd     ra, 8(sp)
205fe6060f1SDimitry Andric  jr     t0
206fe6060f1SDimitry Andric
207fe6060f1SDimitry Andric#else
208dfa39133SDimitry Andric
209dfa39133SDimitry Andric  .globl  __riscv_save_2
210dfa39133SDimitry Andric  .type   __riscv_save_2,@function
211dfa39133SDimitry Andric  .globl  __riscv_save_1
212dfa39133SDimitry Andric  .type   __riscv_save_1,@function
213dfa39133SDimitry Andric  .globl  __riscv_save_0
214dfa39133SDimitry Andric  .type   __riscv_save_0,@function
215dfa39133SDimitry Andric__riscv_save_2:
216dfa39133SDimitry Andric__riscv_save_1:
217dfa39133SDimitry Andric__riscv_save_0:
218dfa39133SDimitry Andric  addi   sp, sp, -24
219dfa39133SDimitry Andric  sd     s1, 0(sp)
220dfa39133SDimitry Andric  sd     s0, 8(sp)
221dfa39133SDimitry Andric  sd     ra, 16(sp)
222dfa39133SDimitry Andric  jr     t0
223dfa39133SDimitry Andric
224dfa39133SDimitry Andric#endif
225dfa39133SDimitry Andric
226dfa39133SDimitry Andric#else
227fe6060f1SDimitry Andric# error "xlen must be 32 or 64 for save-restore implementation
228fe6060f1SDimitry Andric#endif
229