1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/TargetParser/X86TargetParser.h" 21 #include <optional> 22 23 namespace clang { 24 namespace targets { 25 26 static constexpr Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 67 }; 68 69 const TargetInfo::AddlRegName AddlRegNames[] = { 70 {{"al", "ah", "eax", "rax"}, 0}, 71 {{"bl", "bh", "ebx", "rbx"}, 3}, 72 {{"cl", "ch", "ecx", "rcx"}, 2}, 73 {{"dl", "dh", "edx", "rdx"}, 1}, 74 {{"esi", "rsi"}, 4}, 75 {{"edi", "rdi"}, 5}, 76 {{"esp", "rsp"}, 7}, 77 {{"ebp", "rbp"}, 6}, 78 {{"r8d", "r8w", "r8b"}, 38}, 79 {{"r9d", "r9w", "r9b"}, 39}, 80 {{"r10d", "r10w", "r10b"}, 40}, 81 {{"r11d", "r11w", "r11b"}, 41}, 82 {{"r12d", "r12w", "r12b"}, 42}, 83 {{"r13d", "r13w", "r13b"}, 43}, 84 {{"r14d", "r14w", "r14b"}, 44}, 85 {{"r15d", "r15w", "r15b"}, 45}, 86 }; 87 88 } // namespace targets 89 } // namespace clang 90 91 using namespace clang; 92 using namespace clang::targets; 93 94 bool X86TargetInfo::setFPMath(StringRef Name) { 95 if (Name == "387") { 96 FPMath = FP_387; 97 return true; 98 } 99 if (Name == "sse") { 100 FPMath = FP_SSE; 101 return true; 102 } 103 return false; 104 } 105 106 bool X86TargetInfo::initFeatureMap( 107 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 108 const std::vector<std::string> &FeaturesVec) const { 109 // FIXME: This *really* should not be here. 110 // X86_64 always has SSE2. 111 if (getTriple().getArch() == llvm::Triple::x86_64) 112 setFeatureEnabled(Features, "sse2", true); 113 114 using namespace llvm::X86; 115 116 SmallVector<StringRef, 16> CPUFeatures; 117 getFeaturesForCPU(CPU, CPUFeatures); 118 for (auto &F : CPUFeatures) 119 setFeatureEnabled(Features, F, true); 120 121 std::vector<std::string> UpdatedFeaturesVec; 122 std::vector<std::string> UpdatedAVX10FeaturesVec; 123 enum { FE_NOSET = -1, FE_FALSE, FE_TRUE }; 124 int HasEVEX512 = FE_NOSET; 125 bool HasAVX512F = Features.lookup("avx512f"); 126 bool HasAVX10 = Features.lookup("avx10.1-256"); 127 bool HasAVX10_512 = Features.lookup("avx10.1-512"); 128 std::string LastAVX10; 129 std::string LastAVX512; 130 for (const auto &Feature : FeaturesVec) { 131 // Expand general-regs-only to -x86, -mmx and -sse 132 if (Feature == "+general-regs-only") { 133 UpdatedFeaturesVec.push_back("-x87"); 134 UpdatedFeaturesVec.push_back("-mmx"); 135 UpdatedFeaturesVec.push_back("-sse"); 136 continue; 137 } 138 139 if (Feature.substr(1, 6) == "avx10.") { 140 if (Feature[0] == '+') { 141 HasAVX10 = true; 142 if (Feature.substr(Feature.size() - 3, 3) == "512") 143 HasAVX10_512 = true; 144 LastAVX10 = Feature; 145 } else if (HasAVX10 && Feature == "-avx10.1-256") { 146 HasAVX10 = false; 147 HasAVX10_512 = false; 148 } else if (HasAVX10_512 && Feature == "-avx10.1-512") { 149 HasAVX10_512 = false; 150 } 151 // Postpone AVX10 features handling after AVX512 settled. 152 UpdatedAVX10FeaturesVec.push_back(Feature); 153 continue; 154 } else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") { 155 HasAVX512F = true; 156 LastAVX512 = Feature; 157 } else if (HasAVX512F && Feature == "-avx512f") { 158 HasAVX512F = false; 159 } else if (HasEVEX512 != FE_TRUE && Feature == "+evex512") { 160 HasEVEX512 = FE_TRUE; 161 continue; 162 } else if (HasEVEX512 != FE_FALSE && Feature == "-evex512") { 163 HasEVEX512 = FE_FALSE; 164 continue; 165 } 166 167 UpdatedFeaturesVec.push_back(Feature); 168 } 169 llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec); 170 // HasEVEX512 is a three-states flag. We need to turn it into [+-]evex512 171 // according to other features. 172 if (HasAVX512F) { 173 UpdatedFeaturesVec.push_back(HasEVEX512 == FE_FALSE ? "-evex512" 174 : "+evex512"); 175 if (HasAVX10 && !HasAVX10_512 && HasEVEX512 != FE_FALSE) 176 Diags.Report(diag::warn_invalid_feature_combination) 177 << LastAVX512 + " " + LastAVX10 + "; will be promoted to avx10.1-512"; 178 } else if (HasAVX10) { 179 if (HasEVEX512 != FE_NOSET) 180 Diags.Report(diag::warn_invalid_feature_combination) 181 << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512"); 182 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512"); 183 } 184 185 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 186 return false; 187 188 // Can't do this earlier because we need to be able to explicitly enable 189 // or disable these features and the things that they depend upon. 190 191 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 192 auto I = Features.find("sse4.2"); 193 if (I != Features.end() && I->getValue() && 194 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 195 Features["popcnt"] = true; 196 197 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 198 // then enable MMX. 199 I = Features.find("sse"); 200 if (I != Features.end() && I->getValue() && 201 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 202 Features["mmx"] = true; 203 204 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 205 I = Features.find("avx"); 206 if (I != Features.end() && I->getValue() && 207 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 208 Features["xsave"] = true; 209 210 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 211 I = Features.find("sse4.2"); 212 if (I != Features.end() && I->getValue() && 213 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 214 Features["crc32"] = true; 215 216 return true; 217 } 218 219 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 220 StringRef Name, bool Enabled) const { 221 if (Name == "sse4") { 222 // We can get here via the __target__ attribute since that's not controlled 223 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 224 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 225 // disabled. 226 if (Enabled) 227 Name = "sse4.2"; 228 else 229 Name = "sse4.1"; 230 } 231 232 Features[Name] = Enabled; 233 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 234 } 235 236 /// handleTargetFeatures - Perform initialization based on the user 237 /// configured set of features. 238 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 239 DiagnosticsEngine &Diags) { 240 for (const auto &Feature : Features) { 241 if (Feature[0] != '+') 242 continue; 243 244 if (Feature == "+aes") { 245 HasAES = true; 246 } else if (Feature == "+vaes") { 247 HasVAES = true; 248 } else if (Feature == "+pclmul") { 249 HasPCLMUL = true; 250 } else if (Feature == "+vpclmulqdq") { 251 HasVPCLMULQDQ = true; 252 } else if (Feature == "+lzcnt") { 253 HasLZCNT = true; 254 } else if (Feature == "+rdrnd") { 255 HasRDRND = true; 256 } else if (Feature == "+fsgsbase") { 257 HasFSGSBASE = true; 258 } else if (Feature == "+bmi") { 259 HasBMI = true; 260 } else if (Feature == "+bmi2") { 261 HasBMI2 = true; 262 } else if (Feature == "+popcnt") { 263 HasPOPCNT = true; 264 } else if (Feature == "+rtm") { 265 HasRTM = true; 266 } else if (Feature == "+prfchw") { 267 HasPRFCHW = true; 268 } else if (Feature == "+rdseed") { 269 HasRDSEED = true; 270 } else if (Feature == "+adx") { 271 HasADX = true; 272 } else if (Feature == "+tbm") { 273 HasTBM = true; 274 } else if (Feature == "+lwp") { 275 HasLWP = true; 276 } else if (Feature == "+fma") { 277 HasFMA = true; 278 } else if (Feature == "+f16c") { 279 HasF16C = true; 280 } else if (Feature == "+gfni") { 281 HasGFNI = true; 282 } else if (Feature == "+evex512") { 283 HasEVEX512 = true; 284 } else if (Feature == "+avx10.1-256") { 285 HasAVX10_1 = true; 286 } else if (Feature == "+avx10.1-512") { 287 HasAVX10_1_512 = true; 288 } else if (Feature == "+avx512cd") { 289 HasAVX512CD = true; 290 } else if (Feature == "+avx512vpopcntdq") { 291 HasAVX512VPOPCNTDQ = true; 292 } else if (Feature == "+avx512vnni") { 293 HasAVX512VNNI = true; 294 } else if (Feature == "+avx512bf16") { 295 HasAVX512BF16 = true; 296 } else if (Feature == "+avx512er") { 297 HasAVX512ER = true; 298 } else if (Feature == "+avx512fp16") { 299 HasAVX512FP16 = true; 300 HasLegalHalfType = true; 301 } else if (Feature == "+avx512pf") { 302 HasAVX512PF = true; 303 } else if (Feature == "+avx512dq") { 304 HasAVX512DQ = true; 305 } else if (Feature == "+avx512bitalg") { 306 HasAVX512BITALG = true; 307 } else if (Feature == "+avx512bw") { 308 HasAVX512BW = true; 309 } else if (Feature == "+avx512vl") { 310 HasAVX512VL = true; 311 } else if (Feature == "+avx512vbmi") { 312 HasAVX512VBMI = true; 313 } else if (Feature == "+avx512vbmi2") { 314 HasAVX512VBMI2 = true; 315 } else if (Feature == "+avx512ifma") { 316 HasAVX512IFMA = true; 317 } else if (Feature == "+avx512vp2intersect") { 318 HasAVX512VP2INTERSECT = true; 319 } else if (Feature == "+sha") { 320 HasSHA = true; 321 } else if (Feature == "+sha512") { 322 HasSHA512 = true; 323 } else if (Feature == "+shstk") { 324 HasSHSTK = true; 325 } else if (Feature == "+sm3") { 326 HasSM3 = true; 327 } else if (Feature == "+sm4") { 328 HasSM4 = true; 329 } else if (Feature == "+movbe") { 330 HasMOVBE = true; 331 } else if (Feature == "+sgx") { 332 HasSGX = true; 333 } else if (Feature == "+cx8") { 334 HasCX8 = true; 335 } else if (Feature == "+cx16") { 336 HasCX16 = true; 337 } else if (Feature == "+fxsr") { 338 HasFXSR = true; 339 } else if (Feature == "+xsave") { 340 HasXSAVE = true; 341 } else if (Feature == "+xsaveopt") { 342 HasXSAVEOPT = true; 343 } else if (Feature == "+xsavec") { 344 HasXSAVEC = true; 345 } else if (Feature == "+xsaves") { 346 HasXSAVES = true; 347 } else if (Feature == "+mwaitx") { 348 HasMWAITX = true; 349 } else if (Feature == "+pku") { 350 HasPKU = true; 351 } else if (Feature == "+clflushopt") { 352 HasCLFLUSHOPT = true; 353 } else if (Feature == "+clwb") { 354 HasCLWB = true; 355 } else if (Feature == "+wbnoinvd") { 356 HasWBNOINVD = true; 357 } else if (Feature == "+prefetchi") { 358 HasPREFETCHI = true; 359 } else if (Feature == "+prefetchwt1") { 360 HasPREFETCHWT1 = true; 361 } else if (Feature == "+clzero") { 362 HasCLZERO = true; 363 } else if (Feature == "+cldemote") { 364 HasCLDEMOTE = true; 365 } else if (Feature == "+rdpid") { 366 HasRDPID = true; 367 } else if (Feature == "+rdpru") { 368 HasRDPRU = true; 369 } else if (Feature == "+kl") { 370 HasKL = true; 371 } else if (Feature == "+widekl") { 372 HasWIDEKL = true; 373 } else if (Feature == "+retpoline-external-thunk") { 374 HasRetpolineExternalThunk = true; 375 } else if (Feature == "+sahf") { 376 HasLAHFSAHF = true; 377 } else if (Feature == "+waitpkg") { 378 HasWAITPKG = true; 379 } else if (Feature == "+movdiri") { 380 HasMOVDIRI = true; 381 } else if (Feature == "+movdir64b") { 382 HasMOVDIR64B = true; 383 } else if (Feature == "+pconfig") { 384 HasPCONFIG = true; 385 } else if (Feature == "+ptwrite") { 386 HasPTWRITE = true; 387 } else if (Feature == "+invpcid") { 388 HasINVPCID = true; 389 } else if (Feature == "+enqcmd") { 390 HasENQCMD = true; 391 } else if (Feature == "+hreset") { 392 HasHRESET = true; 393 } else if (Feature == "+amx-bf16") { 394 HasAMXBF16 = true; 395 } else if (Feature == "+amx-fp16") { 396 HasAMXFP16 = true; 397 } else if (Feature == "+amx-int8") { 398 HasAMXINT8 = true; 399 } else if (Feature == "+amx-tile") { 400 HasAMXTILE = true; 401 } else if (Feature == "+amx-complex") { 402 HasAMXCOMPLEX = true; 403 } else if (Feature == "+cmpccxadd") { 404 HasCMPCCXADD = true; 405 } else if (Feature == "+raoint") { 406 HasRAOINT = true; 407 } else if (Feature == "+avxifma") { 408 HasAVXIFMA = true; 409 } else if (Feature == "+avxneconvert") { 410 HasAVXNECONVERT= true; 411 } else if (Feature == "+avxvnni") { 412 HasAVXVNNI = true; 413 } else if (Feature == "+avxvnniint16") { 414 HasAVXVNNIINT16 = true; 415 } else if (Feature == "+avxvnniint8") { 416 HasAVXVNNIINT8 = true; 417 } else if (Feature == "+serialize") { 418 HasSERIALIZE = true; 419 } else if (Feature == "+tsxldtrk") { 420 HasTSXLDTRK = true; 421 } else if (Feature == "+uintr") { 422 HasUINTR = true; 423 } else if (Feature == "+usermsr") { 424 HasUSERMSR = true; 425 } else if (Feature == "+crc32") { 426 HasCRC32 = true; 427 } else if (Feature == "+x87") { 428 HasX87 = true; 429 } else if (Feature == "+fullbf16") { 430 HasFullBFloat16 = true; 431 } else if (Feature == "+egpr") { 432 HasEGPR = true; 433 } else if (Feature == "+push2pop2") { 434 HasPush2Pop2 = true; 435 } else if (Feature == "+ppx") { 436 HasPPX = true; 437 } else if (Feature == "+ndd") { 438 HasNDD = true; 439 } else if (Feature == "+ccmp") { 440 HasCCMP = true; 441 } else if (Feature == "+cf") { 442 HasCF = true; 443 } 444 445 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 446 .Case("+avx512f", AVX512F) 447 .Case("+avx2", AVX2) 448 .Case("+avx", AVX) 449 .Case("+sse4.2", SSE42) 450 .Case("+sse4.1", SSE41) 451 .Case("+ssse3", SSSE3) 452 .Case("+sse3", SSE3) 453 .Case("+sse2", SSE2) 454 .Case("+sse", SSE1) 455 .Default(NoSSE); 456 SSELevel = std::max(SSELevel, Level); 457 458 HasFloat16 = SSELevel >= SSE2; 459 460 // X86 target has bfloat16 emulation support in the backend, where 461 // bfloat16 is treated as a 32-bit float, arithmetic operations are 462 // performed in 32-bit, and the result is converted back to bfloat16. 463 // Truncation and extension between bfloat16 and 32-bit float are supported 464 // by the compiler-rt library. However, native bfloat16 support is currently 465 // not available in the X86 target. Hence, HasFullBFloat16 will be false 466 // until native bfloat16 support is available. HasFullBFloat16 is used to 467 // determine whether to automatically use excess floating point precision 468 // for bfloat16 arithmetic operations in the front-end. 469 HasBFloat16 = SSELevel >= SSE2; 470 471 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 472 .Case("+3dnowa", AMD3DNowAthlon) 473 .Case("+3dnow", AMD3DNow) 474 .Case("+mmx", MMX) 475 .Default(NoMMX3DNow); 476 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 477 478 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 479 .Case("+xop", XOP) 480 .Case("+fma4", FMA4) 481 .Case("+sse4a", SSE4A) 482 .Default(NoXOP); 483 XOPLevel = std::max(XOPLevel, XLevel); 484 } 485 486 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 487 // matches the selected sse level. 488 if ((FPMath == FP_SSE && SSELevel < SSE1) || 489 (FPMath == FP_387 && SSELevel >= SSE1)) { 490 Diags.Report(diag::err_target_unsupported_fpmath) 491 << (FPMath == FP_SSE ? "sse" : "387"); 492 return false; 493 } 494 495 // FIXME: We should allow long double type on 32-bits to match with GCC. 496 // This requires backend to be able to lower f80 without x87 first. 497 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 498 HasLongDouble = false; 499 500 return true; 501 } 502 503 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 504 /// definitions for this particular subtarget. 505 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 506 MacroBuilder &Builder) const { 507 // Inline assembly supports X86 flag outputs. 508 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 509 510 std::string CodeModel = getTargetOpts().CodeModel; 511 if (CodeModel == "default") 512 CodeModel = "small"; 513 Builder.defineMacro("__code_model_" + CodeModel + "__"); 514 515 // Target identification. 516 if (getTriple().getArch() == llvm::Triple::x86_64) { 517 Builder.defineMacro("__amd64__"); 518 Builder.defineMacro("__amd64"); 519 Builder.defineMacro("__x86_64"); 520 Builder.defineMacro("__x86_64__"); 521 if (getTriple().getArchName() == "x86_64h") { 522 Builder.defineMacro("__x86_64h"); 523 Builder.defineMacro("__x86_64h__"); 524 } 525 } else { 526 DefineStd(Builder, "i386", Opts); 527 } 528 529 Builder.defineMacro("__SEG_GS"); 530 Builder.defineMacro("__SEG_FS"); 531 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 532 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 533 534 // Subtarget options. 535 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 536 // truly should be based on -mtune options. 537 using namespace llvm::X86; 538 switch (CPU) { 539 case CK_None: 540 break; 541 case CK_i386: 542 // The rest are coming from the i386 define above. 543 Builder.defineMacro("__tune_i386__"); 544 break; 545 case CK_i486: 546 case CK_WinChipC6: 547 case CK_WinChip2: 548 case CK_C3: 549 defineCPUMacros(Builder, "i486"); 550 break; 551 case CK_PentiumMMX: 552 Builder.defineMacro("__pentium_mmx__"); 553 Builder.defineMacro("__tune_pentium_mmx__"); 554 [[fallthrough]]; 555 case CK_i586: 556 case CK_Pentium: 557 defineCPUMacros(Builder, "i586"); 558 defineCPUMacros(Builder, "pentium"); 559 break; 560 case CK_Pentium3: 561 case CK_PentiumM: 562 Builder.defineMacro("__tune_pentium3__"); 563 [[fallthrough]]; 564 case CK_Pentium2: 565 case CK_C3_2: 566 Builder.defineMacro("__tune_pentium2__"); 567 [[fallthrough]]; 568 case CK_PentiumPro: 569 case CK_i686: 570 defineCPUMacros(Builder, "i686"); 571 defineCPUMacros(Builder, "pentiumpro"); 572 break; 573 case CK_Pentium4: 574 defineCPUMacros(Builder, "pentium4"); 575 break; 576 case CK_Yonah: 577 case CK_Prescott: 578 case CK_Nocona: 579 defineCPUMacros(Builder, "nocona"); 580 break; 581 case CK_Core2: 582 case CK_Penryn: 583 defineCPUMacros(Builder, "core2"); 584 break; 585 case CK_Bonnell: 586 defineCPUMacros(Builder, "atom"); 587 break; 588 case CK_Silvermont: 589 defineCPUMacros(Builder, "slm"); 590 break; 591 case CK_Goldmont: 592 defineCPUMacros(Builder, "goldmont"); 593 break; 594 case CK_GoldmontPlus: 595 defineCPUMacros(Builder, "goldmont_plus"); 596 break; 597 case CK_Tremont: 598 defineCPUMacros(Builder, "tremont"); 599 break; 600 // Gracemont and later atom-cores use P-core cpu macros. 601 case CK_Gracemont: 602 case CK_Nehalem: 603 case CK_Westmere: 604 case CK_SandyBridge: 605 case CK_IvyBridge: 606 case CK_Haswell: 607 case CK_Broadwell: 608 case CK_SkylakeClient: 609 case CK_SkylakeServer: 610 case CK_Cascadelake: 611 case CK_Cooperlake: 612 case CK_Cannonlake: 613 case CK_IcelakeClient: 614 case CK_Rocketlake: 615 case CK_IcelakeServer: 616 case CK_Tigerlake: 617 case CK_SapphireRapids: 618 case CK_Alderlake: 619 case CK_Raptorlake: 620 case CK_Meteorlake: 621 case CK_Arrowlake: 622 case CK_ArrowlakeS: 623 case CK_Lunarlake: 624 case CK_Pantherlake: 625 case CK_Sierraforest: 626 case CK_Grandridge: 627 case CK_Graniterapids: 628 case CK_GraniterapidsD: 629 case CK_Emeraldrapids: 630 case CK_Clearwaterforest: 631 // FIXME: Historically, we defined this legacy name, it would be nice to 632 // remove it at some point. We've never exposed fine-grained names for 633 // recent primary x86 CPUs, and we should keep it that way. 634 defineCPUMacros(Builder, "corei7"); 635 break; 636 case CK_KNL: 637 defineCPUMacros(Builder, "knl"); 638 break; 639 case CK_KNM: 640 break; 641 case CK_Lakemont: 642 defineCPUMacros(Builder, "i586", /*Tuning*/false); 643 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 644 Builder.defineMacro("__tune_lakemont__"); 645 break; 646 case CK_K6_2: 647 Builder.defineMacro("__k6_2__"); 648 Builder.defineMacro("__tune_k6_2__"); 649 [[fallthrough]]; 650 case CK_K6_3: 651 if (CPU != CK_K6_2) { // In case of fallthrough 652 // FIXME: GCC may be enabling these in cases where some other k6 653 // architecture is specified but -m3dnow is explicitly provided. The 654 // exact semantics need to be determined and emulated here. 655 Builder.defineMacro("__k6_3__"); 656 Builder.defineMacro("__tune_k6_3__"); 657 } 658 [[fallthrough]]; 659 case CK_K6: 660 defineCPUMacros(Builder, "k6"); 661 break; 662 case CK_Athlon: 663 case CK_AthlonXP: 664 defineCPUMacros(Builder, "athlon"); 665 if (SSELevel != NoSSE) { 666 Builder.defineMacro("__athlon_sse__"); 667 Builder.defineMacro("__tune_athlon_sse__"); 668 } 669 break; 670 case CK_K8: 671 case CK_K8SSE3: 672 case CK_x86_64: 673 defineCPUMacros(Builder, "k8"); 674 break; 675 case CK_x86_64_v2: 676 case CK_x86_64_v3: 677 case CK_x86_64_v4: 678 break; 679 case CK_AMDFAM10: 680 defineCPUMacros(Builder, "amdfam10"); 681 break; 682 case CK_BTVER1: 683 defineCPUMacros(Builder, "btver1"); 684 break; 685 case CK_BTVER2: 686 defineCPUMacros(Builder, "btver2"); 687 break; 688 case CK_BDVER1: 689 defineCPUMacros(Builder, "bdver1"); 690 break; 691 case CK_BDVER2: 692 defineCPUMacros(Builder, "bdver2"); 693 break; 694 case CK_BDVER3: 695 defineCPUMacros(Builder, "bdver3"); 696 break; 697 case CK_BDVER4: 698 defineCPUMacros(Builder, "bdver4"); 699 break; 700 case CK_ZNVER1: 701 defineCPUMacros(Builder, "znver1"); 702 break; 703 case CK_ZNVER2: 704 defineCPUMacros(Builder, "znver2"); 705 break; 706 case CK_ZNVER3: 707 defineCPUMacros(Builder, "znver3"); 708 break; 709 case CK_ZNVER4: 710 defineCPUMacros(Builder, "znver4"); 711 break; 712 case CK_Geode: 713 defineCPUMacros(Builder, "geode"); 714 break; 715 } 716 717 // Target properties. 718 Builder.defineMacro("__REGISTER_PREFIX__", ""); 719 720 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 721 // functions in glibc header files that use FP Stack inline asm which the 722 // backend can't deal with (PR879). 723 Builder.defineMacro("__NO_MATH_INLINES"); 724 725 if (HasAES) 726 Builder.defineMacro("__AES__"); 727 728 if (HasVAES) 729 Builder.defineMacro("__VAES__"); 730 731 if (HasPCLMUL) 732 Builder.defineMacro("__PCLMUL__"); 733 734 if (HasVPCLMULQDQ) 735 Builder.defineMacro("__VPCLMULQDQ__"); 736 737 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 738 // the feature flag only applies to 64-bit mode. 739 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 740 Builder.defineMacro("__LAHF_SAHF__"); 741 742 if (HasLZCNT) 743 Builder.defineMacro("__LZCNT__"); 744 745 if (HasRDRND) 746 Builder.defineMacro("__RDRND__"); 747 748 if (HasFSGSBASE) 749 Builder.defineMacro("__FSGSBASE__"); 750 751 if (HasBMI) 752 Builder.defineMacro("__BMI__"); 753 754 if (HasBMI2) 755 Builder.defineMacro("__BMI2__"); 756 757 if (HasPOPCNT) 758 Builder.defineMacro("__POPCNT__"); 759 760 if (HasRTM) 761 Builder.defineMacro("__RTM__"); 762 763 if (HasPRFCHW) 764 Builder.defineMacro("__PRFCHW__"); 765 766 if (HasRDSEED) 767 Builder.defineMacro("__RDSEED__"); 768 769 if (HasADX) 770 Builder.defineMacro("__ADX__"); 771 772 if (HasTBM) 773 Builder.defineMacro("__TBM__"); 774 775 if (HasLWP) 776 Builder.defineMacro("__LWP__"); 777 778 if (HasMWAITX) 779 Builder.defineMacro("__MWAITX__"); 780 781 if (HasMOVBE) 782 Builder.defineMacro("__MOVBE__"); 783 784 switch (XOPLevel) { 785 case XOP: 786 Builder.defineMacro("__XOP__"); 787 [[fallthrough]]; 788 case FMA4: 789 Builder.defineMacro("__FMA4__"); 790 [[fallthrough]]; 791 case SSE4A: 792 Builder.defineMacro("__SSE4A__"); 793 [[fallthrough]]; 794 case NoXOP: 795 break; 796 } 797 798 if (HasFMA) 799 Builder.defineMacro("__FMA__"); 800 801 if (HasF16C) 802 Builder.defineMacro("__F16C__"); 803 804 if (HasGFNI) 805 Builder.defineMacro("__GFNI__"); 806 807 if (HasEVEX512) 808 Builder.defineMacro("__EVEX512__"); 809 if (HasAVX10_1) 810 Builder.defineMacro("__AVX10_1__"); 811 if (HasAVX10_1_512) 812 Builder.defineMacro("__AVX10_1_512__"); 813 if (HasAVX512CD) 814 Builder.defineMacro("__AVX512CD__"); 815 if (HasAVX512VPOPCNTDQ) 816 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 817 if (HasAVX512VNNI) 818 Builder.defineMacro("__AVX512VNNI__"); 819 if (HasAVX512BF16) 820 Builder.defineMacro("__AVX512BF16__"); 821 if (HasAVX512ER) 822 Builder.defineMacro("__AVX512ER__"); 823 if (HasAVX512FP16) 824 Builder.defineMacro("__AVX512FP16__"); 825 if (HasAVX512PF) 826 Builder.defineMacro("__AVX512PF__"); 827 if (HasAVX512DQ) 828 Builder.defineMacro("__AVX512DQ__"); 829 if (HasAVX512BITALG) 830 Builder.defineMacro("__AVX512BITALG__"); 831 if (HasAVX512BW) 832 Builder.defineMacro("__AVX512BW__"); 833 if (HasAVX512VL) { 834 Builder.defineMacro("__AVX512VL__"); 835 Builder.defineMacro("__EVEX256__"); 836 } 837 if (HasAVX512VBMI) 838 Builder.defineMacro("__AVX512VBMI__"); 839 if (HasAVX512VBMI2) 840 Builder.defineMacro("__AVX512VBMI2__"); 841 if (HasAVX512IFMA) 842 Builder.defineMacro("__AVX512IFMA__"); 843 if (HasAVX512VP2INTERSECT) 844 Builder.defineMacro("__AVX512VP2INTERSECT__"); 845 if (HasSHA) 846 Builder.defineMacro("__SHA__"); 847 if (HasSHA512) 848 Builder.defineMacro("__SHA512__"); 849 850 if (HasFXSR) 851 Builder.defineMacro("__FXSR__"); 852 if (HasXSAVE) 853 Builder.defineMacro("__XSAVE__"); 854 if (HasXSAVEOPT) 855 Builder.defineMacro("__XSAVEOPT__"); 856 if (HasXSAVEC) 857 Builder.defineMacro("__XSAVEC__"); 858 if (HasXSAVES) 859 Builder.defineMacro("__XSAVES__"); 860 if (HasPKU) 861 Builder.defineMacro("__PKU__"); 862 if (HasCLFLUSHOPT) 863 Builder.defineMacro("__CLFLUSHOPT__"); 864 if (HasCLWB) 865 Builder.defineMacro("__CLWB__"); 866 if (HasWBNOINVD) 867 Builder.defineMacro("__WBNOINVD__"); 868 if (HasSHSTK) 869 Builder.defineMacro("__SHSTK__"); 870 if (HasSGX) 871 Builder.defineMacro("__SGX__"); 872 if (HasSM3) 873 Builder.defineMacro("__SM3__"); 874 if (HasSM4) 875 Builder.defineMacro("__SM4__"); 876 if (HasPREFETCHI) 877 Builder.defineMacro("__PREFETCHI__"); 878 if (HasPREFETCHWT1) 879 Builder.defineMacro("__PREFETCHWT1__"); 880 if (HasCLZERO) 881 Builder.defineMacro("__CLZERO__"); 882 if (HasKL) 883 Builder.defineMacro("__KL__"); 884 if (HasWIDEKL) 885 Builder.defineMacro("__WIDEKL__"); 886 if (HasRDPID) 887 Builder.defineMacro("__RDPID__"); 888 if (HasRDPRU) 889 Builder.defineMacro("__RDPRU__"); 890 if (HasCLDEMOTE) 891 Builder.defineMacro("__CLDEMOTE__"); 892 if (HasWAITPKG) 893 Builder.defineMacro("__WAITPKG__"); 894 if (HasMOVDIRI) 895 Builder.defineMacro("__MOVDIRI__"); 896 if (HasMOVDIR64B) 897 Builder.defineMacro("__MOVDIR64B__"); 898 if (HasPCONFIG) 899 Builder.defineMacro("__PCONFIG__"); 900 if (HasPTWRITE) 901 Builder.defineMacro("__PTWRITE__"); 902 if (HasINVPCID) 903 Builder.defineMacro("__INVPCID__"); 904 if (HasENQCMD) 905 Builder.defineMacro("__ENQCMD__"); 906 if (HasHRESET) 907 Builder.defineMacro("__HRESET__"); 908 if (HasAMXTILE) 909 Builder.defineMacro("__AMX_TILE__"); 910 if (HasAMXINT8) 911 Builder.defineMacro("__AMX_INT8__"); 912 if (HasAMXBF16) 913 Builder.defineMacro("__AMX_BF16__"); 914 if (HasAMXFP16) 915 Builder.defineMacro("__AMX_FP16__"); 916 if (HasAMXCOMPLEX) 917 Builder.defineMacro("__AMX_COMPLEX__"); 918 if (HasCMPCCXADD) 919 Builder.defineMacro("__CMPCCXADD__"); 920 if (HasRAOINT) 921 Builder.defineMacro("__RAOINT__"); 922 if (HasAVXIFMA) 923 Builder.defineMacro("__AVXIFMA__"); 924 if (HasAVXNECONVERT) 925 Builder.defineMacro("__AVXNECONVERT__"); 926 if (HasAVXVNNI) 927 Builder.defineMacro("__AVXVNNI__"); 928 if (HasAVXVNNIINT16) 929 Builder.defineMacro("__AVXVNNIINT16__"); 930 if (HasAVXVNNIINT8) 931 Builder.defineMacro("__AVXVNNIINT8__"); 932 if (HasSERIALIZE) 933 Builder.defineMacro("__SERIALIZE__"); 934 if (HasTSXLDTRK) 935 Builder.defineMacro("__TSXLDTRK__"); 936 if (HasUINTR) 937 Builder.defineMacro("__UINTR__"); 938 if (HasUSERMSR) 939 Builder.defineMacro("__USERMSR__"); 940 if (HasCRC32) 941 Builder.defineMacro("__CRC32__"); 942 if (HasEGPR) 943 Builder.defineMacro("__EGPR__"); 944 if (HasPush2Pop2) 945 Builder.defineMacro("__PUSH2POP2__"); 946 if (HasPPX) 947 Builder.defineMacro("__PPX__"); 948 if (HasNDD) 949 Builder.defineMacro("__NDD__"); 950 if (HasCCMP) 951 Builder.defineMacro("__CCMP__"); 952 if (HasCF) 953 Builder.defineMacro("__CF__"); 954 955 // Each case falls through to the previous one here. 956 switch (SSELevel) { 957 case AVX512F: 958 Builder.defineMacro("__AVX512F__"); 959 [[fallthrough]]; 960 case AVX2: 961 Builder.defineMacro("__AVX2__"); 962 [[fallthrough]]; 963 case AVX: 964 Builder.defineMacro("__AVX__"); 965 [[fallthrough]]; 966 case SSE42: 967 Builder.defineMacro("__SSE4_2__"); 968 [[fallthrough]]; 969 case SSE41: 970 Builder.defineMacro("__SSE4_1__"); 971 [[fallthrough]]; 972 case SSSE3: 973 Builder.defineMacro("__SSSE3__"); 974 [[fallthrough]]; 975 case SSE3: 976 Builder.defineMacro("__SSE3__"); 977 [[fallthrough]]; 978 case SSE2: 979 Builder.defineMacro("__SSE2__"); 980 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 981 [[fallthrough]]; 982 case SSE1: 983 Builder.defineMacro("__SSE__"); 984 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 985 [[fallthrough]]; 986 case NoSSE: 987 break; 988 } 989 990 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 991 switch (SSELevel) { 992 case AVX512F: 993 case AVX2: 994 case AVX: 995 case SSE42: 996 case SSE41: 997 case SSSE3: 998 case SSE3: 999 case SSE2: 1000 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1001 break; 1002 case SSE1: 1003 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1004 break; 1005 default: 1006 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1007 break; 1008 } 1009 } 1010 1011 // Each case falls through to the previous one here. 1012 switch (MMX3DNowLevel) { 1013 case AMD3DNowAthlon: 1014 Builder.defineMacro("__3dNOW_A__"); 1015 [[fallthrough]]; 1016 case AMD3DNow: 1017 Builder.defineMacro("__3dNOW__"); 1018 [[fallthrough]]; 1019 case MMX: 1020 Builder.defineMacro("__MMX__"); 1021 [[fallthrough]]; 1022 case NoMMX3DNow: 1023 break; 1024 } 1025 1026 if (CPU >= CK_i486 || CPU == CK_None) { 1027 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1028 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1029 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1030 } 1031 if (HasCX8) 1032 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1033 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1034 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1035 1036 if (HasFloat128) 1037 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1038 } 1039 1040 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1041 return llvm::StringSwitch<bool>(Name) 1042 .Case("3dnow", true) 1043 .Case("3dnowa", true) 1044 .Case("adx", true) 1045 .Case("aes", true) 1046 .Case("amx-bf16", true) 1047 .Case("amx-complex", true) 1048 .Case("amx-fp16", true) 1049 .Case("amx-int8", true) 1050 .Case("amx-tile", true) 1051 .Case("avx", true) 1052 .Case("avx10.1-256", true) 1053 .Case("avx10.1-512", true) 1054 .Case("avx2", true) 1055 .Case("avx512f", true) 1056 .Case("avx512cd", true) 1057 .Case("avx512vpopcntdq", true) 1058 .Case("avx512vnni", true) 1059 .Case("avx512bf16", true) 1060 .Case("avx512er", true) 1061 .Case("avx512fp16", true) 1062 .Case("avx512pf", true) 1063 .Case("avx512dq", true) 1064 .Case("avx512bitalg", true) 1065 .Case("avx512bw", true) 1066 .Case("avx512vl", true) 1067 .Case("avx512vbmi", true) 1068 .Case("avx512vbmi2", true) 1069 .Case("avx512ifma", true) 1070 .Case("avx512vp2intersect", true) 1071 .Case("avxifma", true) 1072 .Case("avxneconvert", true) 1073 .Case("avxvnni", true) 1074 .Case("avxvnniint16", true) 1075 .Case("avxvnniint8", true) 1076 .Case("bmi", true) 1077 .Case("bmi2", true) 1078 .Case("cldemote", true) 1079 .Case("clflushopt", true) 1080 .Case("clwb", true) 1081 .Case("clzero", true) 1082 .Case("cmpccxadd", true) 1083 .Case("crc32", true) 1084 .Case("cx16", true) 1085 .Case("enqcmd", true) 1086 .Case("evex512", true) 1087 .Case("f16c", true) 1088 .Case("fma", true) 1089 .Case("fma4", true) 1090 .Case("fsgsbase", true) 1091 .Case("fxsr", true) 1092 .Case("general-regs-only", true) 1093 .Case("gfni", true) 1094 .Case("hreset", true) 1095 .Case("invpcid", true) 1096 .Case("kl", true) 1097 .Case("widekl", true) 1098 .Case("lwp", true) 1099 .Case("lzcnt", true) 1100 .Case("mmx", true) 1101 .Case("movbe", true) 1102 .Case("movdiri", true) 1103 .Case("movdir64b", true) 1104 .Case("mwaitx", true) 1105 .Case("pclmul", true) 1106 .Case("pconfig", true) 1107 .Case("pku", true) 1108 .Case("popcnt", true) 1109 .Case("prefetchi", true) 1110 .Case("prefetchwt1", true) 1111 .Case("prfchw", true) 1112 .Case("ptwrite", true) 1113 .Case("raoint", true) 1114 .Case("rdpid", true) 1115 .Case("rdpru", true) 1116 .Case("rdrnd", true) 1117 .Case("rdseed", true) 1118 .Case("rtm", true) 1119 .Case("sahf", true) 1120 .Case("serialize", true) 1121 .Case("sgx", true) 1122 .Case("sha", true) 1123 .Case("sha512", true) 1124 .Case("shstk", true) 1125 .Case("sm3", true) 1126 .Case("sm4", true) 1127 .Case("sse", true) 1128 .Case("sse2", true) 1129 .Case("sse3", true) 1130 .Case("ssse3", true) 1131 .Case("sse4", true) 1132 .Case("sse4.1", true) 1133 .Case("sse4.2", true) 1134 .Case("sse4a", true) 1135 .Case("tbm", true) 1136 .Case("tsxldtrk", true) 1137 .Case("uintr", true) 1138 .Case("usermsr", true) 1139 .Case("vaes", true) 1140 .Case("vpclmulqdq", true) 1141 .Case("wbnoinvd", true) 1142 .Case("waitpkg", true) 1143 .Case("x87", true) 1144 .Case("xop", true) 1145 .Case("xsave", true) 1146 .Case("xsavec", true) 1147 .Case("xsaves", true) 1148 .Case("xsaveopt", true) 1149 .Case("egpr", true) 1150 .Case("push2pop2", true) 1151 .Case("ppx", true) 1152 .Case("ndd", true) 1153 .Case("ccmp", true) 1154 .Case("cf", true) 1155 .Default(false); 1156 } 1157 1158 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1159 return llvm::StringSwitch<bool>(Feature) 1160 .Case("adx", HasADX) 1161 .Case("aes", HasAES) 1162 .Case("amx-bf16", HasAMXBF16) 1163 .Case("amx-complex", HasAMXCOMPLEX) 1164 .Case("amx-fp16", HasAMXFP16) 1165 .Case("amx-int8", HasAMXINT8) 1166 .Case("amx-tile", HasAMXTILE) 1167 .Case("avx", SSELevel >= AVX) 1168 .Case("avx10.1-256", HasAVX10_1) 1169 .Case("avx10.1-512", HasAVX10_1_512) 1170 .Case("avx2", SSELevel >= AVX2) 1171 .Case("avx512f", SSELevel >= AVX512F) 1172 .Case("avx512cd", HasAVX512CD) 1173 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1174 .Case("avx512vnni", HasAVX512VNNI) 1175 .Case("avx512bf16", HasAVX512BF16) 1176 .Case("avx512er", HasAVX512ER) 1177 .Case("avx512fp16", HasAVX512FP16) 1178 .Case("avx512pf", HasAVX512PF) 1179 .Case("avx512dq", HasAVX512DQ) 1180 .Case("avx512bitalg", HasAVX512BITALG) 1181 .Case("avx512bw", HasAVX512BW) 1182 .Case("avx512vl", HasAVX512VL) 1183 .Case("avx512vbmi", HasAVX512VBMI) 1184 .Case("avx512vbmi2", HasAVX512VBMI2) 1185 .Case("avx512ifma", HasAVX512IFMA) 1186 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1187 .Case("avxifma", HasAVXIFMA) 1188 .Case("avxneconvert", HasAVXNECONVERT) 1189 .Case("avxvnni", HasAVXVNNI) 1190 .Case("avxvnniint16", HasAVXVNNIINT16) 1191 .Case("avxvnniint8", HasAVXVNNIINT8) 1192 .Case("bmi", HasBMI) 1193 .Case("bmi2", HasBMI2) 1194 .Case("cldemote", HasCLDEMOTE) 1195 .Case("clflushopt", HasCLFLUSHOPT) 1196 .Case("clwb", HasCLWB) 1197 .Case("clzero", HasCLZERO) 1198 .Case("cmpccxadd", HasCMPCCXADD) 1199 .Case("crc32", HasCRC32) 1200 .Case("cx8", HasCX8) 1201 .Case("cx16", HasCX16) 1202 .Case("enqcmd", HasENQCMD) 1203 .Case("evex512", HasEVEX512) 1204 .Case("f16c", HasF16C) 1205 .Case("fma", HasFMA) 1206 .Case("fma4", XOPLevel >= FMA4) 1207 .Case("fsgsbase", HasFSGSBASE) 1208 .Case("fxsr", HasFXSR) 1209 .Case("gfni", HasGFNI) 1210 .Case("hreset", HasHRESET) 1211 .Case("invpcid", HasINVPCID) 1212 .Case("kl", HasKL) 1213 .Case("widekl", HasWIDEKL) 1214 .Case("lwp", HasLWP) 1215 .Case("lzcnt", HasLZCNT) 1216 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1217 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1218 .Case("mmx", MMX3DNowLevel >= MMX) 1219 .Case("movbe", HasMOVBE) 1220 .Case("movdiri", HasMOVDIRI) 1221 .Case("movdir64b", HasMOVDIR64B) 1222 .Case("mwaitx", HasMWAITX) 1223 .Case("pclmul", HasPCLMUL) 1224 .Case("pconfig", HasPCONFIG) 1225 .Case("pku", HasPKU) 1226 .Case("popcnt", HasPOPCNT) 1227 .Case("prefetchi", HasPREFETCHI) 1228 .Case("prefetchwt1", HasPREFETCHWT1) 1229 .Case("prfchw", HasPRFCHW) 1230 .Case("ptwrite", HasPTWRITE) 1231 .Case("raoint", HasRAOINT) 1232 .Case("rdpid", HasRDPID) 1233 .Case("rdpru", HasRDPRU) 1234 .Case("rdrnd", HasRDRND) 1235 .Case("rdseed", HasRDSEED) 1236 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1237 .Case("rtm", HasRTM) 1238 .Case("sahf", HasLAHFSAHF) 1239 .Case("serialize", HasSERIALIZE) 1240 .Case("sgx", HasSGX) 1241 .Case("sha", HasSHA) 1242 .Case("sha512", HasSHA512) 1243 .Case("shstk", HasSHSTK) 1244 .Case("sm3", HasSM3) 1245 .Case("sm4", HasSM4) 1246 .Case("sse", SSELevel >= SSE1) 1247 .Case("sse2", SSELevel >= SSE2) 1248 .Case("sse3", SSELevel >= SSE3) 1249 .Case("ssse3", SSELevel >= SSSE3) 1250 .Case("sse4.1", SSELevel >= SSE41) 1251 .Case("sse4.2", SSELevel >= SSE42) 1252 .Case("sse4a", XOPLevel >= SSE4A) 1253 .Case("tbm", HasTBM) 1254 .Case("tsxldtrk", HasTSXLDTRK) 1255 .Case("uintr", HasUINTR) 1256 .Case("usermsr", HasUSERMSR) 1257 .Case("vaes", HasVAES) 1258 .Case("vpclmulqdq", HasVPCLMULQDQ) 1259 .Case("wbnoinvd", HasWBNOINVD) 1260 .Case("waitpkg", HasWAITPKG) 1261 .Case("x86", true) 1262 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1263 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1264 .Case("x87", HasX87) 1265 .Case("xop", XOPLevel >= XOP) 1266 .Case("xsave", HasXSAVE) 1267 .Case("xsavec", HasXSAVEC) 1268 .Case("xsaves", HasXSAVES) 1269 .Case("xsaveopt", HasXSAVEOPT) 1270 .Case("fullbf16", HasFullBFloat16) 1271 .Case("egpr", HasEGPR) 1272 .Case("push2pop2", HasPush2Pop2) 1273 .Case("ppx", HasPPX) 1274 .Case("ndd", HasNDD) 1275 .Case("ccmp", HasCCMP) 1276 .Case("cf", HasCF) 1277 .Default(false); 1278 } 1279 1280 // We can't use a generic validation scheme for the features accepted here 1281 // versus subtarget features accepted in the target attribute because the 1282 // bitfield structure that's initialized in the runtime only supports the 1283 // below currently rather than the full range of subtarget features. (See 1284 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1285 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1286 return llvm::StringSwitch<bool>(FeatureStr) 1287 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1288 #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true) 1289 #include "llvm/TargetParser/X86TargetParser.def" 1290 .Default(false); 1291 } 1292 1293 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1294 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1295 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1296 .Case(STR, llvm::X86::FEATURE_##ENUM) 1297 1298 #include "llvm/TargetParser/X86TargetParser.def" 1299 ; 1300 // Note, this function should only be used after ensuring the value is 1301 // correct, so it asserts if the value is out of range. 1302 } 1303 1304 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1305 // Valid CPUs have a 'key feature' that compares just better than its key 1306 // feature. 1307 using namespace llvm::X86; 1308 CPUKind Kind = parseArchX86(Name); 1309 if (Kind != CK_None) { 1310 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1311 return (getFeaturePriority(KeyFeature) << 1) + 1; 1312 } 1313 1314 // Now we know we have a feature, so get its priority and shift it a few so 1315 // that we have sufficient room for the CPUs (above). 1316 return getFeaturePriority(getFeature(Name)) << 1; 1317 } 1318 1319 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1320 return llvm::X86::validateCPUSpecificCPUDispatch(Name); 1321 } 1322 1323 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1324 return llvm::X86::getCPUDispatchMangling(Name); 1325 } 1326 1327 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1328 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1329 SmallVector<StringRef, 32> TargetCPUFeatures; 1330 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true); 1331 for (auto &F : TargetCPUFeatures) 1332 Features.push_back(F); 1333 } 1334 1335 // We can't use a generic validation scheme for the cpus accepted here 1336 // versus subtarget cpus accepted in the target attribute because the 1337 // variables intitialized by the runtime only support the below currently 1338 // rather than the full range of cpus. 1339 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1340 return llvm::StringSwitch<bool>(FeatureStr) 1341 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1342 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1343 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1344 #define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1345 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1346 #include "llvm/TargetParser/X86TargetParser.def" 1347 .Default(false); 1348 } 1349 1350 static unsigned matchAsmCCConstraint(const char *Name) { 1351 auto RV = llvm::StringSwitch<unsigned>(Name) 1352 .Case("@cca", 4) 1353 .Case("@ccae", 5) 1354 .Case("@ccb", 4) 1355 .Case("@ccbe", 5) 1356 .Case("@ccc", 4) 1357 .Case("@cce", 4) 1358 .Case("@ccz", 4) 1359 .Case("@ccg", 4) 1360 .Case("@ccge", 5) 1361 .Case("@ccl", 4) 1362 .Case("@ccle", 5) 1363 .Case("@ccna", 5) 1364 .Case("@ccnae", 6) 1365 .Case("@ccnb", 5) 1366 .Case("@ccnbe", 6) 1367 .Case("@ccnc", 5) 1368 .Case("@ccne", 5) 1369 .Case("@ccnz", 5) 1370 .Case("@ccng", 5) 1371 .Case("@ccnge", 6) 1372 .Case("@ccnl", 5) 1373 .Case("@ccnle", 6) 1374 .Case("@ccno", 5) 1375 .Case("@ccnp", 5) 1376 .Case("@ccns", 5) 1377 .Case("@cco", 4) 1378 .Case("@ccp", 4) 1379 .Case("@ccs", 4) 1380 .Default(0); 1381 return RV; 1382 } 1383 1384 bool X86TargetInfo::validateAsmConstraint( 1385 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1386 switch (*Name) { 1387 default: 1388 return false; 1389 // Constant constraints. 1390 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1391 // instructions. 1392 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1393 // x86_64 instructions. 1394 case 's': 1395 Info.setRequiresImmediate(); 1396 return true; 1397 case 'I': 1398 Info.setRequiresImmediate(0, 31); 1399 return true; 1400 case 'J': 1401 Info.setRequiresImmediate(0, 63); 1402 return true; 1403 case 'K': 1404 Info.setRequiresImmediate(-128, 127); 1405 return true; 1406 case 'L': 1407 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1408 return true; 1409 case 'M': 1410 Info.setRequiresImmediate(0, 3); 1411 return true; 1412 case 'N': 1413 Info.setRequiresImmediate(0, 255); 1414 return true; 1415 case 'O': 1416 Info.setRequiresImmediate(0, 127); 1417 return true; 1418 // Register constraints. 1419 case 'Y': // 'Y' is the first character for several 2-character constraints. 1420 // Shift the pointer to the second character of the constraint. 1421 Name++; 1422 switch (*Name) { 1423 default: 1424 return false; 1425 case 'z': // First SSE register. 1426 case '2': 1427 case 't': // Any SSE register, when SSE2 is enabled. 1428 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1429 case 'm': // Any MMX register, when inter-unit moves enabled. 1430 case 'k': // AVX512 arch mask registers: k1-k7. 1431 Info.setAllowsRegister(); 1432 return true; 1433 } 1434 case 'f': // Any x87 floating point stack register. 1435 // Constraint 'f' cannot be used for output operands. 1436 if (Info.ConstraintStr[0] == '=') 1437 return false; 1438 Info.setAllowsRegister(); 1439 return true; 1440 case 'a': // eax. 1441 case 'b': // ebx. 1442 case 'c': // ecx. 1443 case 'd': // edx. 1444 case 'S': // esi. 1445 case 'D': // edi. 1446 case 'A': // edx:eax. 1447 case 't': // Top of floating point stack. 1448 case 'u': // Second from top of floating point stack. 1449 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1450 case 'y': // Any MMX register. 1451 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1452 case 'x': // Any SSE register. 1453 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1454 // for intermideate k reg operations). 1455 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1456 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1457 case 'l': // "Index" registers: any general register that can be used as an 1458 // index in a base+index memory access. 1459 Info.setAllowsRegister(); 1460 return true; 1461 // Floating point constant constraints. 1462 case 'C': // SSE floating point constant. 1463 case 'G': // x87 floating point constant. 1464 return true; 1465 case '@': 1466 // CC condition changes. 1467 if (auto Len = matchAsmCCConstraint(Name)) { 1468 Name += Len - 1; 1469 Info.setAllowsRegister(); 1470 return true; 1471 } 1472 return false; 1473 } 1474 } 1475 1476 // Below is based on the following information: 1477 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1478 // | Processor Name | Cache Line Size (Bytes) | Source | 1479 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1480 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1481 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1482 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1483 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1484 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1485 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1486 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1487 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1488 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1489 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1490 // | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1491 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1492 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1493 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1494 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1495 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1496 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1497 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1498 std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1499 using namespace llvm::X86; 1500 switch (CPU) { 1501 // i386 1502 case CK_i386: 1503 // i486 1504 case CK_i486: 1505 case CK_WinChipC6: 1506 case CK_WinChip2: 1507 case CK_C3: 1508 // Lakemont 1509 case CK_Lakemont: 1510 return 16; 1511 1512 // i586 1513 case CK_i586: 1514 case CK_Pentium: 1515 case CK_PentiumMMX: 1516 // i686 1517 case CK_PentiumPro: 1518 case CK_i686: 1519 case CK_Pentium2: 1520 case CK_Pentium3: 1521 case CK_PentiumM: 1522 case CK_C3_2: 1523 // K6 1524 case CK_K6: 1525 case CK_K6_2: 1526 case CK_K6_3: 1527 // Geode 1528 case CK_Geode: 1529 return 32; 1530 1531 // Netburst 1532 case CK_Pentium4: 1533 case CK_Prescott: 1534 case CK_Nocona: 1535 // Atom 1536 case CK_Bonnell: 1537 case CK_Silvermont: 1538 case CK_Goldmont: 1539 case CK_GoldmontPlus: 1540 case CK_Tremont: 1541 case CK_Gracemont: 1542 1543 case CK_Westmere: 1544 case CK_SandyBridge: 1545 case CK_IvyBridge: 1546 case CK_Haswell: 1547 case CK_Broadwell: 1548 case CK_SkylakeClient: 1549 case CK_SkylakeServer: 1550 case CK_Cascadelake: 1551 case CK_Nehalem: 1552 case CK_Cooperlake: 1553 case CK_Cannonlake: 1554 case CK_Tigerlake: 1555 case CK_SapphireRapids: 1556 case CK_IcelakeClient: 1557 case CK_Rocketlake: 1558 case CK_IcelakeServer: 1559 case CK_Alderlake: 1560 case CK_Raptorlake: 1561 case CK_Meteorlake: 1562 case CK_Arrowlake: 1563 case CK_ArrowlakeS: 1564 case CK_Lunarlake: 1565 case CK_Pantherlake: 1566 case CK_Sierraforest: 1567 case CK_Grandridge: 1568 case CK_Graniterapids: 1569 case CK_GraniterapidsD: 1570 case CK_Emeraldrapids: 1571 case CK_Clearwaterforest: 1572 case CK_KNL: 1573 case CK_KNM: 1574 // K7 1575 case CK_Athlon: 1576 case CK_AthlonXP: 1577 // K8 1578 case CK_K8: 1579 case CK_K8SSE3: 1580 case CK_AMDFAM10: 1581 // Bobcat 1582 case CK_BTVER1: 1583 case CK_BTVER2: 1584 // Bulldozer 1585 case CK_BDVER1: 1586 case CK_BDVER2: 1587 case CK_BDVER3: 1588 case CK_BDVER4: 1589 // Zen 1590 case CK_ZNVER1: 1591 case CK_ZNVER2: 1592 case CK_ZNVER3: 1593 case CK_ZNVER4: 1594 // Deprecated 1595 case CK_x86_64: 1596 case CK_x86_64_v2: 1597 case CK_x86_64_v3: 1598 case CK_x86_64_v4: 1599 case CK_Yonah: 1600 case CK_Penryn: 1601 case CK_Core2: 1602 return 64; 1603 1604 // The following currently have unknown cache line sizes (but they are probably all 64): 1605 // Core 1606 case CK_None: 1607 return std::nullopt; 1608 } 1609 llvm_unreachable("Unknown CPU kind"); 1610 } 1611 1612 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1613 StringRef Constraint, 1614 unsigned Size) const { 1615 // Strip off constraint modifiers. 1616 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1617 Constraint = Constraint.substr(1); 1618 1619 return validateOperandSize(FeatureMap, Constraint, Size); 1620 } 1621 1622 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1623 StringRef Constraint, 1624 unsigned Size) const { 1625 return validateOperandSize(FeatureMap, Constraint, Size); 1626 } 1627 1628 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1629 StringRef Constraint, 1630 unsigned Size) const { 1631 switch (Constraint[0]) { 1632 default: 1633 break; 1634 case 'k': 1635 // Registers k0-k7 (AVX512) size limit is 64 bit. 1636 case 'y': 1637 return Size <= 64; 1638 case 'f': 1639 case 't': 1640 case 'u': 1641 return Size <= 128; 1642 case 'Y': 1643 // 'Y' is the first character for several 2-character constraints. 1644 switch (Constraint[1]) { 1645 default: 1646 return false; 1647 case 'm': 1648 // 'Ym' is synonymous with 'y'. 1649 case 'k': 1650 return Size <= 64; 1651 case 'z': 1652 // XMM0/YMM/ZMM0 1653 if (hasFeatureEnabled(FeatureMap, "avx512f") && 1654 hasFeatureEnabled(FeatureMap, "evex512")) 1655 // ZMM0 can be used if target supports AVX512F and EVEX512 is set. 1656 return Size <= 512U; 1657 else if (hasFeatureEnabled(FeatureMap, "avx")) 1658 // YMM0 can be used if target supports AVX. 1659 return Size <= 256U; 1660 else if (hasFeatureEnabled(FeatureMap, "sse")) 1661 return Size <= 128U; 1662 return false; 1663 case 'i': 1664 case 't': 1665 case '2': 1666 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1667 if (SSELevel < SSE2) 1668 return false; 1669 break; 1670 } 1671 break; 1672 case 'v': 1673 case 'x': 1674 if (hasFeatureEnabled(FeatureMap, "avx512f") && 1675 hasFeatureEnabled(FeatureMap, "evex512")) 1676 // 512-bit zmm registers can be used if target supports AVX512F and 1677 // EVEX512 is set. 1678 return Size <= 512U; 1679 else if (hasFeatureEnabled(FeatureMap, "avx")) 1680 // 256-bit ymm registers can be used if target supports AVX. 1681 return Size <= 256U; 1682 return Size <= 128U; 1683 1684 } 1685 1686 return true; 1687 } 1688 1689 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1690 switch (*Constraint) { 1691 case '@': 1692 if (auto Len = matchAsmCCConstraint(Constraint)) { 1693 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1694 Constraint += Len - 1; 1695 return Converted; 1696 } 1697 return std::string(1, *Constraint); 1698 case 'a': 1699 return std::string("{ax}"); 1700 case 'b': 1701 return std::string("{bx}"); 1702 case 'c': 1703 return std::string("{cx}"); 1704 case 'd': 1705 return std::string("{dx}"); 1706 case 'S': 1707 return std::string("{si}"); 1708 case 'D': 1709 return std::string("{di}"); 1710 case 'p': // Keep 'p' constraint (address). 1711 return std::string("p"); 1712 case 't': // top of floating point stack. 1713 return std::string("{st}"); 1714 case 'u': // second from top of floating point stack. 1715 return std::string("{st(1)}"); // second from top of floating point stack. 1716 case 'Y': 1717 switch (Constraint[1]) { 1718 default: 1719 // Break from inner switch and fall through (copy single char), 1720 // continue parsing after copying the current constraint into 1721 // the return string. 1722 break; 1723 case 'k': 1724 case 'm': 1725 case 'i': 1726 case 't': 1727 case 'z': 1728 case '2': 1729 // "^" hints llvm that this is a 2 letter constraint. 1730 // "Constraint++" is used to promote the string iterator 1731 // to the next constraint. 1732 return std::string("^") + std::string(Constraint++, 2); 1733 } 1734 [[fallthrough]]; 1735 default: 1736 return std::string(1, *Constraint); 1737 } 1738 } 1739 1740 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1741 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1742 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1743 } 1744 1745 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1746 llvm::X86::fillValidTuneCPUList(Values); 1747 } 1748 1749 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1750 return llvm::ArrayRef(GCCRegNames); 1751 } 1752 1753 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1754 return llvm::ArrayRef(AddlRegNames); 1755 } 1756 1757 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1758 return llvm::ArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1759 Builtin::FirstTSBuiltin + 1); 1760 } 1761 1762 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1763 return llvm::ArrayRef(BuiltinInfoX86, 1764 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1765 } 1766