1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 156 Features["xsave"] = true; 157 158 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 159 I = Features.find("sse4.2"); 160 if (I != Features.end() && I->getValue() && 161 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 162 Features["crc32"] = true; 163 164 return true; 165 } 166 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 168 StringRef Name, bool Enabled) const { 169 if (Name == "sse4") { 170 // We can get here via the __target__ attribute since that's not controlled 171 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 172 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 173 // disabled. 174 if (Enabled) 175 Name = "sse4.2"; 176 else 177 Name = "sse4.1"; 178 } 179 180 Features[Name] = Enabled; 181 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 182 } 183 184 /// handleTargetFeatures - Perform initialization based on the user 185 /// configured set of features. 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 187 DiagnosticsEngine &Diags) { 188 for (const auto &Feature : Features) { 189 if (Feature[0] != '+') 190 continue; 191 192 if (Feature == "+aes") { 193 HasAES = true; 194 } else if (Feature == "+vaes") { 195 HasVAES = true; 196 } else if (Feature == "+pclmul") { 197 HasPCLMUL = true; 198 } else if (Feature == "+vpclmulqdq") { 199 HasVPCLMULQDQ = true; 200 } else if (Feature == "+lzcnt") { 201 HasLZCNT = true; 202 } else if (Feature == "+rdrnd") { 203 HasRDRND = true; 204 } else if (Feature == "+fsgsbase") { 205 HasFSGSBASE = true; 206 } else if (Feature == "+bmi") { 207 HasBMI = true; 208 } else if (Feature == "+bmi2") { 209 HasBMI2 = true; 210 } else if (Feature == "+popcnt") { 211 HasPOPCNT = true; 212 } else if (Feature == "+rtm") { 213 HasRTM = true; 214 } else if (Feature == "+prfchw") { 215 HasPRFCHW = true; 216 } else if (Feature == "+rdseed") { 217 HasRDSEED = true; 218 } else if (Feature == "+adx") { 219 HasADX = true; 220 } else if (Feature == "+tbm") { 221 HasTBM = true; 222 } else if (Feature == "+lwp") { 223 HasLWP = true; 224 } else if (Feature == "+fma") { 225 HasFMA = true; 226 } else if (Feature == "+f16c") { 227 HasF16C = true; 228 } else if (Feature == "+gfni") { 229 HasGFNI = true; 230 } else if (Feature == "+avx512cd") { 231 HasAVX512CD = true; 232 } else if (Feature == "+avx512vpopcntdq") { 233 HasAVX512VPOPCNTDQ = true; 234 } else if (Feature == "+avx512vnni") { 235 HasAVX512VNNI = true; 236 } else if (Feature == "+avx512bf16") { 237 HasAVX512BF16 = true; 238 } else if (Feature == "+avx512er") { 239 HasAVX512ER = true; 240 } else if (Feature == "+avx512fp16") { 241 HasAVX512FP16 = true; 242 } else if (Feature == "+avx512pf") { 243 HasAVX512PF = true; 244 HasLegalHalfType = true; 245 } else if (Feature == "+avx512dq") { 246 HasAVX512DQ = true; 247 } else if (Feature == "+avx512bitalg") { 248 HasAVX512BITALG = true; 249 } else if (Feature == "+avx512bw") { 250 HasAVX512BW = true; 251 } else if (Feature == "+avx512vl") { 252 HasAVX512VL = true; 253 } else if (Feature == "+avx512vbmi") { 254 HasAVX512VBMI = true; 255 } else if (Feature == "+avx512vbmi2") { 256 HasAVX512VBMI2 = true; 257 } else if (Feature == "+avx512ifma") { 258 HasAVX512IFMA = true; 259 } else if (Feature == "+avx512vp2intersect") { 260 HasAVX512VP2INTERSECT = true; 261 } else if (Feature == "+sha") { 262 HasSHA = true; 263 } else if (Feature == "+shstk") { 264 HasSHSTK = true; 265 } else if (Feature == "+movbe") { 266 HasMOVBE = true; 267 } else if (Feature == "+sgx") { 268 HasSGX = true; 269 } else if (Feature == "+cx8") { 270 HasCX8 = true; 271 } else if (Feature == "+cx16") { 272 HasCX16 = true; 273 } else if (Feature == "+fxsr") { 274 HasFXSR = true; 275 } else if (Feature == "+xsave") { 276 HasXSAVE = true; 277 } else if (Feature == "+xsaveopt") { 278 HasXSAVEOPT = true; 279 } else if (Feature == "+xsavec") { 280 HasXSAVEC = true; 281 } else if (Feature == "+xsaves") { 282 HasXSAVES = true; 283 } else if (Feature == "+mwaitx") { 284 HasMWAITX = true; 285 } else if (Feature == "+pku") { 286 HasPKU = true; 287 } else if (Feature == "+clflushopt") { 288 HasCLFLUSHOPT = true; 289 } else if (Feature == "+clwb") { 290 HasCLWB = true; 291 } else if (Feature == "+wbnoinvd") { 292 HasWBNOINVD = true; 293 } else if (Feature == "+prefetchwt1") { 294 HasPREFETCHWT1 = true; 295 } else if (Feature == "+clzero") { 296 HasCLZERO = true; 297 } else if (Feature == "+cldemote") { 298 HasCLDEMOTE = true; 299 } else if (Feature == "+rdpid") { 300 HasRDPID = true; 301 } else if (Feature == "+kl") { 302 HasKL = true; 303 } else if (Feature == "+widekl") { 304 HasWIDEKL = true; 305 } else if (Feature == "+retpoline-external-thunk") { 306 HasRetpolineExternalThunk = true; 307 } else if (Feature == "+sahf") { 308 HasLAHFSAHF = true; 309 } else if (Feature == "+waitpkg") { 310 HasWAITPKG = true; 311 } else if (Feature == "+movdiri") { 312 HasMOVDIRI = true; 313 } else if (Feature == "+movdir64b") { 314 HasMOVDIR64B = true; 315 } else if (Feature == "+pconfig") { 316 HasPCONFIG = true; 317 } else if (Feature == "+ptwrite") { 318 HasPTWRITE = true; 319 } else if (Feature == "+invpcid") { 320 HasINVPCID = true; 321 } else if (Feature == "+enqcmd") { 322 HasENQCMD = true; 323 } else if (Feature == "+hreset") { 324 HasHRESET = true; 325 } else if (Feature == "+amx-bf16") { 326 HasAMXBF16 = true; 327 } else if (Feature == "+amx-int8") { 328 HasAMXINT8 = true; 329 } else if (Feature == "+amx-tile") { 330 HasAMXTILE = true; 331 } else if (Feature == "+avxvnni") { 332 HasAVXVNNI = true; 333 } else if (Feature == "+serialize") { 334 HasSERIALIZE = true; 335 } else if (Feature == "+tsxldtrk") { 336 HasTSXLDTRK = true; 337 } else if (Feature == "+uintr") { 338 HasUINTR = true; 339 } else if (Feature == "+crc32") { 340 HasCRC32 = true; 341 } else if (Feature == "+x87") { 342 HasX87 = true; 343 } 344 345 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 346 .Case("+avx512f", AVX512F) 347 .Case("+avx2", AVX2) 348 .Case("+avx", AVX) 349 .Case("+sse4.2", SSE42) 350 .Case("+sse4.1", SSE41) 351 .Case("+ssse3", SSSE3) 352 .Case("+sse3", SSE3) 353 .Case("+sse2", SSE2) 354 .Case("+sse", SSE1) 355 .Default(NoSSE); 356 SSELevel = std::max(SSELevel, Level); 357 358 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 359 .Case("+3dnowa", AMD3DNowAthlon) 360 .Case("+3dnow", AMD3DNow) 361 .Case("+mmx", MMX) 362 .Default(NoMMX3DNow); 363 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 364 365 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 366 .Case("+xop", XOP) 367 .Case("+fma4", FMA4) 368 .Case("+sse4a", SSE4A) 369 .Default(NoXOP); 370 XOPLevel = std::max(XOPLevel, XLevel); 371 } 372 // Turn on _float16 for x86 (feature sse2) 373 HasFloat16 = SSELevel >= SSE2; 374 375 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 376 // matches the selected sse level. 377 if ((FPMath == FP_SSE && SSELevel < SSE1) || 378 (FPMath == FP_387 && SSELevel >= SSE1)) { 379 Diags.Report(diag::err_target_unsupported_fpmath) 380 << (FPMath == FP_SSE ? "sse" : "387"); 381 return false; 382 } 383 384 SimdDefaultAlign = 385 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 386 387 if (!HasX87) { 388 if (LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 389 HasLongDouble = false; 390 if (getTriple().getArch() == llvm::Triple::x86) 391 HasFPReturn = false; 392 } 393 394 return true; 395 } 396 397 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 398 /// definitions for this particular subtarget. 399 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 400 MacroBuilder &Builder) const { 401 // Inline assembly supports X86 flag outputs. 402 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 403 404 std::string CodeModel = getTargetOpts().CodeModel; 405 if (CodeModel == "default") 406 CodeModel = "small"; 407 Builder.defineMacro("__code_model_" + CodeModel + "__"); 408 409 // Target identification. 410 if (getTriple().getArch() == llvm::Triple::x86_64) { 411 Builder.defineMacro("__amd64__"); 412 Builder.defineMacro("__amd64"); 413 Builder.defineMacro("__x86_64"); 414 Builder.defineMacro("__x86_64__"); 415 if (getTriple().getArchName() == "x86_64h") { 416 Builder.defineMacro("__x86_64h"); 417 Builder.defineMacro("__x86_64h__"); 418 } 419 } else { 420 DefineStd(Builder, "i386", Opts); 421 } 422 423 Builder.defineMacro("__SEG_GS"); 424 Builder.defineMacro("__SEG_FS"); 425 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 426 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 427 428 // Subtarget options. 429 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 430 // truly should be based on -mtune options. 431 using namespace llvm::X86; 432 switch (CPU) { 433 case CK_None: 434 break; 435 case CK_i386: 436 // The rest are coming from the i386 define above. 437 Builder.defineMacro("__tune_i386__"); 438 break; 439 case CK_i486: 440 case CK_WinChipC6: 441 case CK_WinChip2: 442 case CK_C3: 443 defineCPUMacros(Builder, "i486"); 444 break; 445 case CK_PentiumMMX: 446 Builder.defineMacro("__pentium_mmx__"); 447 Builder.defineMacro("__tune_pentium_mmx__"); 448 LLVM_FALLTHROUGH; 449 case CK_i586: 450 case CK_Pentium: 451 defineCPUMacros(Builder, "i586"); 452 defineCPUMacros(Builder, "pentium"); 453 break; 454 case CK_Pentium3: 455 case CK_PentiumM: 456 Builder.defineMacro("__tune_pentium3__"); 457 LLVM_FALLTHROUGH; 458 case CK_Pentium2: 459 case CK_C3_2: 460 Builder.defineMacro("__tune_pentium2__"); 461 LLVM_FALLTHROUGH; 462 case CK_PentiumPro: 463 case CK_i686: 464 defineCPUMacros(Builder, "i686"); 465 defineCPUMacros(Builder, "pentiumpro"); 466 break; 467 case CK_Pentium4: 468 defineCPUMacros(Builder, "pentium4"); 469 break; 470 case CK_Yonah: 471 case CK_Prescott: 472 case CK_Nocona: 473 defineCPUMacros(Builder, "nocona"); 474 break; 475 case CK_Core2: 476 case CK_Penryn: 477 defineCPUMacros(Builder, "core2"); 478 break; 479 case CK_Bonnell: 480 defineCPUMacros(Builder, "atom"); 481 break; 482 case CK_Silvermont: 483 defineCPUMacros(Builder, "slm"); 484 break; 485 case CK_Goldmont: 486 defineCPUMacros(Builder, "goldmont"); 487 break; 488 case CK_GoldmontPlus: 489 defineCPUMacros(Builder, "goldmont_plus"); 490 break; 491 case CK_Tremont: 492 defineCPUMacros(Builder, "tremont"); 493 break; 494 case CK_Nehalem: 495 case CK_Westmere: 496 case CK_SandyBridge: 497 case CK_IvyBridge: 498 case CK_Haswell: 499 case CK_Broadwell: 500 case CK_SkylakeClient: 501 case CK_SkylakeServer: 502 case CK_Cascadelake: 503 case CK_Cooperlake: 504 case CK_Cannonlake: 505 case CK_IcelakeClient: 506 case CK_Rocketlake: 507 case CK_IcelakeServer: 508 case CK_Tigerlake: 509 case CK_SapphireRapids: 510 case CK_Alderlake: 511 // FIXME: Historically, we defined this legacy name, it would be nice to 512 // remove it at some point. We've never exposed fine-grained names for 513 // recent primary x86 CPUs, and we should keep it that way. 514 defineCPUMacros(Builder, "corei7"); 515 break; 516 case CK_KNL: 517 defineCPUMacros(Builder, "knl"); 518 break; 519 case CK_KNM: 520 break; 521 case CK_Lakemont: 522 defineCPUMacros(Builder, "i586", /*Tuning*/false); 523 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 524 Builder.defineMacro("__tune_lakemont__"); 525 break; 526 case CK_K6_2: 527 Builder.defineMacro("__k6_2__"); 528 Builder.defineMacro("__tune_k6_2__"); 529 LLVM_FALLTHROUGH; 530 case CK_K6_3: 531 if (CPU != CK_K6_2) { // In case of fallthrough 532 // FIXME: GCC may be enabling these in cases where some other k6 533 // architecture is specified but -m3dnow is explicitly provided. The 534 // exact semantics need to be determined and emulated here. 535 Builder.defineMacro("__k6_3__"); 536 Builder.defineMacro("__tune_k6_3__"); 537 } 538 LLVM_FALLTHROUGH; 539 case CK_K6: 540 defineCPUMacros(Builder, "k6"); 541 break; 542 case CK_Athlon: 543 case CK_AthlonXP: 544 defineCPUMacros(Builder, "athlon"); 545 if (SSELevel != NoSSE) { 546 Builder.defineMacro("__athlon_sse__"); 547 Builder.defineMacro("__tune_athlon_sse__"); 548 } 549 break; 550 case CK_K8: 551 case CK_K8SSE3: 552 case CK_x86_64: 553 defineCPUMacros(Builder, "k8"); 554 break; 555 case CK_x86_64_v2: 556 case CK_x86_64_v3: 557 case CK_x86_64_v4: 558 break; 559 case CK_AMDFAM10: 560 defineCPUMacros(Builder, "amdfam10"); 561 break; 562 case CK_BTVER1: 563 defineCPUMacros(Builder, "btver1"); 564 break; 565 case CK_BTVER2: 566 defineCPUMacros(Builder, "btver2"); 567 break; 568 case CK_BDVER1: 569 defineCPUMacros(Builder, "bdver1"); 570 break; 571 case CK_BDVER2: 572 defineCPUMacros(Builder, "bdver2"); 573 break; 574 case CK_BDVER3: 575 defineCPUMacros(Builder, "bdver3"); 576 break; 577 case CK_BDVER4: 578 defineCPUMacros(Builder, "bdver4"); 579 break; 580 case CK_ZNVER1: 581 defineCPUMacros(Builder, "znver1"); 582 break; 583 case CK_ZNVER2: 584 defineCPUMacros(Builder, "znver2"); 585 break; 586 case CK_ZNVER3: 587 defineCPUMacros(Builder, "znver3"); 588 break; 589 case CK_Geode: 590 defineCPUMacros(Builder, "geode"); 591 break; 592 } 593 594 // Target properties. 595 Builder.defineMacro("__REGISTER_PREFIX__", ""); 596 597 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 598 // functions in glibc header files that use FP Stack inline asm which the 599 // backend can't deal with (PR879). 600 Builder.defineMacro("__NO_MATH_INLINES"); 601 602 if (HasAES) 603 Builder.defineMacro("__AES__"); 604 605 if (HasVAES) 606 Builder.defineMacro("__VAES__"); 607 608 if (HasPCLMUL) 609 Builder.defineMacro("__PCLMUL__"); 610 611 if (HasVPCLMULQDQ) 612 Builder.defineMacro("__VPCLMULQDQ__"); 613 614 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 615 // the feature flag only applies to 64-bit mode. 616 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 617 Builder.defineMacro("__LAHF_SAHF__"); 618 619 if (HasLZCNT) 620 Builder.defineMacro("__LZCNT__"); 621 622 if (HasRDRND) 623 Builder.defineMacro("__RDRND__"); 624 625 if (HasFSGSBASE) 626 Builder.defineMacro("__FSGSBASE__"); 627 628 if (HasBMI) 629 Builder.defineMacro("__BMI__"); 630 631 if (HasBMI2) 632 Builder.defineMacro("__BMI2__"); 633 634 if (HasPOPCNT) 635 Builder.defineMacro("__POPCNT__"); 636 637 if (HasRTM) 638 Builder.defineMacro("__RTM__"); 639 640 if (HasPRFCHW) 641 Builder.defineMacro("__PRFCHW__"); 642 643 if (HasRDSEED) 644 Builder.defineMacro("__RDSEED__"); 645 646 if (HasADX) 647 Builder.defineMacro("__ADX__"); 648 649 if (HasTBM) 650 Builder.defineMacro("__TBM__"); 651 652 if (HasLWP) 653 Builder.defineMacro("__LWP__"); 654 655 if (HasMWAITX) 656 Builder.defineMacro("__MWAITX__"); 657 658 if (HasMOVBE) 659 Builder.defineMacro("__MOVBE__"); 660 661 switch (XOPLevel) { 662 case XOP: 663 Builder.defineMacro("__XOP__"); 664 LLVM_FALLTHROUGH; 665 case FMA4: 666 Builder.defineMacro("__FMA4__"); 667 LLVM_FALLTHROUGH; 668 case SSE4A: 669 Builder.defineMacro("__SSE4A__"); 670 LLVM_FALLTHROUGH; 671 case NoXOP: 672 break; 673 } 674 675 if (HasFMA) 676 Builder.defineMacro("__FMA__"); 677 678 if (HasF16C) 679 Builder.defineMacro("__F16C__"); 680 681 if (HasGFNI) 682 Builder.defineMacro("__GFNI__"); 683 684 if (HasAVX512CD) 685 Builder.defineMacro("__AVX512CD__"); 686 if (HasAVX512VPOPCNTDQ) 687 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 688 if (HasAVX512VNNI) 689 Builder.defineMacro("__AVX512VNNI__"); 690 if (HasAVX512BF16) 691 Builder.defineMacro("__AVX512BF16__"); 692 if (HasAVX512ER) 693 Builder.defineMacro("__AVX512ER__"); 694 if (HasAVX512FP16) 695 Builder.defineMacro("__AVX512FP16__"); 696 if (HasAVX512PF) 697 Builder.defineMacro("__AVX512PF__"); 698 if (HasAVX512DQ) 699 Builder.defineMacro("__AVX512DQ__"); 700 if (HasAVX512BITALG) 701 Builder.defineMacro("__AVX512BITALG__"); 702 if (HasAVX512BW) 703 Builder.defineMacro("__AVX512BW__"); 704 if (HasAVX512VL) 705 Builder.defineMacro("__AVX512VL__"); 706 if (HasAVX512VBMI) 707 Builder.defineMacro("__AVX512VBMI__"); 708 if (HasAVX512VBMI2) 709 Builder.defineMacro("__AVX512VBMI2__"); 710 if (HasAVX512IFMA) 711 Builder.defineMacro("__AVX512IFMA__"); 712 if (HasAVX512VP2INTERSECT) 713 Builder.defineMacro("__AVX512VP2INTERSECT__"); 714 if (HasSHA) 715 Builder.defineMacro("__SHA__"); 716 717 if (HasFXSR) 718 Builder.defineMacro("__FXSR__"); 719 if (HasXSAVE) 720 Builder.defineMacro("__XSAVE__"); 721 if (HasXSAVEOPT) 722 Builder.defineMacro("__XSAVEOPT__"); 723 if (HasXSAVEC) 724 Builder.defineMacro("__XSAVEC__"); 725 if (HasXSAVES) 726 Builder.defineMacro("__XSAVES__"); 727 if (HasPKU) 728 Builder.defineMacro("__PKU__"); 729 if (HasCLFLUSHOPT) 730 Builder.defineMacro("__CLFLUSHOPT__"); 731 if (HasCLWB) 732 Builder.defineMacro("__CLWB__"); 733 if (HasWBNOINVD) 734 Builder.defineMacro("__WBNOINVD__"); 735 if (HasSHSTK) 736 Builder.defineMacro("__SHSTK__"); 737 if (HasSGX) 738 Builder.defineMacro("__SGX__"); 739 if (HasPREFETCHWT1) 740 Builder.defineMacro("__PREFETCHWT1__"); 741 if (HasCLZERO) 742 Builder.defineMacro("__CLZERO__"); 743 if (HasKL) 744 Builder.defineMacro("__KL__"); 745 if (HasWIDEKL) 746 Builder.defineMacro("__WIDEKL__"); 747 if (HasRDPID) 748 Builder.defineMacro("__RDPID__"); 749 if (HasCLDEMOTE) 750 Builder.defineMacro("__CLDEMOTE__"); 751 if (HasWAITPKG) 752 Builder.defineMacro("__WAITPKG__"); 753 if (HasMOVDIRI) 754 Builder.defineMacro("__MOVDIRI__"); 755 if (HasMOVDIR64B) 756 Builder.defineMacro("__MOVDIR64B__"); 757 if (HasPCONFIG) 758 Builder.defineMacro("__PCONFIG__"); 759 if (HasPTWRITE) 760 Builder.defineMacro("__PTWRITE__"); 761 if (HasINVPCID) 762 Builder.defineMacro("__INVPCID__"); 763 if (HasENQCMD) 764 Builder.defineMacro("__ENQCMD__"); 765 if (HasHRESET) 766 Builder.defineMacro("__HRESET__"); 767 if (HasAMXTILE) 768 Builder.defineMacro("__AMXTILE__"); 769 if (HasAMXINT8) 770 Builder.defineMacro("__AMXINT8__"); 771 if (HasAMXBF16) 772 Builder.defineMacro("__AMXBF16__"); 773 if (HasAVXVNNI) 774 Builder.defineMacro("__AVXVNNI__"); 775 if (HasSERIALIZE) 776 Builder.defineMacro("__SERIALIZE__"); 777 if (HasTSXLDTRK) 778 Builder.defineMacro("__TSXLDTRK__"); 779 if (HasUINTR) 780 Builder.defineMacro("__UINTR__"); 781 if (HasCRC32) 782 Builder.defineMacro("__CRC32__"); 783 784 // Each case falls through to the previous one here. 785 switch (SSELevel) { 786 case AVX512F: 787 Builder.defineMacro("__AVX512F__"); 788 LLVM_FALLTHROUGH; 789 case AVX2: 790 Builder.defineMacro("__AVX2__"); 791 LLVM_FALLTHROUGH; 792 case AVX: 793 Builder.defineMacro("__AVX__"); 794 LLVM_FALLTHROUGH; 795 case SSE42: 796 Builder.defineMacro("__SSE4_2__"); 797 LLVM_FALLTHROUGH; 798 case SSE41: 799 Builder.defineMacro("__SSE4_1__"); 800 LLVM_FALLTHROUGH; 801 case SSSE3: 802 Builder.defineMacro("__SSSE3__"); 803 LLVM_FALLTHROUGH; 804 case SSE3: 805 Builder.defineMacro("__SSE3__"); 806 LLVM_FALLTHROUGH; 807 case SSE2: 808 Builder.defineMacro("__SSE2__"); 809 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 810 LLVM_FALLTHROUGH; 811 case SSE1: 812 Builder.defineMacro("__SSE__"); 813 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 814 LLVM_FALLTHROUGH; 815 case NoSSE: 816 break; 817 } 818 819 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 820 switch (SSELevel) { 821 case AVX512F: 822 case AVX2: 823 case AVX: 824 case SSE42: 825 case SSE41: 826 case SSSE3: 827 case SSE3: 828 case SSE2: 829 Builder.defineMacro("_M_IX86_FP", Twine(2)); 830 break; 831 case SSE1: 832 Builder.defineMacro("_M_IX86_FP", Twine(1)); 833 break; 834 default: 835 Builder.defineMacro("_M_IX86_FP", Twine(0)); 836 break; 837 } 838 } 839 840 // Each case falls through to the previous one here. 841 switch (MMX3DNowLevel) { 842 case AMD3DNowAthlon: 843 Builder.defineMacro("__3dNOW_A__"); 844 LLVM_FALLTHROUGH; 845 case AMD3DNow: 846 Builder.defineMacro("__3dNOW__"); 847 LLVM_FALLTHROUGH; 848 case MMX: 849 Builder.defineMacro("__MMX__"); 850 LLVM_FALLTHROUGH; 851 case NoMMX3DNow: 852 break; 853 } 854 855 if (CPU >= CK_i486 || CPU == CK_None) { 856 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 857 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 858 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 859 } 860 if (HasCX8) 861 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 862 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 863 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 864 865 if (HasFloat128) 866 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 867 } 868 869 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 870 return llvm::StringSwitch<bool>(Name) 871 .Case("3dnow", true) 872 .Case("3dnowa", true) 873 .Case("adx", true) 874 .Case("aes", true) 875 .Case("amx-bf16", true) 876 .Case("amx-int8", true) 877 .Case("amx-tile", true) 878 .Case("avx", true) 879 .Case("avx2", true) 880 .Case("avx512f", true) 881 .Case("avx512cd", true) 882 .Case("avx512vpopcntdq", true) 883 .Case("avx512vnni", true) 884 .Case("avx512bf16", true) 885 .Case("avx512er", true) 886 .Case("avx512fp16", true) 887 .Case("avx512pf", true) 888 .Case("avx512dq", true) 889 .Case("avx512bitalg", true) 890 .Case("avx512bw", true) 891 .Case("avx512vl", true) 892 .Case("avx512vbmi", true) 893 .Case("avx512vbmi2", true) 894 .Case("avx512ifma", true) 895 .Case("avx512vp2intersect", true) 896 .Case("avxvnni", true) 897 .Case("bmi", true) 898 .Case("bmi2", true) 899 .Case("cldemote", true) 900 .Case("clflushopt", true) 901 .Case("clwb", true) 902 .Case("clzero", true) 903 .Case("crc32", true) 904 .Case("cx16", true) 905 .Case("enqcmd", true) 906 .Case("f16c", true) 907 .Case("fma", true) 908 .Case("fma4", true) 909 .Case("fsgsbase", true) 910 .Case("fxsr", true) 911 .Case("general-regs-only", true) 912 .Case("gfni", true) 913 .Case("hreset", true) 914 .Case("invpcid", true) 915 .Case("kl", true) 916 .Case("widekl", true) 917 .Case("lwp", true) 918 .Case("lzcnt", true) 919 .Case("mmx", true) 920 .Case("movbe", true) 921 .Case("movdiri", true) 922 .Case("movdir64b", true) 923 .Case("mwaitx", true) 924 .Case("pclmul", true) 925 .Case("pconfig", true) 926 .Case("pku", true) 927 .Case("popcnt", true) 928 .Case("prefetchwt1", true) 929 .Case("prfchw", true) 930 .Case("ptwrite", true) 931 .Case("rdpid", true) 932 .Case("rdrnd", true) 933 .Case("rdseed", true) 934 .Case("rtm", true) 935 .Case("sahf", true) 936 .Case("serialize", true) 937 .Case("sgx", true) 938 .Case("sha", true) 939 .Case("shstk", true) 940 .Case("sse", true) 941 .Case("sse2", true) 942 .Case("sse3", true) 943 .Case("ssse3", true) 944 .Case("sse4", true) 945 .Case("sse4.1", true) 946 .Case("sse4.2", true) 947 .Case("sse4a", true) 948 .Case("tbm", true) 949 .Case("tsxldtrk", true) 950 .Case("uintr", true) 951 .Case("vaes", true) 952 .Case("vpclmulqdq", true) 953 .Case("wbnoinvd", true) 954 .Case("waitpkg", true) 955 .Case("x87", true) 956 .Case("xop", true) 957 .Case("xsave", true) 958 .Case("xsavec", true) 959 .Case("xsaves", true) 960 .Case("xsaveopt", true) 961 .Default(false); 962 } 963 964 bool X86TargetInfo::hasFeature(StringRef Feature) const { 965 return llvm::StringSwitch<bool>(Feature) 966 .Case("adx", HasADX) 967 .Case("aes", HasAES) 968 .Case("amx-bf16", HasAMXBF16) 969 .Case("amx-int8", HasAMXINT8) 970 .Case("amx-tile", HasAMXTILE) 971 .Case("avxvnni", HasAVXVNNI) 972 .Case("avx", SSELevel >= AVX) 973 .Case("avx2", SSELevel >= AVX2) 974 .Case("avx512f", SSELevel >= AVX512F) 975 .Case("avx512cd", HasAVX512CD) 976 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 977 .Case("avx512vnni", HasAVX512VNNI) 978 .Case("avx512bf16", HasAVX512BF16) 979 .Case("avx512er", HasAVX512ER) 980 .Case("avx512fp16", HasAVX512FP16) 981 .Case("avx512pf", HasAVX512PF) 982 .Case("avx512dq", HasAVX512DQ) 983 .Case("avx512bitalg", HasAVX512BITALG) 984 .Case("avx512bw", HasAVX512BW) 985 .Case("avx512vl", HasAVX512VL) 986 .Case("avx512vbmi", HasAVX512VBMI) 987 .Case("avx512vbmi2", HasAVX512VBMI2) 988 .Case("avx512ifma", HasAVX512IFMA) 989 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 990 .Case("bmi", HasBMI) 991 .Case("bmi2", HasBMI2) 992 .Case("cldemote", HasCLDEMOTE) 993 .Case("clflushopt", HasCLFLUSHOPT) 994 .Case("clwb", HasCLWB) 995 .Case("clzero", HasCLZERO) 996 .Case("crc32", HasCRC32) 997 .Case("cx8", HasCX8) 998 .Case("cx16", HasCX16) 999 .Case("enqcmd", HasENQCMD) 1000 .Case("f16c", HasF16C) 1001 .Case("fma", HasFMA) 1002 .Case("fma4", XOPLevel >= FMA4) 1003 .Case("fsgsbase", HasFSGSBASE) 1004 .Case("fxsr", HasFXSR) 1005 .Case("gfni", HasGFNI) 1006 .Case("hreset", HasHRESET) 1007 .Case("invpcid", HasINVPCID) 1008 .Case("kl", HasKL) 1009 .Case("widekl", HasWIDEKL) 1010 .Case("lwp", HasLWP) 1011 .Case("lzcnt", HasLZCNT) 1012 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1013 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1014 .Case("mmx", MMX3DNowLevel >= MMX) 1015 .Case("movbe", HasMOVBE) 1016 .Case("movdiri", HasMOVDIRI) 1017 .Case("movdir64b", HasMOVDIR64B) 1018 .Case("mwaitx", HasMWAITX) 1019 .Case("pclmul", HasPCLMUL) 1020 .Case("pconfig", HasPCONFIG) 1021 .Case("pku", HasPKU) 1022 .Case("popcnt", HasPOPCNT) 1023 .Case("prefetchwt1", HasPREFETCHWT1) 1024 .Case("prfchw", HasPRFCHW) 1025 .Case("ptwrite", HasPTWRITE) 1026 .Case("rdpid", HasRDPID) 1027 .Case("rdrnd", HasRDRND) 1028 .Case("rdseed", HasRDSEED) 1029 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1030 .Case("rtm", HasRTM) 1031 .Case("sahf", HasLAHFSAHF) 1032 .Case("serialize", HasSERIALIZE) 1033 .Case("sgx", HasSGX) 1034 .Case("sha", HasSHA) 1035 .Case("shstk", HasSHSTK) 1036 .Case("sse", SSELevel >= SSE1) 1037 .Case("sse2", SSELevel >= SSE2) 1038 .Case("sse3", SSELevel >= SSE3) 1039 .Case("ssse3", SSELevel >= SSSE3) 1040 .Case("sse4.1", SSELevel >= SSE41) 1041 .Case("sse4.2", SSELevel >= SSE42) 1042 .Case("sse4a", XOPLevel >= SSE4A) 1043 .Case("tbm", HasTBM) 1044 .Case("tsxldtrk", HasTSXLDTRK) 1045 .Case("uintr", HasUINTR) 1046 .Case("vaes", HasVAES) 1047 .Case("vpclmulqdq", HasVPCLMULQDQ) 1048 .Case("wbnoinvd", HasWBNOINVD) 1049 .Case("waitpkg", HasWAITPKG) 1050 .Case("x86", true) 1051 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1052 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1053 .Case("x87", HasX87) 1054 .Case("xop", XOPLevel >= XOP) 1055 .Case("xsave", HasXSAVE) 1056 .Case("xsavec", HasXSAVEC) 1057 .Case("xsaves", HasXSAVES) 1058 .Case("xsaveopt", HasXSAVEOPT) 1059 .Default(false); 1060 } 1061 1062 // We can't use a generic validation scheme for the features accepted here 1063 // versus subtarget features accepted in the target attribute because the 1064 // bitfield structure that's initialized in the runtime only supports the 1065 // below currently rather than the full range of subtarget features. (See 1066 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1067 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1068 return llvm::StringSwitch<bool>(FeatureStr) 1069 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1070 #include "llvm/Support/X86TargetParser.def" 1071 .Default(false); 1072 } 1073 1074 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1075 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1076 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1077 .Case(STR, llvm::X86::FEATURE_##ENUM) 1078 1079 #include "llvm/Support/X86TargetParser.def" 1080 ; 1081 // Note, this function should only be used after ensuring the value is 1082 // correct, so it asserts if the value is out of range. 1083 } 1084 1085 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1086 // Valid CPUs have a 'key feature' that compares just better than its key 1087 // feature. 1088 using namespace llvm::X86; 1089 CPUKind Kind = parseArchX86(Name); 1090 if (Kind != CK_None) { 1091 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1092 return (getFeaturePriority(KeyFeature) << 1) + 1; 1093 } 1094 1095 // Now we know we have a feature, so get its priority and shift it a few so 1096 // that we have sufficient room for the CPUs (above). 1097 return getFeaturePriority(getFeature(Name)) << 1; 1098 } 1099 1100 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1101 return llvm::StringSwitch<bool>(Name) 1102 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1103 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1104 #include "llvm/Support/X86TargetParser.def" 1105 .Default(false); 1106 } 1107 1108 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1109 return llvm::StringSwitch<StringRef>(Name) 1110 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1111 #include "llvm/Support/X86TargetParser.def" 1112 .Default(Name); 1113 } 1114 1115 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1116 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1117 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1118 #include "llvm/Support/X86TargetParser.def" 1119 .Default(0); 1120 } 1121 1122 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1123 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1124 StringRef WholeList = 1125 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1126 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1127 #include "llvm/Support/X86TargetParser.def" 1128 .Default(""); 1129 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1130 } 1131 1132 // We can't use a generic validation scheme for the cpus accepted here 1133 // versus subtarget cpus accepted in the target attribute because the 1134 // variables intitialized by the runtime only support the below currently 1135 // rather than the full range of cpus. 1136 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1137 return llvm::StringSwitch<bool>(FeatureStr) 1138 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1139 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1140 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1141 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1142 #include "llvm/Support/X86TargetParser.def" 1143 .Default(false); 1144 } 1145 1146 static unsigned matchAsmCCConstraint(const char *&Name) { 1147 auto RV = llvm::StringSwitch<unsigned>(Name) 1148 .Case("@cca", 4) 1149 .Case("@ccae", 5) 1150 .Case("@ccb", 4) 1151 .Case("@ccbe", 5) 1152 .Case("@ccc", 4) 1153 .Case("@cce", 4) 1154 .Case("@ccz", 4) 1155 .Case("@ccg", 4) 1156 .Case("@ccge", 5) 1157 .Case("@ccl", 4) 1158 .Case("@ccle", 5) 1159 .Case("@ccna", 5) 1160 .Case("@ccnae", 6) 1161 .Case("@ccnb", 5) 1162 .Case("@ccnbe", 6) 1163 .Case("@ccnc", 5) 1164 .Case("@ccne", 5) 1165 .Case("@ccnz", 5) 1166 .Case("@ccng", 5) 1167 .Case("@ccnge", 6) 1168 .Case("@ccnl", 5) 1169 .Case("@ccnle", 6) 1170 .Case("@ccno", 5) 1171 .Case("@ccnp", 5) 1172 .Case("@ccns", 5) 1173 .Case("@cco", 4) 1174 .Case("@ccp", 4) 1175 .Case("@ccs", 4) 1176 .Default(0); 1177 return RV; 1178 } 1179 1180 bool X86TargetInfo::validateAsmConstraint( 1181 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1182 switch (*Name) { 1183 default: 1184 return false; 1185 // Constant constraints. 1186 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1187 // instructions. 1188 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1189 // x86_64 instructions. 1190 case 's': 1191 Info.setRequiresImmediate(); 1192 return true; 1193 case 'I': 1194 Info.setRequiresImmediate(0, 31); 1195 return true; 1196 case 'J': 1197 Info.setRequiresImmediate(0, 63); 1198 return true; 1199 case 'K': 1200 Info.setRequiresImmediate(-128, 127); 1201 return true; 1202 case 'L': 1203 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1204 return true; 1205 case 'M': 1206 Info.setRequiresImmediate(0, 3); 1207 return true; 1208 case 'N': 1209 Info.setRequiresImmediate(0, 255); 1210 return true; 1211 case 'O': 1212 Info.setRequiresImmediate(0, 127); 1213 return true; 1214 // Register constraints. 1215 case 'Y': // 'Y' is the first character for several 2-character constraints. 1216 // Shift the pointer to the second character of the constraint. 1217 Name++; 1218 switch (*Name) { 1219 default: 1220 return false; 1221 case 'z': // First SSE register. 1222 case '2': 1223 case 't': // Any SSE register, when SSE2 is enabled. 1224 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1225 case 'm': // Any MMX register, when inter-unit moves enabled. 1226 case 'k': // AVX512 arch mask registers: k1-k7. 1227 Info.setAllowsRegister(); 1228 return true; 1229 } 1230 case 'f': // Any x87 floating point stack register. 1231 // Constraint 'f' cannot be used for output operands. 1232 if (Info.ConstraintStr[0] == '=') 1233 return false; 1234 Info.setAllowsRegister(); 1235 return true; 1236 case 'a': // eax. 1237 case 'b': // ebx. 1238 case 'c': // ecx. 1239 case 'd': // edx. 1240 case 'S': // esi. 1241 case 'D': // edi. 1242 case 'A': // edx:eax. 1243 case 't': // Top of floating point stack. 1244 case 'u': // Second from top of floating point stack. 1245 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1246 case 'y': // Any MMX register. 1247 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1248 case 'x': // Any SSE register. 1249 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1250 // for intermideate k reg operations). 1251 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1252 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1253 case 'l': // "Index" registers: any general register that can be used as an 1254 // index in a base+index memory access. 1255 Info.setAllowsRegister(); 1256 return true; 1257 // Floating point constant constraints. 1258 case 'C': // SSE floating point constant. 1259 case 'G': // x87 floating point constant. 1260 return true; 1261 case '@': 1262 // CC condition changes. 1263 if (auto Len = matchAsmCCConstraint(Name)) { 1264 Name += Len - 1; 1265 Info.setAllowsRegister(); 1266 return true; 1267 } 1268 return false; 1269 } 1270 } 1271 1272 // Below is based on the following information: 1273 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1274 // | Processor Name | Cache Line Size (Bytes) | Source | 1275 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1276 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1277 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1278 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1279 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1280 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1281 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1282 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1283 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1284 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1285 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1286 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1287 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1288 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1289 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1290 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1291 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1292 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1293 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1294 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1295 using namespace llvm::X86; 1296 switch (CPU) { 1297 // i386 1298 case CK_i386: 1299 // i486 1300 case CK_i486: 1301 case CK_WinChipC6: 1302 case CK_WinChip2: 1303 case CK_C3: 1304 // Lakemont 1305 case CK_Lakemont: 1306 return 16; 1307 1308 // i586 1309 case CK_i586: 1310 case CK_Pentium: 1311 case CK_PentiumMMX: 1312 // i686 1313 case CK_PentiumPro: 1314 case CK_i686: 1315 case CK_Pentium2: 1316 case CK_Pentium3: 1317 case CK_PentiumM: 1318 case CK_C3_2: 1319 // K6 1320 case CK_K6: 1321 case CK_K6_2: 1322 case CK_K6_3: 1323 // Geode 1324 case CK_Geode: 1325 return 32; 1326 1327 // Netburst 1328 case CK_Pentium4: 1329 case CK_Prescott: 1330 case CK_Nocona: 1331 // Atom 1332 case CK_Bonnell: 1333 case CK_Silvermont: 1334 case CK_Goldmont: 1335 case CK_GoldmontPlus: 1336 case CK_Tremont: 1337 1338 case CK_Westmere: 1339 case CK_SandyBridge: 1340 case CK_IvyBridge: 1341 case CK_Haswell: 1342 case CK_Broadwell: 1343 case CK_SkylakeClient: 1344 case CK_SkylakeServer: 1345 case CK_Cascadelake: 1346 case CK_Nehalem: 1347 case CK_Cooperlake: 1348 case CK_Cannonlake: 1349 case CK_Tigerlake: 1350 case CK_SapphireRapids: 1351 case CK_IcelakeClient: 1352 case CK_Rocketlake: 1353 case CK_IcelakeServer: 1354 case CK_Alderlake: 1355 case CK_KNL: 1356 case CK_KNM: 1357 // K7 1358 case CK_Athlon: 1359 case CK_AthlonXP: 1360 // K8 1361 case CK_K8: 1362 case CK_K8SSE3: 1363 case CK_AMDFAM10: 1364 // Bobcat 1365 case CK_BTVER1: 1366 case CK_BTVER2: 1367 // Bulldozer 1368 case CK_BDVER1: 1369 case CK_BDVER2: 1370 case CK_BDVER3: 1371 case CK_BDVER4: 1372 // Zen 1373 case CK_ZNVER1: 1374 case CK_ZNVER2: 1375 case CK_ZNVER3: 1376 // Deprecated 1377 case CK_x86_64: 1378 case CK_x86_64_v2: 1379 case CK_x86_64_v3: 1380 case CK_x86_64_v4: 1381 case CK_Yonah: 1382 case CK_Penryn: 1383 case CK_Core2: 1384 return 64; 1385 1386 // The following currently have unknown cache line sizes (but they are probably all 64): 1387 // Core 1388 case CK_None: 1389 return None; 1390 } 1391 llvm_unreachable("Unknown CPU kind"); 1392 } 1393 1394 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1395 StringRef Constraint, 1396 unsigned Size) const { 1397 // Strip off constraint modifiers. 1398 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1399 Constraint = Constraint.substr(1); 1400 1401 return validateOperandSize(FeatureMap, Constraint, Size); 1402 } 1403 1404 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1405 StringRef Constraint, 1406 unsigned Size) const { 1407 return validateOperandSize(FeatureMap, Constraint, Size); 1408 } 1409 1410 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1411 StringRef Constraint, 1412 unsigned Size) const { 1413 switch (Constraint[0]) { 1414 default: 1415 break; 1416 case 'k': 1417 // Registers k0-k7 (AVX512) size limit is 64 bit. 1418 case 'y': 1419 return Size <= 64; 1420 case 'f': 1421 case 't': 1422 case 'u': 1423 return Size <= 128; 1424 case 'Y': 1425 // 'Y' is the first character for several 2-character constraints. 1426 switch (Constraint[1]) { 1427 default: 1428 return false; 1429 case 'm': 1430 // 'Ym' is synonymous with 'y'. 1431 case 'k': 1432 return Size <= 64; 1433 case 'z': 1434 // XMM0/YMM/ZMM0 1435 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1436 // ZMM0 can be used if target supports AVX512F. 1437 return Size <= 512U; 1438 else if (hasFeatureEnabled(FeatureMap, "avx")) 1439 // YMM0 can be used if target supports AVX. 1440 return Size <= 256U; 1441 else if (hasFeatureEnabled(FeatureMap, "sse")) 1442 return Size <= 128U; 1443 return false; 1444 case 'i': 1445 case 't': 1446 case '2': 1447 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1448 if (SSELevel < SSE2) 1449 return false; 1450 break; 1451 } 1452 break; 1453 case 'v': 1454 case 'x': 1455 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1456 // 512-bit zmm registers can be used if target supports AVX512F. 1457 return Size <= 512U; 1458 else if (hasFeatureEnabled(FeatureMap, "avx")) 1459 // 256-bit ymm registers can be used if target supports AVX. 1460 return Size <= 256U; 1461 return Size <= 128U; 1462 1463 } 1464 1465 return true; 1466 } 1467 1468 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1469 switch (*Constraint) { 1470 case '@': 1471 if (auto Len = matchAsmCCConstraint(Constraint)) { 1472 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1473 Constraint += Len - 1; 1474 return Converted; 1475 } 1476 return std::string(1, *Constraint); 1477 case 'a': 1478 return std::string("{ax}"); 1479 case 'b': 1480 return std::string("{bx}"); 1481 case 'c': 1482 return std::string("{cx}"); 1483 case 'd': 1484 return std::string("{dx}"); 1485 case 'S': 1486 return std::string("{si}"); 1487 case 'D': 1488 return std::string("{di}"); 1489 case 'p': // address 1490 return std::string("im"); 1491 case 't': // top of floating point stack. 1492 return std::string("{st}"); 1493 case 'u': // second from top of floating point stack. 1494 return std::string("{st(1)}"); // second from top of floating point stack. 1495 case 'Y': 1496 switch (Constraint[1]) { 1497 default: 1498 // Break from inner switch and fall through (copy single char), 1499 // continue parsing after copying the current constraint into 1500 // the return string. 1501 break; 1502 case 'k': 1503 case 'm': 1504 case 'i': 1505 case 't': 1506 case 'z': 1507 case '2': 1508 // "^" hints llvm that this is a 2 letter constraint. 1509 // "Constraint++" is used to promote the string iterator 1510 // to the next constraint. 1511 return std::string("^") + std::string(Constraint++, 2); 1512 } 1513 LLVM_FALLTHROUGH; 1514 default: 1515 return std::string(1, *Constraint); 1516 } 1517 } 1518 1519 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1520 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1521 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1522 } 1523 1524 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1525 llvm::X86::fillValidTuneCPUList(Values); 1526 } 1527 1528 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1529 return llvm::makeArrayRef(GCCRegNames); 1530 } 1531 1532 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1533 return llvm::makeArrayRef(AddlRegNames); 1534 } 1535 1536 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1537 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1538 Builtin::FirstTSBuiltin + 1); 1539 } 1540 1541 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1542 return llvm::makeArrayRef(BuiltinInfoX86, 1543 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1544 } 1545