1*f3087befSAndrew Turner /* 2*f3087befSAndrew Turner * Single-precision vector sinh(x) function. 3*f3087befSAndrew Turner * 4*f3087befSAndrew Turner * Copyright (c) 2022-2024, Arm Limited. 5*f3087befSAndrew Turner * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6*f3087befSAndrew Turner */ 7*f3087befSAndrew Turner 8*f3087befSAndrew Turner #include "v_math.h" 9*f3087befSAndrew Turner #include "test_sig.h" 10*f3087befSAndrew Turner #include "test_defs.h" 11*f3087befSAndrew Turner #include "v_expm1f_inline.h" 12*f3087befSAndrew Turner 13*f3087befSAndrew Turner static const struct data 14*f3087befSAndrew Turner { 15*f3087befSAndrew Turner struct v_expm1f_data expm1f_consts; 16*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 17*f3087befSAndrew Turner uint32x4_t tiny_bound, thresh; 18*f3087befSAndrew Turner #else 19*f3087befSAndrew Turner float32x4_t oflow_bound; 20*f3087befSAndrew Turner #endif 21*f3087befSAndrew Turner } data = { 22*f3087befSAndrew Turner .expm1f_consts = V_EXPM1F_DATA, 23*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 24*f3087befSAndrew Turner /* 0x1.6a09e8p-32, below which expm1f underflows. */ 25*f3087befSAndrew Turner .tiny_bound = V4 (0x2fb504f4), 26*f3087befSAndrew Turner /* asuint(oflow_bound) - asuint(tiny_bound). */ 27*f3087befSAndrew Turner .thresh = V4 (0x12fbbbb3), 28*f3087befSAndrew Turner #else 29*f3087befSAndrew Turner /* 0x1.61814ep+6, above which expm1f helper overflows. */ 30*f3087befSAndrew Turner .oflow_bound = V4 (0x1.61814ep+6), 31*f3087befSAndrew Turner #endif 32*f3087befSAndrew Turner }; 33*f3087befSAndrew Turner 34*f3087befSAndrew Turner static float32x4_t NOINLINE VPCS_ATTR 35*f3087befSAndrew Turner special_case (float32x4_t x, float32x4_t t, float32x4_t halfsign, 36*f3087befSAndrew Turner uint32x4_t special) 37*f3087befSAndrew Turner { 38*f3087befSAndrew Turner return v_call_f32 (sinhf, x, vmulq_f32 (t, halfsign), special); 39*f3087befSAndrew Turner } 40*f3087befSAndrew Turner 41*f3087befSAndrew Turner /* Approximation for vector single-precision sinh(x) using expm1. 42*f3087befSAndrew Turner sinh(x) = (exp(x) - exp(-x)) / 2. 43*f3087befSAndrew Turner The maximum error is 2.26 ULP: 44*f3087befSAndrew Turner _ZGVnN4v_sinhf (0x1.e34a9ep-4) got 0x1.e469ep-4 45*f3087befSAndrew Turner want 0x1.e469e4p-4. */ 46*f3087befSAndrew Turner float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (sinh) (float32x4_t x) 47*f3087befSAndrew Turner { 48*f3087befSAndrew Turner const struct data *d = ptr_barrier (&data); 49*f3087befSAndrew Turner 50*f3087befSAndrew Turner uint32x4_t ix = vreinterpretq_u32_f32 (x); 51*f3087befSAndrew Turner float32x4_t ax = vabsq_f32 (x); 52*f3087befSAndrew Turner float32x4_t halfsign = vreinterpretq_f32_u32 ( 53*f3087befSAndrew Turner vbslq_u32 (v_u32 (0x80000000), ix, vreinterpretq_u32_f32 (v_f32 (0.5)))); 54*f3087befSAndrew Turner 55*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 56*f3087befSAndrew Turner uint32x4_t special = vcgeq_u32 ( 57*f3087befSAndrew Turner vsubq_u32 (vreinterpretq_u32_f32 (ax), d->tiny_bound), d->thresh); 58*f3087befSAndrew Turner ax = v_zerofy_f32 (ax, special); 59*f3087befSAndrew Turner #else 60*f3087befSAndrew Turner uint32x4_t special = vcageq_f32 (x, d->oflow_bound); 61*f3087befSAndrew Turner #endif 62*f3087befSAndrew Turner 63*f3087befSAndrew Turner /* Up to the point that expm1f overflows, we can use it to calculate sinhf 64*f3087befSAndrew Turner using a slight rearrangement of the definition of asinh. This allows us 65*f3087befSAndrew Turner to retain acceptable accuracy for very small inputs. */ 66*f3087befSAndrew Turner float32x4_t t = expm1f_inline (ax, &d->expm1f_consts); 67*f3087befSAndrew Turner t = vaddq_f32 (t, vdivq_f32 (t, vaddq_f32 (t, v_f32 (1.0)))); 68*f3087befSAndrew Turner 69*f3087befSAndrew Turner /* Fall back to the scalar variant for any lanes that should trigger an 70*f3087befSAndrew Turner exception. */ 71*f3087befSAndrew Turner if (unlikely (v_any_u32 (special))) 72*f3087befSAndrew Turner return special_case (x, t, halfsign, special); 73*f3087befSAndrew Turner 74*f3087befSAndrew Turner return vmulq_f32 (t, halfsign); 75*f3087befSAndrew Turner } 76*f3087befSAndrew Turner 77*f3087befSAndrew Turner HALF_WIDTH_ALIAS_F1 (sinh) 78*f3087befSAndrew Turner 79*f3087befSAndrew Turner TEST_SIG (V, F, 1, sinh, -10.0, 10.0) 80*f3087befSAndrew Turner TEST_ULP (V_NAME_F1 (sinh), 1.76) 81*f3087befSAndrew Turner TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (sinh), WANT_SIMD_EXCEPT) 82*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0, 0x2fb504f4, 1000) 83*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x2fb504f4, 0x42b0c0a7, 100000) 84*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x42b0c0a7, inf, 1000) 85