1*f3087befSAndrew Turner /* 2*f3087befSAndrew Turner * Single-precision vector atanh(x) function. 3*f3087befSAndrew Turner * 4*f3087befSAndrew Turner * Copyright (c) 2022-2024, Arm Limited. 5*f3087befSAndrew Turner * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6*f3087befSAndrew Turner */ 7*f3087befSAndrew Turner 8*f3087befSAndrew Turner #include "v_math.h" 9*f3087befSAndrew Turner #include "test_sig.h" 10*f3087befSAndrew Turner #include "test_defs.h" 11*f3087befSAndrew Turner #include "v_log1pf_inline.h" 12*f3087befSAndrew Turner 13*f3087befSAndrew Turner const static struct data 14*f3087befSAndrew Turner { 15*f3087befSAndrew Turner struct v_log1pf_data log1pf_consts; 16*f3087befSAndrew Turner uint32x4_t one; 17*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 18*f3087befSAndrew Turner uint32x4_t tiny_bound; 19*f3087befSAndrew Turner #endif 20*f3087befSAndrew Turner } data = { 21*f3087befSAndrew Turner .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE, 22*f3087befSAndrew Turner .one = V4 (0x3f800000), 23*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 24*f3087befSAndrew Turner /* 0x1p-12, below which atanhf(x) rounds to x. */ 25*f3087befSAndrew Turner .tiny_bound = V4 (0x39800000), 26*f3087befSAndrew Turner #endif 27*f3087befSAndrew Turner }; 28*f3087befSAndrew Turner 29*f3087befSAndrew Turner #define AbsMask v_u32 (0x7fffffff) 30*f3087befSAndrew Turner #define Half v_u32 (0x3f000000) 31*f3087befSAndrew Turner 32*f3087befSAndrew Turner static float32x4_t NOINLINE VPCS_ATTR 33*f3087befSAndrew Turner special_case (float32x4_t x, float32x4_t halfsign, float32x4_t y, 34*f3087befSAndrew Turner uint32x4_t special) 35*f3087befSAndrew Turner { 36*f3087befSAndrew Turner return v_call_f32 (atanhf, vbslq_f32 (AbsMask, x, halfsign), 37*f3087befSAndrew Turner vmulq_f32 (halfsign, y), special); 38*f3087befSAndrew Turner } 39*f3087befSAndrew Turner 40*f3087befSAndrew Turner /* Approximation for vector single-precision atanh(x) using modified log1p. 41*f3087befSAndrew Turner The maximum error is 2.93 ULP: 42*f3087befSAndrew Turner _ZGVnN4v_atanhf(0x1.f43d7p-5) got 0x1.f4dcfep-5 43*f3087befSAndrew Turner want 0x1.f4dcf8p-5. */ 44*f3087befSAndrew Turner float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (atanh) (float32x4_t x) 45*f3087befSAndrew Turner { 46*f3087befSAndrew Turner const struct data *d = ptr_barrier (&data); 47*f3087befSAndrew Turner 48*f3087befSAndrew Turner float32x4_t halfsign = vbslq_f32 (AbsMask, v_f32 (0.5), x); 49*f3087befSAndrew Turner float32x4_t ax = vabsq_f32 (x); 50*f3087befSAndrew Turner uint32x4_t iax = vreinterpretq_u32_f32 (ax); 51*f3087befSAndrew Turner 52*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 53*f3087befSAndrew Turner uint32x4_t special 54*f3087befSAndrew Turner = vorrq_u32 (vcgeq_u32 (iax, d->one), vcltq_u32 (iax, d->tiny_bound)); 55*f3087befSAndrew Turner /* Side-step special cases by setting those lanes to 0, which will trigger no 56*f3087befSAndrew Turner exceptions. These will be fixed up later. */ 57*f3087befSAndrew Turner if (unlikely (v_any_u32 (special))) 58*f3087befSAndrew Turner ax = v_zerofy_f32 (ax, special); 59*f3087befSAndrew Turner #else 60*f3087befSAndrew Turner uint32x4_t special = vcgeq_u32 (iax, d->one); 61*f3087befSAndrew Turner #endif 62*f3087befSAndrew Turner 63*f3087befSAndrew Turner float32x4_t y = vdivq_f32 (vaddq_f32 (ax, ax), 64*f3087befSAndrew Turner vsubq_f32 (vreinterpretq_f32_u32 (d->one), ax)); 65*f3087befSAndrew Turner y = log1pf_inline (y, &d->log1pf_consts); 66*f3087befSAndrew Turner 67*f3087befSAndrew Turner /* If exceptions not required, pass ax to special-case for shorter dependency 68*f3087befSAndrew Turner chain. If exceptions are required ax will have been zerofied, so have to 69*f3087befSAndrew Turner pass x. */ 70*f3087befSAndrew Turner if (unlikely (v_any_u32 (special))) 71*f3087befSAndrew Turner #if WANT_SIMD_EXCEPT 72*f3087befSAndrew Turner return special_case (x, halfsign, y, special); 73*f3087befSAndrew Turner #else 74*f3087befSAndrew Turner return special_case (ax, halfsign, y, special); 75*f3087befSAndrew Turner #endif 76*f3087befSAndrew Turner return vmulq_f32 (halfsign, y); 77*f3087befSAndrew Turner } 78*f3087befSAndrew Turner 79*f3087befSAndrew Turner HALF_WIDTH_ALIAS_F1 (atanh) 80*f3087befSAndrew Turner 81*f3087befSAndrew Turner TEST_SIG (V, F, 1, atanh, -1.0, 1.0) 82*f3087befSAndrew Turner TEST_ULP (V_NAME_F1 (atanh), 2.44) 83*f3087befSAndrew Turner TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (atanh), WANT_SIMD_EXCEPT) 84*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_F1 (atanh), 0, 0x1p-12, 500) 85*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_F1 (atanh), 0x1p-12, 1, 200000) 86*f3087befSAndrew Turner TEST_SYM_INTERVAL (V_NAME_F1 (atanh), 1, inf, 1000) 87*f3087befSAndrew Turner /* atanh is asymptotic at 1, which is the default control value - have to set 88*f3087befSAndrew Turner -c 0 specially to ensure fp exceptions are triggered correctly (choice of 89*f3087befSAndrew Turner control lane is irrelevant if fp exceptions are disabled). */ 90*f3087befSAndrew Turner TEST_CONTROL_VALUE (V_NAME_F1 (atanh), 0) 91