1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #ifndef __INCLUDE_RTE_LRU_H__ 6 #define __INCLUDE_RTE_LRU_H__ 7 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 #include <rte_config.h> 13 #ifdef RTE_ARCH_X86_64 14 #include "rte_lru_x86.h" 15 #elif defined(RTE_ARCH_ARM64) 16 #include "rte_lru_arm64.h" 17 #else 18 #undef RTE_TABLE_HASH_LRU_STRATEGY 19 #define RTE_TABLE_HASH_LRU_STRATEGY 1 20 #endif 21 22 #if RTE_TABLE_HASH_LRU_STRATEGY == 0 23 24 #define lru_init(bucket) \ 25 do \ 26 bucket = bucket; \ 27 while (0) 28 29 #define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU) 30 31 #define lru_update(bucket, mru_val) \ 32 do { \ 33 bucket = bucket; \ 34 mru_val = mru_val; \ 35 } while (0) 36 37 #elif RTE_TABLE_HASH_LRU_STRATEGY == 1 38 39 #define lru_init(bucket) \ 40 do \ 41 bucket->lru_list = 0x0000000100020003LLU; \ 42 while (0) 43 44 #define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU) 45 46 #define lru_update(bucket, mru_val) \ 47 do { \ 48 uint64_t x, pos, x0, x1, x2, mask; \ 49 \ 50 x = bucket->lru_list; \ 51 \ 52 pos = 4; \ 53 if ((x >> 48) == ((uint64_t) mru_val)) \ 54 pos = 3; \ 55 \ 56 if (((x >> 32) & 0xFFFFLLU) == ((uint64_t) mru_val)) \ 57 pos = 2; \ 58 \ 59 if (((x >> 16) & 0xFFFFLLU) == ((uint64_t) mru_val)) \ 60 pos = 1; \ 61 \ 62 if ((x & 0xFFFFLLU) == ((uint64_t) mru_val)) \ 63 pos = 0; \ 64 \ 65 \ 66 pos <<= 4; \ 67 mask = (~0LLU) << pos; \ 68 x0 = x & (~mask); \ 69 x1 = (x >> 16) & mask; \ 70 x2 = (x << (48 - pos)) & (0xFFFFLLU << 48); \ 71 x = x0 | x1 | x2; \ 72 \ 73 if (pos != 64) \ 74 bucket->lru_list = x; \ 75 } while (0) 76 77 #elif (RTE_TABLE_HASH_LRU_STRATEGY == 2) || (RTE_TABLE_HASH_LRU_STRATEGY == 3) 78 79 /** 80 * These strategies are implemented in architecture specific header files. 81 */ 82 83 #else 84 85 #error "Incorrect value for RTE_TABLE_HASH_LRU_STRATEGY" 86 87 #endif 88 89 #ifdef __cplusplus 90 } 91 #endif 92 93 #endif 94