1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2023 Marvell. 3 */ 4 5 #ifndef RTE_PDCP_HDR_H 6 #define RTE_PDCP_HDR_H 7 8 /** 9 * @file 10 * 11 * PDCP-related defines 12 * 13 * Based on - ETSI TS 138 323 V17.1.0 (2022-08) 14 * https://www.etsi.org/deliver/etsi_ts/138300_138399/138323/17.01.00_60/ts_138323v170100p.pdf 15 */ 16 17 #include <rte_byteorder.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /** 24 * 4.3.1 25 * 26 * Indicate the maximum supported size of a PDCP Control PDU. 27 */ 28 #define RTE_PDCP_CTRL_PDU_SIZE_MAX 9000u 29 30 /** 31 * 6.3.4 MAC-I 32 * 33 * Indicate the size of MAC-I in PDCP PDU. 34 */ 35 #define RTE_PDCP_MAC_I_LEN 4 36 37 /** 38 * Indicate type of control information included in the corresponding PDCP 39 * Control PDU. 40 */ 41 enum rte_pdcp_ctrl_pdu_type { 42 RTE_PDCP_CTRL_PDU_TYPE_STATUS_REPORT = 0, 43 RTE_PDCP_CTRL_PDU_TYPE_ROHC_FEEDBACK = 1, 44 RTE_PDCP_CTRL_PDU_TYPE_EHC_FEEDBACK = 2, 45 RTE_PDCP_CRTL_PDU_TYPE_UDC_FEEDBACK = 3, 46 }; 47 48 /** 49 * 6.3.7 D/C 50 * 51 * This field indicates whether the corresponding PDCP PDU is a 52 * PDCP Data PDU or a PDCP Control PDU. 53 */ 54 enum rte_pdcp_pdu_type { 55 RTE_PDCP_PDU_TYPE_CTRL = 0, 56 RTE_PDCP_PDU_TYPE_DATA = 1, 57 }; 58 59 /** 60 * 6.2.2.1 Data PDU for SRBs 61 */ 62 __extension__ 63 struct rte_pdcp_cp_data_pdu_sn_12_hdr { 64 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 65 uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ 66 uint8_t r : 4; /**< Reserved */ 67 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 68 uint8_t r : 4; /**< Reserved */ 69 uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ 70 #endif 71 uint8_t sn_7_0; /**< Sequence number bits 0-7 */ 72 } __rte_packed; 73 74 /** 75 * 6.2.2.2 Data PDU for DRBs and MRBs with 12 bits PDCP SN 76 */ 77 __extension__ 78 struct rte_pdcp_up_data_pdu_sn_12_hdr { 79 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 80 uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ 81 uint8_t r : 3; /**< Reserved */ 82 uint8_t d_c : 1; /**< D/C bit */ 83 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 84 uint8_t d_c : 1; /**< D/C bit */ 85 uint8_t r : 3; /**< Reserved */ 86 uint8_t sn_11_8 : 4; /**< Sequence number bits 8-11 */ 87 #endif 88 uint8_t sn_7_0; /**< Sequence number bits 0-7 */ 89 } __rte_packed; 90 91 /** 92 * 6.2.2.3 Data PDU for DRBs and MRBs with 18 bits PDCP SN 93 */ 94 __extension__ 95 struct rte_pdcp_up_data_pdu_sn_18_hdr { 96 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 97 uint8_t sn_17_16 : 2; /**< Sequence number bits 16-17 */ 98 uint8_t r : 5; /**< Reserved */ 99 uint8_t d_c : 1; /**< D/C bit */ 100 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 101 uint8_t d_c : 1; /**< D/C bit */ 102 uint8_t r : 5; /**< Reserved */ 103 uint8_t sn_17_16 : 2; /**< Sequence number bits 16-17 */ 104 #endif 105 uint8_t sn_15_8; /**< Sequence number bits 8-15 */ 106 uint8_t sn_7_0; /**< Sequence number bits 0-7 */ 107 } __rte_packed; 108 109 /** 110 * 6.2.3.1 Control PDU for PDCP status report 111 */ 112 __extension__ 113 struct rte_pdcp_up_ctrl_pdu_hdr { 114 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 115 uint8_t r : 4; /**< Reserved */ 116 uint8_t pdu_type : 3; /**< Control PDU type */ 117 uint8_t d_c : 1; /**< D/C bit */ 118 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 119 uint8_t d_c : 1; /**< D/C bit */ 120 uint8_t pdu_type : 3; /**< Control PDU type */ 121 uint8_t r : 4; /**< Reserved */ 122 #endif 123 /** 124 * 6.3.9 FMC 125 * 126 * First Missing COUNT. This field indicates the COUNT value of the 127 * first missing PDCP SDU within the reordering window, i.e. RX_DELIV. 128 */ 129 rte_be32_t fmc; 130 /** 131 * 6.3.10 Bitmap 132 * 133 * Length: Variable. The length of the bitmap field can be 0. 134 * 135 * This field indicates which SDUs are missing and which SDUs are 136 * correctly received in the receiving PDCP entity. The bit position of 137 * Nth bit in the Bitmap is N, i.e., the bit position of the first bit 138 * in the Bitmap is 1. 139 */ 140 uint8_t bitmap[]; 141 } __rte_packed; 142 143 #ifdef __cplusplus 144 } 145 #endif 146 147 #endif /* RTE_PDCP_HDR_H */ 148