1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 NVIDIA Corporation & Affiliates 3 */ 4 5 #ifndef RTE_IB_H 6 #define RTE_IB_H 7 8 /** 9 * @file 10 * 11 * InfiniBand headers definitions 12 * 13 * The infiniBand headers are used by RoCE (RDMA over Converged Ethernet). 14 */ 15 16 #include <stdint.h> 17 18 #include <rte_byteorder.h> 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 /** 25 * InfiniBand Base Transport Header according to 26 * IB Specification Vol 1-Release-1.4. 27 */ 28 __extension__ 29 struct rte_ib_bth { 30 uint8_t opcode; /**< Opcode. */ 31 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 32 uint8_t tver:4; /**< Transport Header Version. */ 33 uint8_t padcnt:2; /**< Pad Count. */ 34 uint8_t m:1; /**< MigReq. */ 35 uint8_t se:1; /**< Solicited Event. */ 36 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 37 uint8_t se:1; /**< Solicited Event. */ 38 uint8_t m:1; /**< MigReq. */ 39 uint8_t padcnt:2; /**< Pad Count. */ 40 uint8_t tver:4; /**< Transport Header Version. */ 41 #endif 42 rte_be16_t pkey; /**< Partition key. */ 43 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 44 uint8_t rsvd0:6; /**< Reserved. */ 45 uint8_t b:1; /**< BECN. */ 46 uint8_t f:1; /**< FECN. */ 47 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 48 uint8_t f:1; /**< FECN. */ 49 uint8_t b:1; /**< BECN. */ 50 uint8_t rsvd0:6; /**< Reserved. */ 51 #endif 52 uint8_t dst_qp[3]; /**< Destination QP */ 53 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 54 uint8_t rsvd1:7; /**< Reserved. */ 55 uint8_t a:1; /**< Acknowledge Request. */ 56 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 57 uint8_t a:1; /**< Acknowledge Request. */ 58 uint8_t rsvd1:7; /**< Reserved. */ 59 #endif 60 uint8_t psn[3]; /**< Packet Sequence Number */ 61 } __rte_packed; 62 63 /** RoCEv2 default port. */ 64 #define RTE_ROCEV2_DEFAULT_PORT 4791 65 66 #ifdef __cplusplus 67 } 68 #endif 69 70 #endif /* RTE_IB_H */ 71