1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <errno.h> 6 #include <inttypes.h> 7 #include <stdbool.h> 8 #include <stdint.h> 9 #include <stdio.h> 10 #include <stdlib.h> 11 #include <string.h> 12 #include <sys/queue.h> 13 14 #include <bus_driver.h> 15 #include <rte_log.h> 16 #include <rte_interrupts.h> 17 #include <rte_kvargs.h> 18 #include <rte_memcpy.h> 19 #include <rte_common.h> 20 #include <rte_mempool.h> 21 #include <rte_malloc.h> 22 #include <rte_mbuf.h> 23 #include <rte_errno.h> 24 #include <rte_spinlock.h> 25 #include <rte_string_fns.h> 26 #include <rte_class.h> 27 #include <rte_ether.h> 28 #include <rte_telemetry.h> 29 30 #include "rte_ethdev.h" 31 #include "rte_ethdev_trace_fp.h" 32 #include "ethdev_driver.h" 33 #include "rte_flow_driver.h" 34 #include "ethdev_profile.h" 35 #include "ethdev_private.h" 36 #include "ethdev_trace.h" 37 #include "sff_telemetry.h" 38 39 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS]; 40 41 /* public fast-path API */ 42 struct rte_eth_fp_ops rte_eth_fp_ops[RTE_MAX_ETHPORTS]; 43 44 /* spinlock for add/remove Rx callbacks */ 45 static rte_spinlock_t eth_dev_rx_cb_lock = RTE_SPINLOCK_INITIALIZER; 46 47 /* spinlock for add/remove Tx callbacks */ 48 static rte_spinlock_t eth_dev_tx_cb_lock = RTE_SPINLOCK_INITIALIZER; 49 50 /* store statistics names and its offset in stats structure */ 51 struct rte_eth_xstats_name_off { 52 char name[RTE_ETH_XSTATS_NAME_SIZE]; 53 unsigned offset; 54 }; 55 56 static const struct rte_eth_xstats_name_off eth_dev_stats_strings[] = { 57 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)}, 58 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)}, 59 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)}, 60 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)}, 61 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)}, 62 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)}, 63 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)}, 64 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats, 65 rx_nombuf)}, 66 }; 67 68 #define RTE_NB_STATS RTE_DIM(eth_dev_stats_strings) 69 70 static const struct rte_eth_xstats_name_off eth_dev_rxq_stats_strings[] = { 71 {"packets", offsetof(struct rte_eth_stats, q_ipackets)}, 72 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)}, 73 {"errors", offsetof(struct rte_eth_stats, q_errors)}, 74 }; 75 76 #define RTE_NB_RXQ_STATS RTE_DIM(eth_dev_rxq_stats_strings) 77 78 static const struct rte_eth_xstats_name_off eth_dev_txq_stats_strings[] = { 79 {"packets", offsetof(struct rte_eth_stats, q_opackets)}, 80 {"bytes", offsetof(struct rte_eth_stats, q_obytes)}, 81 }; 82 #define RTE_NB_TXQ_STATS RTE_DIM(eth_dev_txq_stats_strings) 83 84 #define RTE_RX_OFFLOAD_BIT2STR(_name) \ 85 { RTE_ETH_RX_OFFLOAD_##_name, #_name } 86 87 static const struct { 88 uint64_t offload; 89 const char *name; 90 } eth_dev_rx_offload_names[] = { 91 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP), 92 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM), 93 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM), 94 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM), 95 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO), 96 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP), 97 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 98 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP), 99 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER), 100 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND), 101 RTE_RX_OFFLOAD_BIT2STR(SCATTER), 102 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP), 103 RTE_RX_OFFLOAD_BIT2STR(SECURITY), 104 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC), 105 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM), 106 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 107 RTE_RX_OFFLOAD_BIT2STR(RSS_HASH), 108 RTE_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT), 109 }; 110 111 #undef RTE_RX_OFFLOAD_BIT2STR 112 #undef RTE_ETH_RX_OFFLOAD_BIT2STR 113 114 #define RTE_TX_OFFLOAD_BIT2STR(_name) \ 115 { RTE_ETH_TX_OFFLOAD_##_name, #_name } 116 117 static const struct { 118 uint64_t offload; 119 const char *name; 120 } eth_dev_tx_offload_names[] = { 121 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT), 122 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM), 123 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM), 124 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM), 125 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM), 126 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO), 127 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO), 128 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 129 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT), 130 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO), 131 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO), 132 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO), 133 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO), 134 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT), 135 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE), 136 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS), 137 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE), 138 RTE_TX_OFFLOAD_BIT2STR(SECURITY), 139 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO), 140 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO), 141 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 142 RTE_TX_OFFLOAD_BIT2STR(SEND_ON_TIMESTAMP), 143 }; 144 145 #undef RTE_TX_OFFLOAD_BIT2STR 146 147 static const struct { 148 uint64_t offload; 149 const char *name; 150 } rte_eth_dev_capa_names[] = { 151 {RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP, "RUNTIME_RX_QUEUE_SETUP"}, 152 {RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP, "RUNTIME_TX_QUEUE_SETUP"}, 153 {RTE_ETH_DEV_CAPA_RXQ_SHARE, "RXQ_SHARE"}, 154 {RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP, "FLOW_RULE_KEEP"}, 155 {RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP, "FLOW_SHARED_OBJECT_KEEP"}, 156 }; 157 158 enum { 159 STAT_QMAP_TX = 0, 160 STAT_QMAP_RX 161 }; 162 163 static const struct { 164 enum rte_eth_hash_function algo; 165 const char *name; 166 } rte_eth_dev_rss_algo_names[] = { 167 {RTE_ETH_HASH_FUNCTION_DEFAULT, "default"}, 168 {RTE_ETH_HASH_FUNCTION_SIMPLE_XOR, "simple_xor"}, 169 {RTE_ETH_HASH_FUNCTION_TOEPLITZ, "toeplitz"}, 170 {RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ, "symmetric_toeplitz"}, 171 {RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ_SORT, "symmetric_toeplitz_sort"}, 172 }; 173 174 int 175 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str) 176 { 177 int ret; 178 struct rte_devargs devargs; 179 const char *bus_param_key; 180 char *bus_str = NULL; 181 char *cls_str = NULL; 182 int str_size; 183 184 if (iter == NULL) { 185 RTE_ETHDEV_LOG_LINE(ERR, "Cannot initialize NULL iterator"); 186 return -EINVAL; 187 } 188 189 if (devargs_str == NULL) { 190 RTE_ETHDEV_LOG_LINE(ERR, 191 "Cannot initialize iterator from NULL device description string"); 192 return -EINVAL; 193 } 194 195 memset(iter, 0, sizeof(*iter)); 196 memset(&devargs, 0, sizeof(devargs)); 197 198 /* 199 * The devargs string may use various syntaxes: 200 * - 0000:08:00.0,representor=[1-3] 201 * - pci:0000:06:00.0,representor=[0,5] 202 * - class=eth,mac=00:11:22:33:44:55 203 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z 204 */ 205 206 /* 207 * Handle pure class filter (i.e. without any bus-level argument), 208 * from future new syntax. 209 * rte_devargs_parse() is not yet supporting the new syntax, 210 * that's why this simple case is temporarily parsed here. 211 */ 212 #define iter_anybus_str "class=eth," 213 if (strncmp(devargs_str, iter_anybus_str, 214 strlen(iter_anybus_str)) == 0) { 215 iter->cls_str = devargs_str + strlen(iter_anybus_str); 216 goto end; 217 } 218 219 /* Split bus, device and parameters. */ 220 ret = rte_devargs_parse(&devargs, devargs_str); 221 if (ret != 0) 222 goto error; 223 224 /* 225 * Assume parameters of old syntax can match only at ethdev level. 226 * Extra parameters will be ignored, thanks to "+" prefix. 227 */ 228 str_size = strlen(devargs.args) + 2; 229 cls_str = malloc(str_size); 230 if (cls_str == NULL) { 231 ret = -ENOMEM; 232 goto error; 233 } 234 ret = snprintf(cls_str, str_size, "+%s", devargs.args); 235 if (ret != str_size - 1) { 236 ret = -EINVAL; 237 goto error; 238 } 239 iter->cls_str = cls_str; 240 241 iter->bus = devargs.bus; 242 if (iter->bus->dev_iterate == NULL) { 243 ret = -ENOTSUP; 244 goto error; 245 } 246 247 /* Convert bus args to new syntax for use with new API dev_iterate. */ 248 if ((strcmp(iter->bus->name, "vdev") == 0) || 249 (strcmp(iter->bus->name, "fslmc") == 0) || 250 (strcmp(iter->bus->name, "dpaa_bus") == 0)) { 251 bus_param_key = "name"; 252 } else if (strcmp(iter->bus->name, "pci") == 0) { 253 bus_param_key = "addr"; 254 } else { 255 ret = -ENOTSUP; 256 goto error; 257 } 258 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2; 259 bus_str = malloc(str_size); 260 if (bus_str == NULL) { 261 ret = -ENOMEM; 262 goto error; 263 } 264 ret = snprintf(bus_str, str_size, "%s=%s", 265 bus_param_key, devargs.name); 266 if (ret != str_size - 1) { 267 ret = -EINVAL; 268 goto error; 269 } 270 iter->bus_str = bus_str; 271 272 end: 273 iter->cls = rte_class_find_by_name("eth"); 274 rte_devargs_reset(&devargs); 275 276 rte_eth_trace_iterator_init(devargs_str); 277 278 return 0; 279 280 error: 281 if (ret == -ENOTSUP) 282 RTE_ETHDEV_LOG_LINE(ERR, "Bus %s does not support iterating.", 283 iter->bus->name); 284 rte_devargs_reset(&devargs); 285 free(bus_str); 286 free(cls_str); 287 return ret; 288 } 289 290 uint16_t 291 rte_eth_iterator_next(struct rte_dev_iterator *iter) 292 { 293 if (iter == NULL) { 294 RTE_ETHDEV_LOG_LINE(ERR, 295 "Cannot get next device from NULL iterator"); 296 return RTE_MAX_ETHPORTS; 297 } 298 299 if (iter->cls == NULL) /* invalid ethdev iterator */ 300 return RTE_MAX_ETHPORTS; 301 302 do { /* loop to try all matching rte_device */ 303 /* If not pure ethdev filter and */ 304 if (iter->bus != NULL && 305 /* not in middle of rte_eth_dev iteration, */ 306 iter->class_device == NULL) { 307 /* get next rte_device to try. */ 308 iter->device = iter->bus->dev_iterate( 309 iter->device, iter->bus_str, iter); 310 if (iter->device == NULL) 311 break; /* no more rte_device candidate */ 312 } 313 /* A device is matching bus part, need to check ethdev part. */ 314 iter->class_device = iter->cls->dev_iterate( 315 iter->class_device, iter->cls_str, iter); 316 if (iter->class_device != NULL) { 317 uint16_t id = eth_dev_to_id(iter->class_device); 318 319 rte_eth_trace_iterator_next(iter, id); 320 321 return id; /* match */ 322 } 323 } while (iter->bus != NULL); /* need to try next rte_device */ 324 325 /* No more ethdev port to iterate. */ 326 rte_eth_iterator_cleanup(iter); 327 return RTE_MAX_ETHPORTS; 328 } 329 330 void 331 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter) 332 { 333 if (iter == NULL) { 334 RTE_ETHDEV_LOG_LINE(ERR, "Cannot do clean up from NULL iterator"); 335 return; 336 } 337 338 if (iter->bus_str == NULL) 339 return; /* nothing to free in pure class filter */ 340 341 rte_eth_trace_iterator_cleanup(iter); 342 343 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */ 344 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */ 345 memset(iter, 0, sizeof(*iter)); 346 } 347 348 uint16_t 349 rte_eth_find_next(uint16_t port_id) 350 { 351 while (port_id < RTE_MAX_ETHPORTS && 352 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED) 353 port_id++; 354 355 if (port_id >= RTE_MAX_ETHPORTS) 356 return RTE_MAX_ETHPORTS; 357 358 rte_eth_trace_find_next(port_id); 359 360 return port_id; 361 } 362 363 /* 364 * Macro to iterate over all valid ports for internal usage. 365 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports. 366 */ 367 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \ 368 for (port_id = rte_eth_find_next(0); \ 369 port_id < RTE_MAX_ETHPORTS; \ 370 port_id = rte_eth_find_next(port_id + 1)) 371 372 uint16_t 373 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent) 374 { 375 port_id = rte_eth_find_next(port_id); 376 while (port_id < RTE_MAX_ETHPORTS && 377 rte_eth_devices[port_id].device != parent) 378 port_id = rte_eth_find_next(port_id + 1); 379 380 rte_eth_trace_find_next_of(port_id, parent); 381 382 return port_id; 383 } 384 385 uint16_t 386 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id) 387 { 388 uint16_t ret; 389 390 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS); 391 ret = rte_eth_find_next_of(port_id, 392 rte_eth_devices[ref_port_id].device); 393 394 rte_eth_trace_find_next_sibling(port_id, ref_port_id, ret); 395 396 return ret; 397 } 398 399 static bool 400 eth_dev_is_allocated(const struct rte_eth_dev *ethdev) 401 { 402 return ethdev->data != NULL && ethdev->data->name[0] != '\0'; 403 } 404 405 int 406 rte_eth_dev_is_valid_port(uint16_t port_id) 407 { 408 int is_valid; 409 410 if (port_id >= RTE_MAX_ETHPORTS || 411 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)) 412 is_valid = 0; 413 else 414 is_valid = 1; 415 416 rte_ethdev_trace_is_valid_port(port_id, is_valid); 417 418 return is_valid; 419 } 420 421 static int 422 eth_is_valid_owner_id(uint64_t owner_id) 423 __rte_exclusive_locks_required(rte_mcfg_ethdev_get_lock()) 424 { 425 if (owner_id == RTE_ETH_DEV_NO_OWNER || 426 eth_dev_shared_data->next_owner_id <= owner_id) 427 return 0; 428 return 1; 429 } 430 431 uint64_t 432 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id) 433 { 434 port_id = rte_eth_find_next(port_id); 435 while (port_id < RTE_MAX_ETHPORTS && 436 rte_eth_devices[port_id].data->owner.id != owner_id) 437 port_id = rte_eth_find_next(port_id + 1); 438 439 rte_eth_trace_find_next_owned_by(port_id, owner_id); 440 441 return port_id; 442 } 443 444 int 445 rte_eth_dev_owner_new(uint64_t *owner_id) 446 { 447 int ret; 448 449 if (owner_id == NULL) { 450 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get new owner ID to NULL"); 451 return -EINVAL; 452 } 453 454 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 455 456 if (eth_dev_shared_data_prepare() != NULL) { 457 *owner_id = eth_dev_shared_data->next_owner_id++; 458 eth_dev_shared_data->allocated_owners++; 459 ret = 0; 460 } else { 461 ret = -ENOMEM; 462 } 463 464 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 465 466 rte_ethdev_trace_owner_new(*owner_id, ret); 467 468 return ret; 469 } 470 471 static int 472 eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id, 473 const struct rte_eth_dev_owner *new_owner) 474 __rte_exclusive_locks_required(rte_mcfg_ethdev_get_lock()) 475 { 476 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id]; 477 struct rte_eth_dev_owner *port_owner; 478 479 if (port_id >= RTE_MAX_ETHPORTS || !eth_dev_is_allocated(ethdev)) { 480 RTE_ETHDEV_LOG_LINE(ERR, "Port ID %"PRIu16" is not allocated", 481 port_id); 482 return -ENODEV; 483 } 484 485 if (new_owner == NULL) { 486 RTE_ETHDEV_LOG_LINE(ERR, 487 "Cannot set ethdev port %u owner from NULL owner", 488 port_id); 489 return -EINVAL; 490 } 491 492 if (!eth_is_valid_owner_id(new_owner->id) && 493 !eth_is_valid_owner_id(old_owner_id)) { 494 RTE_ETHDEV_LOG_LINE(ERR, 495 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64, 496 old_owner_id, new_owner->id); 497 return -EINVAL; 498 } 499 500 port_owner = &rte_eth_devices[port_id].data->owner; 501 if (port_owner->id != old_owner_id) { 502 RTE_ETHDEV_LOG_LINE(ERR, 503 "Cannot set owner to port %u already owned by %s_%016"PRIX64, 504 port_id, port_owner->name, port_owner->id); 505 return -EPERM; 506 } 507 508 /* can not truncate (same structure) */ 509 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN); 510 511 port_owner->id = new_owner->id; 512 513 RTE_ETHDEV_LOG_LINE(DEBUG, "Port %u owner is %s_%016"PRIx64, 514 port_id, new_owner->name, new_owner->id); 515 516 return 0; 517 } 518 519 int 520 rte_eth_dev_owner_set(const uint16_t port_id, 521 const struct rte_eth_dev_owner *owner) 522 { 523 int ret; 524 525 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 526 527 if (eth_dev_shared_data_prepare() != NULL) 528 ret = eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner); 529 else 530 ret = -ENOMEM; 531 532 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 533 534 rte_ethdev_trace_owner_set(port_id, owner, ret); 535 536 return ret; 537 } 538 539 int 540 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id) 541 { 542 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner) 543 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""}; 544 int ret; 545 546 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 547 548 if (eth_dev_shared_data_prepare() != NULL) 549 ret = eth_dev_owner_set(port_id, owner_id, &new_owner); 550 else 551 ret = -ENOMEM; 552 553 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 554 555 rte_ethdev_trace_owner_unset(port_id, owner_id, ret); 556 557 return ret; 558 } 559 560 int 561 rte_eth_dev_owner_delete(const uint64_t owner_id) 562 { 563 uint16_t port_id; 564 int ret = 0; 565 566 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 567 568 if (eth_dev_shared_data_prepare() == NULL) { 569 ret = -ENOMEM; 570 } else if (eth_is_valid_owner_id(owner_id)) { 571 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { 572 struct rte_eth_dev_data *data = 573 rte_eth_devices[port_id].data; 574 if (data != NULL && data->owner.id == owner_id) 575 memset(&data->owner, 0, 576 sizeof(struct rte_eth_dev_owner)); 577 } 578 RTE_ETHDEV_LOG_LINE(NOTICE, 579 "All port owners owned by %016"PRIx64" identifier have removed", 580 owner_id); 581 eth_dev_shared_data->allocated_owners--; 582 eth_dev_shared_data_release(); 583 } else { 584 RTE_ETHDEV_LOG_LINE(ERR, 585 "Invalid owner ID=%016"PRIx64, 586 owner_id); 587 ret = -EINVAL; 588 } 589 590 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 591 592 rte_ethdev_trace_owner_delete(owner_id, ret); 593 594 return ret; 595 } 596 597 int 598 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner) 599 { 600 struct rte_eth_dev *ethdev; 601 int ret; 602 603 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 604 ethdev = &rte_eth_devices[port_id]; 605 606 if (!eth_dev_is_allocated(ethdev)) { 607 RTE_ETHDEV_LOG_LINE(ERR, "Port ID %"PRIu16" is not allocated", 608 port_id); 609 return -ENODEV; 610 } 611 612 if (owner == NULL) { 613 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u owner to NULL", 614 port_id); 615 return -EINVAL; 616 } 617 618 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 619 620 if (eth_dev_shared_data_prepare() != NULL) { 621 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner)); 622 ret = 0; 623 } else { 624 ret = -ENOMEM; 625 } 626 627 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 628 629 rte_ethdev_trace_owner_get(port_id, owner, ret); 630 631 return ret; 632 } 633 634 int 635 rte_eth_dev_socket_id(uint16_t port_id) 636 { 637 int socket_id = SOCKET_ID_ANY; 638 639 if (!rte_eth_dev_is_valid_port(port_id)) { 640 rte_errno = EINVAL; 641 } else { 642 socket_id = rte_eth_devices[port_id].data->numa_node; 643 if (socket_id == SOCKET_ID_ANY) 644 rte_errno = 0; 645 } 646 647 rte_ethdev_trace_socket_id(port_id, socket_id); 648 649 return socket_id; 650 } 651 652 void * 653 rte_eth_dev_get_sec_ctx(uint16_t port_id) 654 { 655 void *ctx; 656 657 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL); 658 ctx = rte_eth_devices[port_id].security_ctx; 659 660 rte_ethdev_trace_get_sec_ctx(port_id, ctx); 661 662 return ctx; 663 } 664 665 uint16_t 666 rte_eth_dev_count_avail(void) 667 { 668 uint16_t p; 669 uint16_t count; 670 671 count = 0; 672 673 RTE_ETH_FOREACH_DEV(p) 674 count++; 675 676 rte_ethdev_trace_count_avail(count); 677 678 return count; 679 } 680 681 uint16_t 682 rte_eth_dev_count_total(void) 683 { 684 uint16_t port, count = 0; 685 686 RTE_ETH_FOREACH_VALID_DEV(port) 687 count++; 688 689 rte_ethdev_trace_count_total(count); 690 691 return count; 692 } 693 694 int 695 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name) 696 { 697 char *tmp; 698 699 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 700 701 if (name == NULL) { 702 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u name to NULL", 703 port_id); 704 return -EINVAL; 705 } 706 707 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 708 /* shouldn't check 'rte_eth_devices[i].data', 709 * because it might be overwritten by VDEV PMD */ 710 tmp = eth_dev_shared_data->data[port_id].name; 711 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 712 713 strcpy(name, tmp); 714 715 rte_ethdev_trace_get_name_by_port(port_id, name); 716 717 return 0; 718 } 719 720 int 721 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id) 722 { 723 int ret = -ENODEV; 724 uint16_t pid; 725 726 if (name == NULL) { 727 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get port ID from NULL name"); 728 return -EINVAL; 729 } 730 731 if (port_id == NULL) { 732 RTE_ETHDEV_LOG_LINE(ERR, 733 "Cannot get port ID to NULL for %s", name); 734 return -EINVAL; 735 } 736 737 rte_spinlock_lock(rte_mcfg_ethdev_get_lock()); 738 RTE_ETH_FOREACH_VALID_DEV(pid) { 739 if (strcmp(name, eth_dev_shared_data->data[pid].name) != 0) 740 continue; 741 742 *port_id = pid; 743 rte_ethdev_trace_get_port_by_name(name, *port_id); 744 ret = 0; 745 break; 746 } 747 rte_spinlock_unlock(rte_mcfg_ethdev_get_lock()); 748 749 return ret; 750 } 751 752 int 753 eth_err(uint16_t port_id, int ret) 754 { 755 if (ret == 0) 756 return 0; 757 if (rte_eth_dev_is_removed(port_id)) 758 return -EIO; 759 return ret; 760 } 761 762 static int 763 eth_dev_validate_rx_queue(const struct rte_eth_dev *dev, uint16_t rx_queue_id) 764 { 765 uint16_t port_id; 766 767 if (rx_queue_id >= dev->data->nb_rx_queues) { 768 port_id = dev->data->port_id; 769 RTE_ETHDEV_LOG_LINE(ERR, 770 "Invalid Rx queue_id=%u of device with port_id=%u", 771 rx_queue_id, port_id); 772 return -EINVAL; 773 } 774 775 if (dev->data->rx_queues[rx_queue_id] == NULL) { 776 port_id = dev->data->port_id; 777 RTE_ETHDEV_LOG_LINE(ERR, 778 "Queue %u of device with port_id=%u has not been setup", 779 rx_queue_id, port_id); 780 return -EINVAL; 781 } 782 783 return 0; 784 } 785 786 static int 787 eth_dev_validate_tx_queue(const struct rte_eth_dev *dev, uint16_t tx_queue_id) 788 { 789 uint16_t port_id; 790 791 if (tx_queue_id >= dev->data->nb_tx_queues) { 792 port_id = dev->data->port_id; 793 RTE_ETHDEV_LOG_LINE(ERR, 794 "Invalid Tx queue_id=%u of device with port_id=%u", 795 tx_queue_id, port_id); 796 return -EINVAL; 797 } 798 799 if (dev->data->tx_queues[tx_queue_id] == NULL) { 800 port_id = dev->data->port_id; 801 RTE_ETHDEV_LOG_LINE(ERR, 802 "Queue %u of device with port_id=%u has not been setup", 803 tx_queue_id, port_id); 804 return -EINVAL; 805 } 806 807 return 0; 808 } 809 810 int 811 rte_eth_rx_queue_is_valid(uint16_t port_id, uint16_t queue_id) 812 { 813 struct rte_eth_dev *dev; 814 815 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 816 dev = &rte_eth_devices[port_id]; 817 818 return eth_dev_validate_rx_queue(dev, queue_id); 819 } 820 821 int 822 rte_eth_tx_queue_is_valid(uint16_t port_id, uint16_t queue_id) 823 { 824 struct rte_eth_dev *dev; 825 826 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 827 dev = &rte_eth_devices[port_id]; 828 829 return eth_dev_validate_tx_queue(dev, queue_id); 830 } 831 832 int 833 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id) 834 { 835 struct rte_eth_dev *dev; 836 int ret; 837 838 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 839 dev = &rte_eth_devices[port_id]; 840 841 if (!dev->data->dev_started) { 842 RTE_ETHDEV_LOG_LINE(ERR, 843 "Port %u must be started before start any queue", 844 port_id); 845 return -EINVAL; 846 } 847 848 ret = eth_dev_validate_rx_queue(dev, rx_queue_id); 849 if (ret != 0) 850 return ret; 851 852 if (*dev->dev_ops->rx_queue_start == NULL) 853 return -ENOTSUP; 854 855 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) { 856 RTE_ETHDEV_LOG_LINE(INFO, 857 "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16, 858 rx_queue_id, port_id); 859 return -EINVAL; 860 } 861 862 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 863 RTE_ETHDEV_LOG_LINE(INFO, 864 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started", 865 rx_queue_id, port_id); 866 return 0; 867 } 868 869 ret = eth_err(port_id, dev->dev_ops->rx_queue_start(dev, rx_queue_id)); 870 871 rte_ethdev_trace_rx_queue_start(port_id, rx_queue_id, ret); 872 873 return ret; 874 } 875 876 int 877 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id) 878 { 879 struct rte_eth_dev *dev; 880 int ret; 881 882 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 883 dev = &rte_eth_devices[port_id]; 884 885 ret = eth_dev_validate_rx_queue(dev, rx_queue_id); 886 if (ret != 0) 887 return ret; 888 889 if (*dev->dev_ops->rx_queue_stop == NULL) 890 return -ENOTSUP; 891 892 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) { 893 RTE_ETHDEV_LOG_LINE(INFO, 894 "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16, 895 rx_queue_id, port_id); 896 return -EINVAL; 897 } 898 899 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 900 RTE_ETHDEV_LOG_LINE(INFO, 901 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped", 902 rx_queue_id, port_id); 903 return 0; 904 } 905 906 ret = eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id)); 907 908 rte_ethdev_trace_rx_queue_stop(port_id, rx_queue_id, ret); 909 910 return ret; 911 } 912 913 int 914 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id) 915 { 916 struct rte_eth_dev *dev; 917 int ret; 918 919 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 920 dev = &rte_eth_devices[port_id]; 921 922 if (!dev->data->dev_started) { 923 RTE_ETHDEV_LOG_LINE(ERR, 924 "Port %u must be started before start any queue", 925 port_id); 926 return -EINVAL; 927 } 928 929 ret = eth_dev_validate_tx_queue(dev, tx_queue_id); 930 if (ret != 0) 931 return ret; 932 933 if (*dev->dev_ops->tx_queue_start == NULL) 934 return -ENOTSUP; 935 936 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) { 937 RTE_ETHDEV_LOG_LINE(INFO, 938 "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16, 939 tx_queue_id, port_id); 940 return -EINVAL; 941 } 942 943 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 944 RTE_ETHDEV_LOG_LINE(INFO, 945 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started", 946 tx_queue_id, port_id); 947 return 0; 948 } 949 950 ret = eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id)); 951 952 rte_ethdev_trace_tx_queue_start(port_id, tx_queue_id, ret); 953 954 return ret; 955 } 956 957 int 958 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id) 959 { 960 struct rte_eth_dev *dev; 961 int ret; 962 963 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 964 dev = &rte_eth_devices[port_id]; 965 966 ret = eth_dev_validate_tx_queue(dev, tx_queue_id); 967 if (ret != 0) 968 return ret; 969 970 if (*dev->dev_ops->tx_queue_stop == NULL) 971 return -ENOTSUP; 972 973 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) { 974 RTE_ETHDEV_LOG_LINE(INFO, 975 "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16, 976 tx_queue_id, port_id); 977 return -EINVAL; 978 } 979 980 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 981 RTE_ETHDEV_LOG_LINE(INFO, 982 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped", 983 tx_queue_id, port_id); 984 return 0; 985 } 986 987 ret = eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id)); 988 989 rte_ethdev_trace_tx_queue_stop(port_id, tx_queue_id, ret); 990 991 return ret; 992 } 993 994 uint32_t 995 rte_eth_speed_bitflag(uint32_t speed, int duplex) 996 { 997 uint32_t ret; 998 999 switch (speed) { 1000 case RTE_ETH_SPEED_NUM_10M: 1001 ret = duplex ? RTE_ETH_LINK_SPEED_10M : RTE_ETH_LINK_SPEED_10M_HD; 1002 break; 1003 case RTE_ETH_SPEED_NUM_100M: 1004 ret = duplex ? RTE_ETH_LINK_SPEED_100M : RTE_ETH_LINK_SPEED_100M_HD; 1005 break; 1006 case RTE_ETH_SPEED_NUM_1G: 1007 ret = RTE_ETH_LINK_SPEED_1G; 1008 break; 1009 case RTE_ETH_SPEED_NUM_2_5G: 1010 ret = RTE_ETH_LINK_SPEED_2_5G; 1011 break; 1012 case RTE_ETH_SPEED_NUM_5G: 1013 ret = RTE_ETH_LINK_SPEED_5G; 1014 break; 1015 case RTE_ETH_SPEED_NUM_10G: 1016 ret = RTE_ETH_LINK_SPEED_10G; 1017 break; 1018 case RTE_ETH_SPEED_NUM_20G: 1019 ret = RTE_ETH_LINK_SPEED_20G; 1020 break; 1021 case RTE_ETH_SPEED_NUM_25G: 1022 ret = RTE_ETH_LINK_SPEED_25G; 1023 break; 1024 case RTE_ETH_SPEED_NUM_40G: 1025 ret = RTE_ETH_LINK_SPEED_40G; 1026 break; 1027 case RTE_ETH_SPEED_NUM_50G: 1028 ret = RTE_ETH_LINK_SPEED_50G; 1029 break; 1030 case RTE_ETH_SPEED_NUM_56G: 1031 ret = RTE_ETH_LINK_SPEED_56G; 1032 break; 1033 case RTE_ETH_SPEED_NUM_100G: 1034 ret = RTE_ETH_LINK_SPEED_100G; 1035 break; 1036 case RTE_ETH_SPEED_NUM_200G: 1037 ret = RTE_ETH_LINK_SPEED_200G; 1038 break; 1039 case RTE_ETH_SPEED_NUM_400G: 1040 ret = RTE_ETH_LINK_SPEED_400G; 1041 break; 1042 default: 1043 ret = 0; 1044 } 1045 1046 rte_eth_trace_speed_bitflag(speed, duplex, ret); 1047 1048 return ret; 1049 } 1050 1051 const char * 1052 rte_eth_dev_rx_offload_name(uint64_t offload) 1053 { 1054 const char *name = "UNKNOWN"; 1055 unsigned int i; 1056 1057 for (i = 0; i < RTE_DIM(eth_dev_rx_offload_names); ++i) { 1058 if (offload == eth_dev_rx_offload_names[i].offload) { 1059 name = eth_dev_rx_offload_names[i].name; 1060 break; 1061 } 1062 } 1063 1064 rte_ethdev_trace_rx_offload_name(offload, name); 1065 1066 return name; 1067 } 1068 1069 const char * 1070 rte_eth_dev_tx_offload_name(uint64_t offload) 1071 { 1072 const char *name = "UNKNOWN"; 1073 unsigned int i; 1074 1075 for (i = 0; i < RTE_DIM(eth_dev_tx_offload_names); ++i) { 1076 if (offload == eth_dev_tx_offload_names[i].offload) { 1077 name = eth_dev_tx_offload_names[i].name; 1078 break; 1079 } 1080 } 1081 1082 rte_ethdev_trace_tx_offload_name(offload, name); 1083 1084 return name; 1085 } 1086 1087 static char * 1088 eth_dev_offload_names(uint64_t bitmask, char *buf, size_t size, 1089 const char *(*offload_name)(uint64_t)) 1090 { 1091 unsigned int pos = 0; 1092 int ret; 1093 1094 /* There should be at least enough space to handle those cases */ 1095 RTE_ASSERT(size >= sizeof("none") && size >= sizeof("...")); 1096 1097 if (bitmask == 0) { 1098 ret = snprintf(&buf[pos], size - pos, "none"); 1099 if (ret < 0 || pos + ret >= size) 1100 ret = 0; 1101 pos += ret; 1102 goto out; 1103 } 1104 1105 while (bitmask != 0) { 1106 uint64_t offload = RTE_BIT64(rte_ctz64(bitmask)); 1107 const char *name = offload_name(offload); 1108 1109 ret = snprintf(&buf[pos], size - pos, "%s,", name); 1110 if (ret < 0 || pos + ret >= size) { 1111 if (pos + sizeof("...") >= size) 1112 pos = size - sizeof("..."); 1113 ret = snprintf(&buf[pos], size - pos, "..."); 1114 if (ret > 0 && pos + ret < size) 1115 pos += ret; 1116 goto out; 1117 } 1118 1119 pos += ret; 1120 bitmask &= ~offload; 1121 } 1122 1123 /* Eliminate trailing comma */ 1124 pos--; 1125 out: 1126 buf[pos] = '\0'; 1127 return buf; 1128 } 1129 1130 const char * 1131 rte_eth_dev_capability_name(uint64_t capability) 1132 { 1133 const char *name = "UNKNOWN"; 1134 unsigned int i; 1135 1136 for (i = 0; i < RTE_DIM(rte_eth_dev_capa_names); ++i) { 1137 if (capability == rte_eth_dev_capa_names[i].offload) { 1138 name = rte_eth_dev_capa_names[i].name; 1139 break; 1140 } 1141 } 1142 1143 rte_ethdev_trace_capability_name(capability, name); 1144 1145 return name; 1146 } 1147 1148 static inline int 1149 eth_dev_check_lro_pkt_size(uint16_t port_id, uint32_t config_size, 1150 uint32_t max_rx_pkt_len, uint32_t dev_info_size) 1151 { 1152 int ret = 0; 1153 1154 if (dev_info_size == 0) { 1155 if (config_size != max_rx_pkt_len) { 1156 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%d max_lro_pkt_size" 1157 " %u != %u is not allowed", 1158 port_id, config_size, max_rx_pkt_len); 1159 ret = -EINVAL; 1160 } 1161 } else if (config_size > dev_info_size) { 1162 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%d max_lro_pkt_size %u " 1163 "> max allowed value %u", port_id, config_size, 1164 dev_info_size); 1165 ret = -EINVAL; 1166 } else if (config_size < RTE_ETHER_MIN_LEN) { 1167 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%d max_lro_pkt_size %u " 1168 "< min allowed value %u", port_id, config_size, 1169 (unsigned int)RTE_ETHER_MIN_LEN); 1170 ret = -EINVAL; 1171 } 1172 return ret; 1173 } 1174 1175 /* 1176 * Validate offloads that are requested through rte_eth_dev_configure against 1177 * the offloads successfully set by the Ethernet device. 1178 * 1179 * @param port_id 1180 * The port identifier of the Ethernet device. 1181 * @param req_offloads 1182 * The offloads that have been requested through `rte_eth_dev_configure`. 1183 * @param set_offloads 1184 * The offloads successfully set by the Ethernet device. 1185 * @param offload_type 1186 * The offload type i.e. Rx/Tx string. 1187 * @param offload_name 1188 * The function that prints the offload name. 1189 * @return 1190 * - (0) if validation successful. 1191 * - (-EINVAL) if requested offload has been silently disabled. 1192 */ 1193 static int 1194 eth_dev_validate_offloads(uint16_t port_id, uint64_t req_offloads, 1195 uint64_t set_offloads, const char *offload_type, 1196 const char *(*offload_name)(uint64_t)) 1197 { 1198 uint64_t offloads_diff = req_offloads ^ set_offloads; 1199 uint64_t offload; 1200 int ret = 0; 1201 1202 while (offloads_diff != 0) { 1203 /* Check if any offload is requested but not enabled. */ 1204 offload = RTE_BIT64(rte_ctz64(offloads_diff)); 1205 if (offload & req_offloads) { 1206 RTE_ETHDEV_LOG_LINE(ERR, 1207 "Port %u failed to enable %s offload %s", 1208 port_id, offload_type, offload_name(offload)); 1209 ret = -EINVAL; 1210 } 1211 1212 /* Check if offload couldn't be disabled. */ 1213 if (offload & set_offloads) { 1214 RTE_ETHDEV_LOG_LINE(DEBUG, 1215 "Port %u %s offload %s is not requested but enabled", 1216 port_id, offload_type, offload_name(offload)); 1217 } 1218 1219 offloads_diff &= ~offload; 1220 } 1221 1222 return ret; 1223 } 1224 1225 static uint32_t 1226 eth_dev_get_overhead_len(uint32_t max_rx_pktlen, uint16_t max_mtu) 1227 { 1228 uint32_t overhead_len; 1229 1230 if (max_mtu != UINT16_MAX && max_rx_pktlen > max_mtu) 1231 overhead_len = max_rx_pktlen - max_mtu; 1232 else 1233 overhead_len = RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 1234 1235 return overhead_len; 1236 } 1237 1238 /* rte_eth_dev_info_get() should be called prior to this function */ 1239 static int 1240 eth_dev_validate_mtu(uint16_t port_id, struct rte_eth_dev_info *dev_info, 1241 uint16_t mtu) 1242 { 1243 uint32_t overhead_len; 1244 uint32_t frame_size; 1245 1246 if (mtu < dev_info->min_mtu) { 1247 RTE_ETHDEV_LOG_LINE(ERR, 1248 "MTU (%u) < device min MTU (%u) for port_id %u", 1249 mtu, dev_info->min_mtu, port_id); 1250 return -EINVAL; 1251 } 1252 if (mtu > dev_info->max_mtu) { 1253 RTE_ETHDEV_LOG_LINE(ERR, 1254 "MTU (%u) > device max MTU (%u) for port_id %u", 1255 mtu, dev_info->max_mtu, port_id); 1256 return -EINVAL; 1257 } 1258 1259 overhead_len = eth_dev_get_overhead_len(dev_info->max_rx_pktlen, 1260 dev_info->max_mtu); 1261 frame_size = mtu + overhead_len; 1262 if (frame_size < RTE_ETHER_MIN_LEN) { 1263 RTE_ETHDEV_LOG_LINE(ERR, 1264 "Frame size (%u) < min frame size (%u) for port_id %u", 1265 frame_size, RTE_ETHER_MIN_LEN, port_id); 1266 return -EINVAL; 1267 } 1268 1269 if (frame_size > dev_info->max_rx_pktlen) { 1270 RTE_ETHDEV_LOG_LINE(ERR, 1271 "Frame size (%u) > device max frame size (%u) for port_id %u", 1272 frame_size, dev_info->max_rx_pktlen, port_id); 1273 return -EINVAL; 1274 } 1275 1276 return 0; 1277 } 1278 1279 int 1280 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, 1281 const struct rte_eth_conf *dev_conf) 1282 { 1283 enum rte_eth_hash_function algorithm; 1284 struct rte_eth_dev *dev; 1285 struct rte_eth_dev_info dev_info; 1286 struct rte_eth_conf orig_conf; 1287 int diag; 1288 int ret; 1289 uint16_t old_mtu; 1290 1291 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1292 dev = &rte_eth_devices[port_id]; 1293 1294 if (dev_conf == NULL) { 1295 RTE_ETHDEV_LOG_LINE(ERR, 1296 "Cannot configure ethdev port %u from NULL config", 1297 port_id); 1298 return -EINVAL; 1299 } 1300 1301 if (*dev->dev_ops->dev_configure == NULL) 1302 return -ENOTSUP; 1303 1304 if (dev->data->dev_started) { 1305 RTE_ETHDEV_LOG_LINE(ERR, 1306 "Port %u must be stopped to allow configuration", 1307 port_id); 1308 return -EBUSY; 1309 } 1310 1311 /* 1312 * Ensure that "dev_configured" is always 0 each time prepare to do 1313 * dev_configure() to avoid any non-anticipated behaviour. 1314 * And set to 1 when dev_configure() is executed successfully. 1315 */ 1316 dev->data->dev_configured = 0; 1317 1318 /* Store original config, as rollback required on failure */ 1319 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf)); 1320 1321 /* 1322 * Copy the dev_conf parameter into the dev structure. 1323 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get 1324 */ 1325 if (dev_conf != &dev->data->dev_conf) 1326 memcpy(&dev->data->dev_conf, dev_conf, 1327 sizeof(dev->data->dev_conf)); 1328 1329 /* Backup mtu for rollback */ 1330 old_mtu = dev->data->mtu; 1331 1332 /* fields must be zero to reserve them for future ABI changes */ 1333 if (dev_conf->rxmode.reserved_64s[0] != 0 || 1334 dev_conf->rxmode.reserved_64s[1] != 0 || 1335 dev_conf->rxmode.reserved_ptrs[0] != NULL || 1336 dev_conf->rxmode.reserved_ptrs[1] != NULL) { 1337 RTE_ETHDEV_LOG_LINE(ERR, "Rxmode reserved fields not zero"); 1338 ret = -EINVAL; 1339 goto rollback; 1340 } 1341 1342 if (dev_conf->txmode.reserved_64s[0] != 0 || 1343 dev_conf->txmode.reserved_64s[1] != 0 || 1344 dev_conf->txmode.reserved_ptrs[0] != NULL || 1345 dev_conf->txmode.reserved_ptrs[1] != NULL) { 1346 RTE_ETHDEV_LOG_LINE(ERR, "txmode reserved fields not zero"); 1347 ret = -EINVAL; 1348 goto rollback; 1349 } 1350 1351 ret = rte_eth_dev_info_get(port_id, &dev_info); 1352 if (ret != 0) 1353 goto rollback; 1354 1355 /* If number of queues specified by application for both Rx and Tx is 1356 * zero, use driver preferred values. This cannot be done individually 1357 * as it is valid for either Tx or Rx (but not both) to be zero. 1358 * If driver does not provide any preferred valued, fall back on 1359 * EAL defaults. 1360 */ 1361 if (nb_rx_q == 0 && nb_tx_q == 0) { 1362 nb_rx_q = dev_info.default_rxportconf.nb_queues; 1363 if (nb_rx_q == 0) 1364 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES; 1365 nb_tx_q = dev_info.default_txportconf.nb_queues; 1366 if (nb_tx_q == 0) 1367 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES; 1368 } 1369 1370 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) { 1371 RTE_ETHDEV_LOG_LINE(ERR, 1372 "Number of Rx queues requested (%u) is greater than max supported(%d)", 1373 nb_rx_q, RTE_MAX_QUEUES_PER_PORT); 1374 ret = -EINVAL; 1375 goto rollback; 1376 } 1377 1378 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) { 1379 RTE_ETHDEV_LOG_LINE(ERR, 1380 "Number of Tx queues requested (%u) is greater than max supported(%d)", 1381 nb_tx_q, RTE_MAX_QUEUES_PER_PORT); 1382 ret = -EINVAL; 1383 goto rollback; 1384 } 1385 1386 /* 1387 * Check that the numbers of Rx and Tx queues are not greater 1388 * than the maximum number of Rx and Tx queues supported by the 1389 * configured device. 1390 */ 1391 if (nb_rx_q > dev_info.max_rx_queues) { 1392 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u", 1393 port_id, nb_rx_q, dev_info.max_rx_queues); 1394 ret = -EINVAL; 1395 goto rollback; 1396 } 1397 1398 if (nb_tx_q > dev_info.max_tx_queues) { 1399 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u", 1400 port_id, nb_tx_q, dev_info.max_tx_queues); 1401 ret = -EINVAL; 1402 goto rollback; 1403 } 1404 1405 /* Check that the device supports requested interrupts */ 1406 if ((dev_conf->intr_conf.lsc == 1) && 1407 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) { 1408 RTE_ETHDEV_LOG_LINE(ERR, "Driver %s does not support lsc", 1409 dev->device->driver->name); 1410 ret = -EINVAL; 1411 goto rollback; 1412 } 1413 if ((dev_conf->intr_conf.rmv == 1) && 1414 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) { 1415 RTE_ETHDEV_LOG_LINE(ERR, "Driver %s does not support rmv", 1416 dev->device->driver->name); 1417 ret = -EINVAL; 1418 goto rollback; 1419 } 1420 1421 if (dev_conf->rxmode.mtu == 0) 1422 dev->data->dev_conf.rxmode.mtu = 1423 (dev_info.max_mtu == 0) ? RTE_ETHER_MTU : 1424 RTE_MIN(dev_info.max_mtu, RTE_ETHER_MTU); 1425 1426 ret = eth_dev_validate_mtu(port_id, &dev_info, 1427 dev->data->dev_conf.rxmode.mtu); 1428 if (ret != 0) 1429 goto rollback; 1430 1431 dev->data->mtu = dev->data->dev_conf.rxmode.mtu; 1432 1433 /* 1434 * If LRO is enabled, check that the maximum aggregated packet 1435 * size is supported by the configured device. 1436 */ 1437 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) { 1438 uint32_t max_rx_pktlen; 1439 uint32_t overhead_len; 1440 1441 overhead_len = eth_dev_get_overhead_len(dev_info.max_rx_pktlen, 1442 dev_info.max_mtu); 1443 max_rx_pktlen = dev->data->dev_conf.rxmode.mtu + overhead_len; 1444 if (dev_conf->rxmode.max_lro_pkt_size == 0) 1445 dev->data->dev_conf.rxmode.max_lro_pkt_size = max_rx_pktlen; 1446 ret = eth_dev_check_lro_pkt_size(port_id, 1447 dev->data->dev_conf.rxmode.max_lro_pkt_size, 1448 max_rx_pktlen, 1449 dev_info.max_lro_pkt_size); 1450 if (ret != 0) 1451 goto rollback; 1452 } 1453 1454 /* Any requested offloading must be within its device capabilities */ 1455 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) != 1456 dev_conf->rxmode.offloads) { 1457 char buffer[512]; 1458 1459 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%u does not support Rx offloads %s", 1460 port_id, eth_dev_offload_names( 1461 dev_conf->rxmode.offloads & ~dev_info.rx_offload_capa, 1462 buffer, sizeof(buffer), rte_eth_dev_rx_offload_name)); 1463 RTE_ETHDEV_LOG_LINE(DEBUG, "Ethdev port_id=%u was requested Rx offloads %s", 1464 port_id, eth_dev_offload_names(dev_conf->rxmode.offloads, 1465 buffer, sizeof(buffer), rte_eth_dev_rx_offload_name)); 1466 RTE_ETHDEV_LOG_LINE(DEBUG, "Ethdev port_id=%u supports Rx offloads %s", 1467 port_id, eth_dev_offload_names(dev_info.rx_offload_capa, 1468 buffer, sizeof(buffer), rte_eth_dev_rx_offload_name)); 1469 1470 ret = -EINVAL; 1471 goto rollback; 1472 } 1473 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) != 1474 dev_conf->txmode.offloads) { 1475 char buffer[512]; 1476 1477 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port_id=%u does not support Tx offloads %s", 1478 port_id, eth_dev_offload_names( 1479 dev_conf->txmode.offloads & ~dev_info.tx_offload_capa, 1480 buffer, sizeof(buffer), rte_eth_dev_tx_offload_name)); 1481 RTE_ETHDEV_LOG_LINE(DEBUG, "Ethdev port_id=%u was requested Tx offloads %s", 1482 port_id, eth_dev_offload_names(dev_conf->txmode.offloads, 1483 buffer, sizeof(buffer), rte_eth_dev_tx_offload_name)); 1484 RTE_ETHDEV_LOG_LINE(DEBUG, "Ethdev port_id=%u supports Tx offloads %s", 1485 port_id, eth_dev_offload_names(dev_info.tx_offload_capa, 1486 buffer, sizeof(buffer), rte_eth_dev_tx_offload_name)); 1487 ret = -EINVAL; 1488 goto rollback; 1489 } 1490 1491 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf = 1492 rte_eth_rss_hf_refine(dev_conf->rx_adv_conf.rss_conf.rss_hf); 1493 1494 /* Check that device supports requested rss hash functions. */ 1495 if ((dev_info.flow_type_rss_offloads | 1496 dev_conf->rx_adv_conf.rss_conf.rss_hf) != 1497 dev_info.flow_type_rss_offloads) { 1498 RTE_ETHDEV_LOG_LINE(ERR, 1499 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64, 1500 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf, 1501 dev_info.flow_type_rss_offloads); 1502 ret = -EINVAL; 1503 goto rollback; 1504 } 1505 1506 /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */ 1507 if (((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) == 0) && 1508 (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH)) { 1509 RTE_ETHDEV_LOG_LINE(ERR, 1510 "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested", 1511 port_id, 1512 rte_eth_dev_rx_offload_name(RTE_ETH_RX_OFFLOAD_RSS_HASH)); 1513 ret = -EINVAL; 1514 goto rollback; 1515 } 1516 1517 if (dev_conf->rx_adv_conf.rss_conf.rss_key != NULL && 1518 dev_conf->rx_adv_conf.rss_conf.rss_key_len != dev_info.hash_key_size) { 1519 RTE_ETHDEV_LOG_LINE(ERR, 1520 "Ethdev port_id=%u invalid RSS key len: %u, valid value: %u", 1521 port_id, dev_conf->rx_adv_conf.rss_conf.rss_key_len, 1522 dev_info.hash_key_size); 1523 ret = -EINVAL; 1524 goto rollback; 1525 } 1526 1527 algorithm = dev_conf->rx_adv_conf.rss_conf.algorithm; 1528 if ((size_t)algorithm >= CHAR_BIT * sizeof(dev_info.rss_algo_capa) || 1529 (dev_info.rss_algo_capa & RTE_ETH_HASH_ALGO_TO_CAPA(algorithm)) == 0) { 1530 RTE_ETHDEV_LOG_LINE(ERR, 1531 "Ethdev port_id=%u configured RSS hash algorithm (%u)" 1532 "is not in the algorithm capability (0x%" PRIx32 ")", 1533 port_id, algorithm, dev_info.rss_algo_capa); 1534 ret = -EINVAL; 1535 goto rollback; 1536 } 1537 1538 /* 1539 * Setup new number of Rx/Tx queues and reconfigure device. 1540 */ 1541 diag = eth_dev_rx_queue_config(dev, nb_rx_q); 1542 if (diag != 0) { 1543 RTE_ETHDEV_LOG_LINE(ERR, 1544 "Port%u eth_dev_rx_queue_config = %d", 1545 port_id, diag); 1546 ret = diag; 1547 goto rollback; 1548 } 1549 1550 diag = eth_dev_tx_queue_config(dev, nb_tx_q); 1551 if (diag != 0) { 1552 RTE_ETHDEV_LOG_LINE(ERR, 1553 "Port%u eth_dev_tx_queue_config = %d", 1554 port_id, diag); 1555 eth_dev_rx_queue_config(dev, 0); 1556 ret = diag; 1557 goto rollback; 1558 } 1559 1560 diag = (*dev->dev_ops->dev_configure)(dev); 1561 if (diag != 0) { 1562 RTE_ETHDEV_LOG_LINE(ERR, "Port%u dev_configure = %d", 1563 port_id, diag); 1564 ret = eth_err(port_id, diag); 1565 goto reset_queues; 1566 } 1567 1568 /* Initialize Rx profiling if enabled at compilation time. */ 1569 diag = __rte_eth_dev_profile_init(port_id, dev); 1570 if (diag != 0) { 1571 RTE_ETHDEV_LOG_LINE(ERR, "Port%u __rte_eth_dev_profile_init = %d", 1572 port_id, diag); 1573 ret = eth_err(port_id, diag); 1574 goto reset_queues; 1575 } 1576 1577 /* Validate Rx offloads. */ 1578 diag = eth_dev_validate_offloads(port_id, 1579 dev_conf->rxmode.offloads, 1580 dev->data->dev_conf.rxmode.offloads, "Rx", 1581 rte_eth_dev_rx_offload_name); 1582 if (diag != 0) { 1583 ret = diag; 1584 goto reset_queues; 1585 } 1586 1587 /* Validate Tx offloads. */ 1588 diag = eth_dev_validate_offloads(port_id, 1589 dev_conf->txmode.offloads, 1590 dev->data->dev_conf.txmode.offloads, "Tx", 1591 rte_eth_dev_tx_offload_name); 1592 if (diag != 0) { 1593 ret = diag; 1594 goto reset_queues; 1595 } 1596 1597 dev->data->dev_configured = 1; 1598 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, 0); 1599 return 0; 1600 reset_queues: 1601 eth_dev_rx_queue_config(dev, 0); 1602 eth_dev_tx_queue_config(dev, 0); 1603 rollback: 1604 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf)); 1605 if (old_mtu != dev->data->mtu) 1606 dev->data->mtu = old_mtu; 1607 1608 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret); 1609 return ret; 1610 } 1611 1612 static void 1613 eth_dev_mac_restore(struct rte_eth_dev *dev, 1614 struct rte_eth_dev_info *dev_info) 1615 { 1616 struct rte_ether_addr *addr; 1617 uint16_t i; 1618 uint32_t pool = 0; 1619 uint64_t pool_mask; 1620 1621 /* replay MAC address configuration including default MAC */ 1622 addr = &dev->data->mac_addrs[0]; 1623 if (*dev->dev_ops->mac_addr_set != NULL) 1624 (*dev->dev_ops->mac_addr_set)(dev, addr); 1625 else if (*dev->dev_ops->mac_addr_add != NULL) 1626 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool); 1627 1628 if (*dev->dev_ops->mac_addr_add != NULL) { 1629 for (i = 1; i < dev_info->max_mac_addrs; i++) { 1630 addr = &dev->data->mac_addrs[i]; 1631 1632 /* skip zero address */ 1633 if (rte_is_zero_ether_addr(addr)) 1634 continue; 1635 1636 pool = 0; 1637 pool_mask = dev->data->mac_pool_sel[i]; 1638 1639 do { 1640 if (pool_mask & UINT64_C(1)) 1641 (*dev->dev_ops->mac_addr_add)(dev, 1642 addr, i, pool); 1643 pool_mask >>= 1; 1644 pool++; 1645 } while (pool_mask); 1646 } 1647 } 1648 } 1649 1650 static int 1651 eth_dev_promiscuous_restore(struct rte_eth_dev *dev, uint16_t port_id) 1652 { 1653 int ret; 1654 1655 /* replay promiscuous configuration */ 1656 /* 1657 * use callbacks directly since we don't need port_id check and 1658 * would like to bypass the same value set 1659 */ 1660 if (rte_eth_promiscuous_get(port_id) == 1 && 1661 *dev->dev_ops->promiscuous_enable != NULL) { 1662 ret = eth_err(port_id, 1663 (*dev->dev_ops->promiscuous_enable)(dev)); 1664 if (ret != 0 && ret != -ENOTSUP) { 1665 RTE_ETHDEV_LOG_LINE(ERR, 1666 "Failed to enable promiscuous mode for device (port %u): %s", 1667 port_id, rte_strerror(-ret)); 1668 return ret; 1669 } 1670 } else if (rte_eth_promiscuous_get(port_id) == 0 && 1671 *dev->dev_ops->promiscuous_disable != NULL) { 1672 ret = eth_err(port_id, 1673 (*dev->dev_ops->promiscuous_disable)(dev)); 1674 if (ret != 0 && ret != -ENOTSUP) { 1675 RTE_ETHDEV_LOG_LINE(ERR, 1676 "Failed to disable promiscuous mode for device (port %u): %s", 1677 port_id, rte_strerror(-ret)); 1678 return ret; 1679 } 1680 } 1681 1682 return 0; 1683 } 1684 1685 static int 1686 eth_dev_allmulticast_restore(struct rte_eth_dev *dev, uint16_t port_id) 1687 { 1688 int ret; 1689 1690 /* replay all multicast configuration */ 1691 /* 1692 * use callbacks directly since we don't need port_id check and 1693 * would like to bypass the same value set 1694 */ 1695 if (rte_eth_allmulticast_get(port_id) == 1 && 1696 *dev->dev_ops->allmulticast_enable != NULL) { 1697 ret = eth_err(port_id, 1698 (*dev->dev_ops->allmulticast_enable)(dev)); 1699 if (ret != 0 && ret != -ENOTSUP) { 1700 RTE_ETHDEV_LOG_LINE(ERR, 1701 "Failed to enable allmulticast mode for device (port %u): %s", 1702 port_id, rte_strerror(-ret)); 1703 return ret; 1704 } 1705 } else if (rte_eth_allmulticast_get(port_id) == 0 && 1706 *dev->dev_ops->allmulticast_disable != NULL) { 1707 ret = eth_err(port_id, 1708 (*dev->dev_ops->allmulticast_disable)(dev)); 1709 if (ret != 0 && ret != -ENOTSUP) { 1710 RTE_ETHDEV_LOG_LINE(ERR, 1711 "Failed to disable allmulticast mode for device (port %u): %s", 1712 port_id, rte_strerror(-ret)); 1713 return ret; 1714 } 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int 1721 eth_dev_config_restore(struct rte_eth_dev *dev, 1722 struct rte_eth_dev_info *dev_info, 1723 uint64_t restore_flags, 1724 uint16_t port_id) 1725 { 1726 int ret; 1727 1728 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR) && 1729 (restore_flags & RTE_ETH_RESTORE_MAC_ADDR)) 1730 eth_dev_mac_restore(dev, dev_info); 1731 1732 if (restore_flags & RTE_ETH_RESTORE_PROMISC) { 1733 ret = eth_dev_promiscuous_restore(dev, port_id); 1734 if (ret != 0) 1735 return ret; 1736 } 1737 1738 if (restore_flags & RTE_ETH_RESTORE_ALLMULTI) { 1739 ret = eth_dev_allmulticast_restore(dev, port_id); 1740 if (ret != 0) 1741 return ret; 1742 } 1743 1744 return 0; 1745 } 1746 1747 int 1748 rte_eth_dev_start(uint16_t port_id) 1749 { 1750 struct rte_eth_dev *dev; 1751 struct rte_eth_dev_info dev_info; 1752 uint64_t restore_flags; 1753 int diag; 1754 int ret, ret_stop; 1755 1756 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1757 dev = &rte_eth_devices[port_id]; 1758 1759 if (*dev->dev_ops->dev_start == NULL) 1760 return -ENOTSUP; 1761 1762 if (dev->data->dev_configured == 0) { 1763 RTE_ETHDEV_LOG_LINE(INFO, 1764 "Device with port_id=%"PRIu16" is not configured.", 1765 port_id); 1766 return -EINVAL; 1767 } 1768 1769 if (dev->data->dev_started != 0) { 1770 RTE_ETHDEV_LOG_LINE(INFO, 1771 "Device with port_id=%"PRIu16" already started", 1772 port_id); 1773 return 0; 1774 } 1775 1776 ret = rte_eth_dev_info_get(port_id, &dev_info); 1777 if (ret != 0) 1778 return ret; 1779 1780 restore_flags = rte_eth_get_restore_flags(dev, RTE_ETH_START); 1781 1782 /* Lets restore MAC now if device does not support live change */ 1783 if ((*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR) && 1784 (restore_flags & RTE_ETH_RESTORE_MAC_ADDR)) 1785 eth_dev_mac_restore(dev, &dev_info); 1786 1787 diag = (*dev->dev_ops->dev_start)(dev); 1788 if (diag == 0) 1789 dev->data->dev_started = 1; 1790 else 1791 return eth_err(port_id, diag); 1792 1793 ret = eth_dev_config_restore(dev, &dev_info, restore_flags, port_id); 1794 if (ret != 0) { 1795 RTE_ETHDEV_LOG_LINE(ERR, 1796 "Error during restoring configuration for device (port %u): %s", 1797 port_id, rte_strerror(-ret)); 1798 ret_stop = rte_eth_dev_stop(port_id); 1799 if (ret_stop != 0) { 1800 RTE_ETHDEV_LOG_LINE(ERR, 1801 "Failed to stop device (port %u): %s", 1802 port_id, rte_strerror(-ret_stop)); 1803 } 1804 1805 return ret; 1806 } 1807 1808 if (dev->data->dev_conf.intr_conf.lsc == 0) { 1809 if (*dev->dev_ops->link_update == NULL) 1810 return -ENOTSUP; 1811 (*dev->dev_ops->link_update)(dev, 0); 1812 } 1813 1814 /* expose selection of PMD fast-path functions */ 1815 eth_dev_fp_ops_setup(rte_eth_fp_ops + port_id, dev); 1816 1817 rte_ethdev_trace_start(port_id); 1818 return 0; 1819 } 1820 1821 int 1822 rte_eth_dev_stop(uint16_t port_id) 1823 { 1824 struct rte_eth_dev *dev; 1825 int ret; 1826 1827 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1828 dev = &rte_eth_devices[port_id]; 1829 1830 if (*dev->dev_ops->dev_stop == NULL) 1831 return -ENOTSUP; 1832 1833 if (dev->data->dev_started == 0) { 1834 RTE_ETHDEV_LOG_LINE(INFO, 1835 "Device with port_id=%"PRIu16" already stopped", 1836 port_id); 1837 return 0; 1838 } 1839 1840 /* point fast-path functions to dummy ones */ 1841 eth_dev_fp_ops_reset(rte_eth_fp_ops + port_id); 1842 1843 ret = (*dev->dev_ops->dev_stop)(dev); 1844 if (ret == 0) 1845 dev->data->dev_started = 0; 1846 rte_ethdev_trace_stop(port_id, ret); 1847 1848 return ret; 1849 } 1850 1851 int 1852 rte_eth_dev_set_link_up(uint16_t port_id) 1853 { 1854 struct rte_eth_dev *dev; 1855 int ret; 1856 1857 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1858 dev = &rte_eth_devices[port_id]; 1859 1860 if (*dev->dev_ops->dev_set_link_up == NULL) 1861 return -ENOTSUP; 1862 ret = eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev)); 1863 1864 rte_ethdev_trace_set_link_up(port_id, ret); 1865 1866 return ret; 1867 } 1868 1869 int 1870 rte_eth_dev_set_link_down(uint16_t port_id) 1871 { 1872 struct rte_eth_dev *dev; 1873 int ret; 1874 1875 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1876 dev = &rte_eth_devices[port_id]; 1877 1878 if (*dev->dev_ops->dev_set_link_down == NULL) 1879 return -ENOTSUP; 1880 ret = eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev)); 1881 1882 rte_ethdev_trace_set_link_down(port_id, ret); 1883 1884 return ret; 1885 } 1886 1887 int 1888 rte_eth_speed_lanes_get(uint16_t port_id, uint32_t *lane) 1889 { 1890 struct rte_eth_dev *dev; 1891 1892 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1893 dev = &rte_eth_devices[port_id]; 1894 1895 if (*dev->dev_ops->speed_lanes_get == NULL) 1896 return -ENOTSUP; 1897 return eth_err(port_id, (*dev->dev_ops->speed_lanes_get)(dev, lane)); 1898 } 1899 1900 int 1901 rte_eth_speed_lanes_get_capability(uint16_t port_id, 1902 struct rte_eth_speed_lanes_capa *speed_lanes_capa, 1903 unsigned int num) 1904 { 1905 struct rte_eth_dev *dev; 1906 int ret; 1907 1908 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1909 dev = &rte_eth_devices[port_id]; 1910 1911 if (*dev->dev_ops->speed_lanes_get_capa == NULL) 1912 return -ENOTSUP; 1913 1914 if (speed_lanes_capa == NULL && num > 0) { 1915 RTE_ETHDEV_LOG_LINE(ERR, 1916 "Cannot get ethdev port %u speed lanes capability to NULL when array size is non zero", 1917 port_id); 1918 return -EINVAL; 1919 } 1920 1921 ret = (*dev->dev_ops->speed_lanes_get_capa)(dev, speed_lanes_capa, num); 1922 1923 return ret; 1924 } 1925 1926 int 1927 rte_eth_speed_lanes_set(uint16_t port_id, uint32_t speed_lanes_capa) 1928 { 1929 struct rte_eth_dev *dev; 1930 1931 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1932 dev = &rte_eth_devices[port_id]; 1933 1934 if (*dev->dev_ops->speed_lanes_set == NULL) 1935 return -ENOTSUP; 1936 return eth_err(port_id, (*dev->dev_ops->speed_lanes_set)(dev, speed_lanes_capa)); 1937 } 1938 1939 int 1940 rte_eth_dev_close(uint16_t port_id) 1941 { 1942 struct rte_eth_dev *dev; 1943 int firsterr, binerr; 1944 int *lasterr = &firsterr; 1945 1946 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1947 dev = &rte_eth_devices[port_id]; 1948 1949 /* 1950 * Secondary process needs to close device to release process private 1951 * resources. But secondary process should not be obliged to wait 1952 * for device stop before closing ethdev. 1953 */ 1954 if (rte_eal_process_type() == RTE_PROC_PRIMARY && 1955 dev->data->dev_started) { 1956 RTE_ETHDEV_LOG_LINE(ERR, "Cannot close started device (port %u)", 1957 port_id); 1958 return -EINVAL; 1959 } 1960 1961 if (*dev->dev_ops->dev_close == NULL) 1962 return -ENOTSUP; 1963 *lasterr = (*dev->dev_ops->dev_close)(dev); 1964 if (*lasterr != 0) 1965 lasterr = &binerr; 1966 1967 rte_ethdev_trace_close(port_id); 1968 *lasterr = rte_eth_dev_release_port(dev); 1969 1970 return firsterr; 1971 } 1972 1973 int 1974 rte_eth_dev_reset(uint16_t port_id) 1975 { 1976 struct rte_eth_dev *dev; 1977 int ret; 1978 1979 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1980 dev = &rte_eth_devices[port_id]; 1981 1982 if (*dev->dev_ops->dev_reset == NULL) 1983 return -ENOTSUP; 1984 1985 ret = rte_eth_dev_stop(port_id); 1986 if (ret != 0) { 1987 RTE_ETHDEV_LOG_LINE(ERR, 1988 "Failed to stop device (port %u) before reset: %s - ignore", 1989 port_id, rte_strerror(-ret)); 1990 } 1991 ret = eth_err(port_id, dev->dev_ops->dev_reset(dev)); 1992 1993 rte_ethdev_trace_reset(port_id, ret); 1994 1995 return ret; 1996 } 1997 1998 int 1999 rte_eth_dev_is_removed(uint16_t port_id) 2000 { 2001 struct rte_eth_dev *dev; 2002 int ret; 2003 2004 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0); 2005 dev = &rte_eth_devices[port_id]; 2006 2007 if (dev->state == RTE_ETH_DEV_REMOVED) 2008 return 1; 2009 2010 if (*dev->dev_ops->is_removed == NULL) 2011 return 0; 2012 2013 ret = dev->dev_ops->is_removed(dev); 2014 if (ret != 0) 2015 /* Device is physically removed. */ 2016 dev->state = RTE_ETH_DEV_REMOVED; 2017 2018 rte_ethdev_trace_is_removed(port_id, ret); 2019 2020 return ret; 2021 } 2022 2023 static int 2024 rte_eth_check_rx_mempool(struct rte_mempool *mp, uint16_t offset, 2025 uint16_t min_length) 2026 { 2027 uint16_t data_room_size; 2028 2029 /* 2030 * Check the size of the mbuf data buffer, this value 2031 * must be provided in the private data of the memory pool. 2032 * First check that the memory pool(s) has a valid private data. 2033 */ 2034 if (mp->private_data_size < 2035 sizeof(struct rte_pktmbuf_pool_private)) { 2036 RTE_ETHDEV_LOG_LINE(ERR, "%s private_data_size %u < %u", 2037 mp->name, mp->private_data_size, 2038 (unsigned int) 2039 sizeof(struct rte_pktmbuf_pool_private)); 2040 return -ENOSPC; 2041 } 2042 data_room_size = rte_pktmbuf_data_room_size(mp); 2043 if (data_room_size < offset + min_length) { 2044 RTE_ETHDEV_LOG_LINE(ERR, 2045 "%s mbuf_data_room_size %u < %u (%u + %u)", 2046 mp->name, data_room_size, 2047 offset + min_length, offset, min_length); 2048 return -EINVAL; 2049 } 2050 return 0; 2051 } 2052 2053 static int 2054 eth_dev_buffer_split_get_supported_hdrs_helper(uint16_t port_id, uint32_t **ptypes) 2055 { 2056 int cnt; 2057 2058 cnt = rte_eth_buffer_split_get_supported_hdr_ptypes(port_id, NULL, 0); 2059 if (cnt <= 0) 2060 return cnt; 2061 2062 *ptypes = malloc(sizeof(uint32_t) * cnt); 2063 if (*ptypes == NULL) 2064 return -ENOMEM; 2065 2066 cnt = rte_eth_buffer_split_get_supported_hdr_ptypes(port_id, *ptypes, cnt); 2067 if (cnt <= 0) { 2068 free(*ptypes); 2069 *ptypes = NULL; 2070 } 2071 return cnt; 2072 } 2073 2074 static int 2075 rte_eth_rx_queue_check_split(uint16_t port_id, 2076 const struct rte_eth_rxseg_split *rx_seg, 2077 uint16_t n_seg, uint32_t *mbp_buf_size, 2078 const struct rte_eth_dev_info *dev_info) 2079 { 2080 const struct rte_eth_rxseg_capa *seg_capa = &dev_info->rx_seg_capa; 2081 struct rte_mempool *mp_first; 2082 uint32_t offset_mask; 2083 uint16_t seg_idx; 2084 int ret = 0; 2085 int ptype_cnt; 2086 uint32_t *ptypes; 2087 uint32_t prev_proto_hdrs = RTE_PTYPE_UNKNOWN; 2088 int i; 2089 2090 if (n_seg > seg_capa->max_nseg) { 2091 RTE_ETHDEV_LOG_LINE(ERR, 2092 "Requested Rx segments %u exceed supported %u", 2093 n_seg, seg_capa->max_nseg); 2094 return -EINVAL; 2095 } 2096 /* 2097 * Check the sizes and offsets against buffer sizes 2098 * for each segment specified in extended configuration. 2099 */ 2100 mp_first = rx_seg[0].mp; 2101 offset_mask = RTE_BIT32(seg_capa->offset_align_log2) - 1; 2102 2103 ptypes = NULL; 2104 ptype_cnt = eth_dev_buffer_split_get_supported_hdrs_helper(port_id, &ptypes); 2105 2106 for (seg_idx = 0; seg_idx < n_seg; seg_idx++) { 2107 struct rte_mempool *mpl = rx_seg[seg_idx].mp; 2108 uint32_t length = rx_seg[seg_idx].length; 2109 uint32_t offset = rx_seg[seg_idx].offset; 2110 uint32_t proto_hdr = rx_seg[seg_idx].proto_hdr; 2111 2112 if (mpl == NULL) { 2113 RTE_ETHDEV_LOG_LINE(ERR, "null mempool pointer"); 2114 ret = -EINVAL; 2115 goto out; 2116 } 2117 if (seg_idx != 0 && mp_first != mpl && 2118 seg_capa->multi_pools == 0) { 2119 RTE_ETHDEV_LOG_LINE(ERR, "Receiving to multiple pools is not supported"); 2120 ret = -ENOTSUP; 2121 goto out; 2122 } 2123 if (offset != 0) { 2124 if (seg_capa->offset_allowed == 0) { 2125 RTE_ETHDEV_LOG_LINE(ERR, "Rx segmentation with offset is not supported"); 2126 ret = -ENOTSUP; 2127 goto out; 2128 } 2129 if (offset & offset_mask) { 2130 RTE_ETHDEV_LOG_LINE(ERR, "Rx segmentation invalid offset alignment %u, %u", 2131 offset, 2132 seg_capa->offset_align_log2); 2133 ret = -EINVAL; 2134 goto out; 2135 } 2136 } 2137 2138 offset += seg_idx != 0 ? 0 : RTE_PKTMBUF_HEADROOM; 2139 *mbp_buf_size = rte_pktmbuf_data_room_size(mpl); 2140 if (proto_hdr != 0) { 2141 /* Split based on protocol headers. */ 2142 if (length != 0) { 2143 RTE_ETHDEV_LOG_LINE(ERR, 2144 "Do not set length split and protocol split within a segment" 2145 ); 2146 ret = -EINVAL; 2147 goto out; 2148 } 2149 if ((proto_hdr & prev_proto_hdrs) != 0) { 2150 RTE_ETHDEV_LOG_LINE(ERR, 2151 "Repeat with previous protocol headers or proto-split after length-based split" 2152 ); 2153 ret = -EINVAL; 2154 goto out; 2155 } 2156 if (ptype_cnt <= 0) { 2157 RTE_ETHDEV_LOG_LINE(ERR, 2158 "Port %u failed to get supported buffer split header protocols", 2159 port_id); 2160 ret = -ENOTSUP; 2161 goto out; 2162 } 2163 for (i = 0; i < ptype_cnt; i++) { 2164 if ((prev_proto_hdrs | proto_hdr) == ptypes[i]) 2165 break; 2166 } 2167 if (i == ptype_cnt) { 2168 RTE_ETHDEV_LOG_LINE(ERR, 2169 "Requested Rx split header protocols 0x%x is not supported.", 2170 proto_hdr); 2171 ret = -EINVAL; 2172 goto out; 2173 } 2174 prev_proto_hdrs |= proto_hdr; 2175 } else { 2176 /* Split at fixed length. */ 2177 length = length != 0 ? length : *mbp_buf_size; 2178 prev_proto_hdrs = RTE_PTYPE_ALL_MASK; 2179 } 2180 2181 ret = rte_eth_check_rx_mempool(mpl, offset, length); 2182 if (ret != 0) 2183 goto out; 2184 } 2185 out: 2186 free(ptypes); 2187 return ret; 2188 } 2189 2190 static int 2191 rte_eth_rx_queue_check_mempools(struct rte_mempool **rx_mempools, 2192 uint16_t n_mempools, uint32_t *min_buf_size, 2193 const struct rte_eth_dev_info *dev_info) 2194 { 2195 uint16_t pool_idx; 2196 int ret; 2197 2198 if (n_mempools > dev_info->max_rx_mempools) { 2199 RTE_ETHDEV_LOG_LINE(ERR, 2200 "Too many Rx mempools %u vs maximum %u", 2201 n_mempools, dev_info->max_rx_mempools); 2202 return -EINVAL; 2203 } 2204 2205 for (pool_idx = 0; pool_idx < n_mempools; pool_idx++) { 2206 struct rte_mempool *mp = rx_mempools[pool_idx]; 2207 2208 if (mp == NULL) { 2209 RTE_ETHDEV_LOG_LINE(ERR, "null Rx mempool pointer"); 2210 return -EINVAL; 2211 } 2212 2213 ret = rte_eth_check_rx_mempool(mp, RTE_PKTMBUF_HEADROOM, 2214 dev_info->min_rx_bufsize); 2215 if (ret != 0) 2216 return ret; 2217 2218 *min_buf_size = RTE_MIN(*min_buf_size, 2219 rte_pktmbuf_data_room_size(mp)); 2220 } 2221 2222 return 0; 2223 } 2224 2225 int 2226 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 2227 uint16_t nb_rx_desc, unsigned int socket_id, 2228 const struct rte_eth_rxconf *rx_conf, 2229 struct rte_mempool *mp) 2230 { 2231 int ret; 2232 uint64_t rx_offloads; 2233 uint32_t mbp_buf_size = UINT32_MAX; 2234 struct rte_eth_dev *dev; 2235 struct rte_eth_dev_info dev_info; 2236 struct rte_eth_rxconf local_conf; 2237 uint32_t buf_data_size; 2238 2239 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2240 dev = &rte_eth_devices[port_id]; 2241 2242 if (rx_queue_id >= dev->data->nb_rx_queues) { 2243 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", rx_queue_id); 2244 return -EINVAL; 2245 } 2246 2247 if (*dev->dev_ops->rx_queue_setup == NULL) 2248 return -ENOTSUP; 2249 2250 if (rx_conf != NULL && 2251 (rx_conf->reserved_64s[0] != 0 || 2252 rx_conf->reserved_64s[1] != 0 || 2253 rx_conf->reserved_ptrs[0] != NULL || 2254 rx_conf->reserved_ptrs[1] != NULL)) { 2255 RTE_ETHDEV_LOG_LINE(ERR, "Rx conf reserved fields not zero"); 2256 return -EINVAL; 2257 } 2258 2259 ret = rte_eth_dev_info_get(port_id, &dev_info); 2260 if (ret != 0) 2261 return ret; 2262 2263 rx_offloads = dev->data->dev_conf.rxmode.offloads; 2264 if (rx_conf != NULL) 2265 rx_offloads |= rx_conf->offloads; 2266 2267 /* Ensure that we have one and only one source of Rx buffers */ 2268 if ((mp != NULL) + 2269 (rx_conf != NULL && rx_conf->rx_nseg > 0) + 2270 (rx_conf != NULL && rx_conf->rx_nmempool > 0) != 1) { 2271 RTE_ETHDEV_LOG_LINE(ERR, 2272 "Ambiguous Rx mempools configuration"); 2273 return -EINVAL; 2274 } 2275 2276 if (mp != NULL) { 2277 /* Single pool configuration check. */ 2278 ret = rte_eth_check_rx_mempool(mp, RTE_PKTMBUF_HEADROOM, 2279 dev_info.min_rx_bufsize); 2280 if (ret != 0) 2281 return ret; 2282 2283 mbp_buf_size = rte_pktmbuf_data_room_size(mp); 2284 buf_data_size = mbp_buf_size - RTE_PKTMBUF_HEADROOM; 2285 if (buf_data_size > dev_info.max_rx_bufsize) 2286 RTE_ETHDEV_LOG_LINE(DEBUG, 2287 "For port_id=%u, the mbuf data buffer size (%u) is bigger than " 2288 "max buffer size (%u) device can utilize, so mbuf size can be reduced.", 2289 port_id, buf_data_size, dev_info.max_rx_bufsize); 2290 } else if (rx_conf != NULL && rx_conf->rx_nseg > 0) { 2291 const struct rte_eth_rxseg_split *rx_seg; 2292 uint16_t n_seg; 2293 2294 /* Extended multi-segment configuration check. */ 2295 if (rx_conf->rx_seg == NULL) { 2296 RTE_ETHDEV_LOG_LINE(ERR, 2297 "Memory pool is null and no multi-segment configuration provided"); 2298 return -EINVAL; 2299 } 2300 2301 rx_seg = (const struct rte_eth_rxseg_split *)rx_conf->rx_seg; 2302 n_seg = rx_conf->rx_nseg; 2303 2304 if (rx_offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) { 2305 ret = rte_eth_rx_queue_check_split(port_id, rx_seg, n_seg, 2306 &mbp_buf_size, 2307 &dev_info); 2308 if (ret != 0) 2309 return ret; 2310 } else { 2311 RTE_ETHDEV_LOG_LINE(ERR, "No Rx segmentation offload configured"); 2312 return -EINVAL; 2313 } 2314 } else if (rx_conf != NULL && rx_conf->rx_nmempool > 0) { 2315 /* Extended multi-pool configuration check. */ 2316 if (rx_conf->rx_mempools == NULL) { 2317 RTE_ETHDEV_LOG_LINE(ERR, "Memory pools array is null"); 2318 return -EINVAL; 2319 } 2320 2321 ret = rte_eth_rx_queue_check_mempools(rx_conf->rx_mempools, 2322 rx_conf->rx_nmempool, 2323 &mbp_buf_size, 2324 &dev_info); 2325 if (ret != 0) 2326 return ret; 2327 } else { 2328 RTE_ETHDEV_LOG_LINE(ERR, "Missing Rx mempool configuration"); 2329 return -EINVAL; 2330 } 2331 2332 /* Use default specified by driver, if nb_rx_desc is zero */ 2333 if (nb_rx_desc == 0) { 2334 nb_rx_desc = dev_info.default_rxportconf.ring_size; 2335 /* If driver default is also zero, fall back on EAL default */ 2336 if (nb_rx_desc == 0) 2337 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE; 2338 } 2339 2340 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max || 2341 nb_rx_desc < dev_info.rx_desc_lim.nb_min || 2342 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) { 2343 2344 RTE_ETHDEV_LOG_LINE(ERR, 2345 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu", 2346 nb_rx_desc, dev_info.rx_desc_lim.nb_max, 2347 dev_info.rx_desc_lim.nb_min, 2348 dev_info.rx_desc_lim.nb_align); 2349 return -EINVAL; 2350 } 2351 2352 if (dev->data->dev_started && 2353 !(dev_info.dev_capa & 2354 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP)) 2355 return -EBUSY; 2356 2357 if (dev->data->dev_started && 2358 (dev->data->rx_queue_state[rx_queue_id] != 2359 RTE_ETH_QUEUE_STATE_STOPPED)) 2360 return -EBUSY; 2361 2362 eth_dev_rxq_release(dev, rx_queue_id); 2363 2364 if (rx_conf == NULL) 2365 rx_conf = &dev_info.default_rxconf; 2366 2367 local_conf = *rx_conf; 2368 2369 /* 2370 * If an offloading has already been enabled in 2371 * rte_eth_dev_configure(), it has been enabled on all queues, 2372 * so there is no need to enable it in this queue again. 2373 * The local_conf.offloads input to underlying PMD only carries 2374 * those offloadings which are only enabled on this queue and 2375 * not enabled on all queues. 2376 */ 2377 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads; 2378 2379 /* 2380 * New added offloadings for this queue are those not enabled in 2381 * rte_eth_dev_configure() and they must be per-queue type. 2382 * A pure per-port offloading can't be enabled on a queue while 2383 * disabled on another queue. A pure per-port offloading can't 2384 * be enabled for any queue as new added one if it hasn't been 2385 * enabled in rte_eth_dev_configure(). 2386 */ 2387 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) != 2388 local_conf.offloads) { 2389 RTE_ETHDEV_LOG_LINE(ERR, 2390 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 2391 "within per-queue offload capabilities 0x%"PRIx64" in %s()", 2392 port_id, rx_queue_id, local_conf.offloads, 2393 dev_info.rx_queue_offload_capa, 2394 __func__); 2395 return -EINVAL; 2396 } 2397 2398 if (local_conf.share_group > 0 && 2399 (dev_info.dev_capa & RTE_ETH_DEV_CAPA_RXQ_SHARE) == 0) { 2400 RTE_ETHDEV_LOG_LINE(ERR, 2401 "Ethdev port_id=%d rx_queue_id=%d, enabled share_group=%hu while device doesn't support Rx queue share", 2402 port_id, rx_queue_id, local_conf.share_group); 2403 return -EINVAL; 2404 } 2405 2406 /* 2407 * If LRO is enabled, check that the maximum aggregated packet 2408 * size is supported by the configured device. 2409 */ 2410 /* Get the real Ethernet overhead length */ 2411 if (local_conf.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) { 2412 uint32_t overhead_len; 2413 uint32_t max_rx_pktlen; 2414 int ret; 2415 2416 overhead_len = eth_dev_get_overhead_len(dev_info.max_rx_pktlen, 2417 dev_info.max_mtu); 2418 max_rx_pktlen = dev->data->mtu + overhead_len; 2419 if (dev->data->dev_conf.rxmode.max_lro_pkt_size == 0) 2420 dev->data->dev_conf.rxmode.max_lro_pkt_size = max_rx_pktlen; 2421 ret = eth_dev_check_lro_pkt_size(port_id, 2422 dev->data->dev_conf.rxmode.max_lro_pkt_size, 2423 max_rx_pktlen, 2424 dev_info.max_lro_pkt_size); 2425 if (ret != 0) 2426 return ret; 2427 } 2428 2429 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc, 2430 socket_id, &local_conf, mp); 2431 if (!ret) { 2432 if (!dev->data->min_rx_buf_size || 2433 dev->data->min_rx_buf_size > mbp_buf_size) 2434 dev->data->min_rx_buf_size = mbp_buf_size; 2435 } 2436 2437 rte_ethdev_trace_rxq_setup(port_id, rx_queue_id, nb_rx_desc, mp, 2438 rx_conf, ret); 2439 return eth_err(port_id, ret); 2440 } 2441 2442 int 2443 rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 2444 uint16_t nb_rx_desc, 2445 const struct rte_eth_hairpin_conf *conf) 2446 { 2447 int ret; 2448 struct rte_eth_dev *dev; 2449 struct rte_eth_hairpin_cap cap; 2450 int i; 2451 int count; 2452 2453 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2454 dev = &rte_eth_devices[port_id]; 2455 2456 if (rx_queue_id >= dev->data->nb_rx_queues) { 2457 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", rx_queue_id); 2458 return -EINVAL; 2459 } 2460 2461 if (conf == NULL) { 2462 RTE_ETHDEV_LOG_LINE(ERR, 2463 "Cannot setup ethdev port %u Rx hairpin queue from NULL config", 2464 port_id); 2465 return -EINVAL; 2466 } 2467 2468 if (conf->reserved != 0) { 2469 RTE_ETHDEV_LOG_LINE(ERR, 2470 "Rx hairpin reserved field not zero"); 2471 return -EINVAL; 2472 } 2473 2474 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap); 2475 if (ret != 0) 2476 return ret; 2477 if (*dev->dev_ops->rx_hairpin_queue_setup == NULL) 2478 return -ENOTSUP; 2479 /* if nb_rx_desc is zero use max number of desc from the driver. */ 2480 if (nb_rx_desc == 0) 2481 nb_rx_desc = cap.max_nb_desc; 2482 if (nb_rx_desc > cap.max_nb_desc) { 2483 RTE_ETHDEV_LOG_LINE(ERR, 2484 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu", 2485 nb_rx_desc, cap.max_nb_desc); 2486 return -EINVAL; 2487 } 2488 if (conf->peer_count > cap.max_rx_2_tx) { 2489 RTE_ETHDEV_LOG_LINE(ERR, 2490 "Invalid value for number of peers for Rx queue(=%u), should be: <= %hu", 2491 conf->peer_count, cap.max_rx_2_tx); 2492 return -EINVAL; 2493 } 2494 if (conf->use_locked_device_memory && !cap.rx_cap.locked_device_memory) { 2495 RTE_ETHDEV_LOG_LINE(ERR, 2496 "Attempt to use locked device memory for Rx queue, which is not supported"); 2497 return -EINVAL; 2498 } 2499 if (conf->use_rte_memory && !cap.rx_cap.rte_memory) { 2500 RTE_ETHDEV_LOG_LINE(ERR, 2501 "Attempt to use DPDK memory for Rx queue, which is not supported"); 2502 return -EINVAL; 2503 } 2504 if (conf->use_locked_device_memory && conf->use_rte_memory) { 2505 RTE_ETHDEV_LOG_LINE(ERR, 2506 "Attempt to use mutually exclusive memory settings for Rx queue"); 2507 return -EINVAL; 2508 } 2509 if (conf->force_memory && 2510 !conf->use_locked_device_memory && 2511 !conf->use_rte_memory) { 2512 RTE_ETHDEV_LOG_LINE(ERR, 2513 "Attempt to force Rx queue memory settings, but none is set"); 2514 return -EINVAL; 2515 } 2516 if (conf->peer_count == 0) { 2517 RTE_ETHDEV_LOG_LINE(ERR, 2518 "Invalid value for number of peers for Rx queue(=%u), should be: > 0", 2519 conf->peer_count); 2520 return -EINVAL; 2521 } 2522 for (i = 0, count = 0; i < dev->data->nb_rx_queues && 2523 cap.max_nb_queues != UINT16_MAX; i++) { 2524 if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i)) 2525 count++; 2526 } 2527 if (count > cap.max_nb_queues) { 2528 RTE_ETHDEV_LOG_LINE(ERR, "To many Rx hairpin queues max is %d", 2529 cap.max_nb_queues); 2530 return -EINVAL; 2531 } 2532 if (dev->data->dev_started) 2533 return -EBUSY; 2534 eth_dev_rxq_release(dev, rx_queue_id); 2535 ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id, 2536 nb_rx_desc, conf); 2537 if (ret == 0) 2538 dev->data->rx_queue_state[rx_queue_id] = 2539 RTE_ETH_QUEUE_STATE_HAIRPIN; 2540 ret = eth_err(port_id, ret); 2541 2542 rte_eth_trace_rx_hairpin_queue_setup(port_id, rx_queue_id, nb_rx_desc, 2543 conf, ret); 2544 2545 return ret; 2546 } 2547 2548 int 2549 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 2550 uint16_t nb_tx_desc, unsigned int socket_id, 2551 const struct rte_eth_txconf *tx_conf) 2552 { 2553 struct rte_eth_dev *dev; 2554 struct rte_eth_dev_info dev_info; 2555 struct rte_eth_txconf local_conf; 2556 int ret; 2557 2558 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2559 dev = &rte_eth_devices[port_id]; 2560 2561 if (tx_queue_id >= dev->data->nb_tx_queues) { 2562 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Tx queue_id=%u", tx_queue_id); 2563 return -EINVAL; 2564 } 2565 2566 if (*dev->dev_ops->tx_queue_setup == NULL) 2567 return -ENOTSUP; 2568 2569 if (tx_conf != NULL && 2570 (tx_conf->reserved_64s[0] != 0 || 2571 tx_conf->reserved_64s[1] != 0 || 2572 tx_conf->reserved_ptrs[0] != NULL || 2573 tx_conf->reserved_ptrs[1] != NULL)) { 2574 RTE_ETHDEV_LOG_LINE(ERR, "Tx conf reserved fields not zero"); 2575 return -EINVAL; 2576 } 2577 2578 ret = rte_eth_dev_info_get(port_id, &dev_info); 2579 if (ret != 0) 2580 return ret; 2581 2582 /* Use default specified by driver, if nb_tx_desc is zero */ 2583 if (nb_tx_desc == 0) { 2584 nb_tx_desc = dev_info.default_txportconf.ring_size; 2585 /* If driver default is zero, fall back on EAL default */ 2586 if (nb_tx_desc == 0) 2587 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE; 2588 } 2589 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max || 2590 nb_tx_desc < dev_info.tx_desc_lim.nb_min || 2591 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) { 2592 RTE_ETHDEV_LOG_LINE(ERR, 2593 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu", 2594 nb_tx_desc, dev_info.tx_desc_lim.nb_max, 2595 dev_info.tx_desc_lim.nb_min, 2596 dev_info.tx_desc_lim.nb_align); 2597 return -EINVAL; 2598 } 2599 2600 if (dev->data->dev_started && 2601 !(dev_info.dev_capa & 2602 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP)) 2603 return -EBUSY; 2604 2605 if (dev->data->dev_started && 2606 (dev->data->tx_queue_state[tx_queue_id] != 2607 RTE_ETH_QUEUE_STATE_STOPPED)) 2608 return -EBUSY; 2609 2610 eth_dev_txq_release(dev, tx_queue_id); 2611 2612 if (tx_conf == NULL) 2613 tx_conf = &dev_info.default_txconf; 2614 2615 local_conf = *tx_conf; 2616 2617 /* 2618 * If an offloading has already been enabled in 2619 * rte_eth_dev_configure(), it has been enabled on all queues, 2620 * so there is no need to enable it in this queue again. 2621 * The local_conf.offloads input to underlying PMD only carries 2622 * those offloadings which are only enabled on this queue and 2623 * not enabled on all queues. 2624 */ 2625 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads; 2626 2627 /* 2628 * New added offloadings for this queue are those not enabled in 2629 * rte_eth_dev_configure() and they must be per-queue type. 2630 * A pure per-port offloading can't be enabled on a queue while 2631 * disabled on another queue. A pure per-port offloading can't 2632 * be enabled for any queue as new added one if it hasn't been 2633 * enabled in rte_eth_dev_configure(). 2634 */ 2635 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) != 2636 local_conf.offloads) { 2637 RTE_ETHDEV_LOG_LINE(ERR, 2638 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 2639 "within per-queue offload capabilities 0x%"PRIx64" in %s()", 2640 port_id, tx_queue_id, local_conf.offloads, 2641 dev_info.tx_queue_offload_capa, 2642 __func__); 2643 return -EINVAL; 2644 } 2645 2646 rte_ethdev_trace_txq_setup(port_id, tx_queue_id, nb_tx_desc, tx_conf); 2647 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev, 2648 tx_queue_id, nb_tx_desc, socket_id, &local_conf)); 2649 } 2650 2651 int 2652 rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 2653 uint16_t nb_tx_desc, 2654 const struct rte_eth_hairpin_conf *conf) 2655 { 2656 struct rte_eth_dev *dev; 2657 struct rte_eth_hairpin_cap cap; 2658 int i; 2659 int count; 2660 int ret; 2661 2662 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2663 dev = &rte_eth_devices[port_id]; 2664 2665 if (tx_queue_id >= dev->data->nb_tx_queues) { 2666 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Tx queue_id=%u", tx_queue_id); 2667 return -EINVAL; 2668 } 2669 2670 if (conf == NULL) { 2671 RTE_ETHDEV_LOG_LINE(ERR, 2672 "Cannot setup ethdev port %u Tx hairpin queue from NULL config", 2673 port_id); 2674 return -EINVAL; 2675 } 2676 2677 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap); 2678 if (ret != 0) 2679 return ret; 2680 if (*dev->dev_ops->tx_hairpin_queue_setup == NULL) 2681 return -ENOTSUP; 2682 /* if nb_rx_desc is zero use max number of desc from the driver. */ 2683 if (nb_tx_desc == 0) 2684 nb_tx_desc = cap.max_nb_desc; 2685 if (nb_tx_desc > cap.max_nb_desc) { 2686 RTE_ETHDEV_LOG_LINE(ERR, 2687 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu", 2688 nb_tx_desc, cap.max_nb_desc); 2689 return -EINVAL; 2690 } 2691 if (conf->peer_count > cap.max_tx_2_rx) { 2692 RTE_ETHDEV_LOG_LINE(ERR, 2693 "Invalid value for number of peers for Tx queue(=%u), should be: <= %hu", 2694 conf->peer_count, cap.max_tx_2_rx); 2695 return -EINVAL; 2696 } 2697 if (conf->use_locked_device_memory && !cap.tx_cap.locked_device_memory) { 2698 RTE_ETHDEV_LOG_LINE(ERR, 2699 "Attempt to use locked device memory for Tx queue, which is not supported"); 2700 return -EINVAL; 2701 } 2702 if (conf->use_rte_memory && !cap.tx_cap.rte_memory) { 2703 RTE_ETHDEV_LOG_LINE(ERR, 2704 "Attempt to use DPDK memory for Tx queue, which is not supported"); 2705 return -EINVAL; 2706 } 2707 if (conf->use_locked_device_memory && conf->use_rte_memory) { 2708 RTE_ETHDEV_LOG_LINE(ERR, 2709 "Attempt to use mutually exclusive memory settings for Tx queue"); 2710 return -EINVAL; 2711 } 2712 if (conf->force_memory && 2713 !conf->use_locked_device_memory && 2714 !conf->use_rte_memory) { 2715 RTE_ETHDEV_LOG_LINE(ERR, 2716 "Attempt to force Tx queue memory settings, but none is set"); 2717 return -EINVAL; 2718 } 2719 if (conf->peer_count == 0) { 2720 RTE_ETHDEV_LOG_LINE(ERR, 2721 "Invalid value for number of peers for Tx queue(=%u), should be: > 0", 2722 conf->peer_count); 2723 return -EINVAL; 2724 } 2725 for (i = 0, count = 0; i < dev->data->nb_tx_queues && 2726 cap.max_nb_queues != UINT16_MAX; i++) { 2727 if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i)) 2728 count++; 2729 } 2730 if (count > cap.max_nb_queues) { 2731 RTE_ETHDEV_LOG_LINE(ERR, "To many Tx hairpin queues max is %d", 2732 cap.max_nb_queues); 2733 return -EINVAL; 2734 } 2735 if (dev->data->dev_started) 2736 return -EBUSY; 2737 eth_dev_txq_release(dev, tx_queue_id); 2738 ret = (*dev->dev_ops->tx_hairpin_queue_setup) 2739 (dev, tx_queue_id, nb_tx_desc, conf); 2740 if (ret == 0) 2741 dev->data->tx_queue_state[tx_queue_id] = 2742 RTE_ETH_QUEUE_STATE_HAIRPIN; 2743 ret = eth_err(port_id, ret); 2744 2745 rte_eth_trace_tx_hairpin_queue_setup(port_id, tx_queue_id, nb_tx_desc, 2746 conf, ret); 2747 2748 return ret; 2749 } 2750 2751 int 2752 rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port) 2753 { 2754 struct rte_eth_dev *dev; 2755 int ret; 2756 2757 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV); 2758 dev = &rte_eth_devices[tx_port]; 2759 2760 if (dev->data->dev_started == 0) { 2761 RTE_ETHDEV_LOG_LINE(ERR, "Tx port %d is not started", tx_port); 2762 return -EBUSY; 2763 } 2764 2765 if (*dev->dev_ops->hairpin_bind == NULL) 2766 return -ENOTSUP; 2767 ret = (*dev->dev_ops->hairpin_bind)(dev, rx_port); 2768 if (ret != 0) 2769 RTE_ETHDEV_LOG_LINE(ERR, "Failed to bind hairpin Tx %d" 2770 " to Rx %d (%d - all ports)", 2771 tx_port, rx_port, RTE_MAX_ETHPORTS); 2772 2773 rte_eth_trace_hairpin_bind(tx_port, rx_port, ret); 2774 2775 return ret; 2776 } 2777 2778 int 2779 rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port) 2780 { 2781 struct rte_eth_dev *dev; 2782 int ret; 2783 2784 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV); 2785 dev = &rte_eth_devices[tx_port]; 2786 2787 if (dev->data->dev_started == 0) { 2788 RTE_ETHDEV_LOG_LINE(ERR, "Tx port %d is already stopped", tx_port); 2789 return -EBUSY; 2790 } 2791 2792 if (*dev->dev_ops->hairpin_unbind == NULL) 2793 return -ENOTSUP; 2794 ret = (*dev->dev_ops->hairpin_unbind)(dev, rx_port); 2795 if (ret != 0) 2796 RTE_ETHDEV_LOG_LINE(ERR, "Failed to unbind hairpin Tx %d" 2797 " from Rx %d (%d - all ports)", 2798 tx_port, rx_port, RTE_MAX_ETHPORTS); 2799 2800 rte_eth_trace_hairpin_unbind(tx_port, rx_port, ret); 2801 2802 return ret; 2803 } 2804 2805 int 2806 rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports, 2807 size_t len, uint32_t direction) 2808 { 2809 struct rte_eth_dev *dev; 2810 int ret; 2811 2812 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2813 dev = &rte_eth_devices[port_id]; 2814 2815 if (peer_ports == NULL) { 2816 RTE_ETHDEV_LOG_LINE(ERR, 2817 "Cannot get ethdev port %u hairpin peer ports to NULL", 2818 port_id); 2819 return -EINVAL; 2820 } 2821 2822 if (len == 0) { 2823 RTE_ETHDEV_LOG_LINE(ERR, 2824 "Cannot get ethdev port %u hairpin peer ports to array with zero size", 2825 port_id); 2826 return -EINVAL; 2827 } 2828 2829 if (*dev->dev_ops->hairpin_get_peer_ports == NULL) 2830 return -ENOTSUP; 2831 2832 ret = (*dev->dev_ops->hairpin_get_peer_ports)(dev, peer_ports, 2833 len, direction); 2834 if (ret < 0) 2835 RTE_ETHDEV_LOG_LINE(ERR, "Failed to get %d hairpin peer %s ports", 2836 port_id, direction ? "Rx" : "Tx"); 2837 2838 rte_eth_trace_hairpin_get_peer_ports(port_id, peer_ports, len, 2839 direction, ret); 2840 2841 return ret; 2842 } 2843 2844 void 2845 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent, 2846 void *userdata __rte_unused) 2847 { 2848 rte_pktmbuf_free_bulk(pkts, unsent); 2849 2850 rte_eth_trace_tx_buffer_drop_callback((void **)pkts, unsent); 2851 } 2852 2853 void 2854 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent, 2855 void *userdata) 2856 { 2857 uint64_t *count = userdata; 2858 2859 rte_pktmbuf_free_bulk(pkts, unsent); 2860 *count += unsent; 2861 2862 rte_eth_trace_tx_buffer_count_callback((void **)pkts, unsent, *count); 2863 } 2864 2865 int 2866 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer, 2867 buffer_tx_error_fn cbfn, void *userdata) 2868 { 2869 if (buffer == NULL) { 2870 RTE_ETHDEV_LOG_LINE(ERR, 2871 "Cannot set Tx buffer error callback to NULL buffer"); 2872 return -EINVAL; 2873 } 2874 2875 buffer->error_callback = cbfn; 2876 buffer->error_userdata = userdata; 2877 2878 rte_eth_trace_tx_buffer_set_err_callback(buffer); 2879 2880 return 0; 2881 } 2882 2883 int 2884 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size) 2885 { 2886 int ret = 0; 2887 2888 if (buffer == NULL) { 2889 RTE_ETHDEV_LOG_LINE(ERR, "Cannot initialize NULL buffer"); 2890 return -EINVAL; 2891 } 2892 2893 buffer->size = size; 2894 if (buffer->error_callback == NULL) { 2895 ret = rte_eth_tx_buffer_set_err_callback( 2896 buffer, rte_eth_tx_buffer_drop_callback, NULL); 2897 } 2898 2899 rte_eth_trace_tx_buffer_init(buffer, size, ret); 2900 2901 return ret; 2902 } 2903 2904 int 2905 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt) 2906 { 2907 struct rte_eth_dev *dev; 2908 int ret; 2909 2910 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2911 dev = &rte_eth_devices[port_id]; 2912 2913 if (*dev->dev_ops->tx_done_cleanup == NULL) 2914 return -ENOTSUP; 2915 2916 /* Call driver to free pending mbufs. */ 2917 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id], 2918 free_cnt); 2919 ret = eth_err(port_id, ret); 2920 2921 rte_eth_trace_tx_done_cleanup(port_id, queue_id, free_cnt, ret); 2922 2923 return ret; 2924 } 2925 2926 int 2927 rte_eth_promiscuous_enable(uint16_t port_id) 2928 { 2929 struct rte_eth_dev *dev; 2930 int diag = 0; 2931 2932 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2933 dev = &rte_eth_devices[port_id]; 2934 2935 if (dev->data->promiscuous == 1) 2936 return 0; 2937 2938 if (*dev->dev_ops->promiscuous_enable == NULL) 2939 return -ENOTSUP; 2940 2941 diag = (*dev->dev_ops->promiscuous_enable)(dev); 2942 dev->data->promiscuous = (diag == 0) ? 1 : 0; 2943 2944 diag = eth_err(port_id, diag); 2945 2946 rte_eth_trace_promiscuous_enable(port_id, dev->data->promiscuous, 2947 diag); 2948 2949 return diag; 2950 } 2951 2952 int 2953 rte_eth_promiscuous_disable(uint16_t port_id) 2954 { 2955 struct rte_eth_dev *dev; 2956 int diag = 0; 2957 2958 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2959 dev = &rte_eth_devices[port_id]; 2960 2961 if (dev->data->promiscuous == 0) 2962 return 0; 2963 2964 if (*dev->dev_ops->promiscuous_disable == NULL) 2965 return -ENOTSUP; 2966 2967 dev->data->promiscuous = 0; 2968 diag = (*dev->dev_ops->promiscuous_disable)(dev); 2969 if (diag != 0) 2970 dev->data->promiscuous = 1; 2971 2972 diag = eth_err(port_id, diag); 2973 2974 rte_eth_trace_promiscuous_disable(port_id, dev->data->promiscuous, 2975 diag); 2976 2977 return diag; 2978 } 2979 2980 int 2981 rte_eth_promiscuous_get(uint16_t port_id) 2982 { 2983 struct rte_eth_dev *dev; 2984 2985 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2986 dev = &rte_eth_devices[port_id]; 2987 2988 rte_eth_trace_promiscuous_get(port_id, dev->data->promiscuous); 2989 2990 return dev->data->promiscuous; 2991 } 2992 2993 int 2994 rte_eth_allmulticast_enable(uint16_t port_id) 2995 { 2996 struct rte_eth_dev *dev; 2997 int diag; 2998 2999 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3000 dev = &rte_eth_devices[port_id]; 3001 3002 if (dev->data->all_multicast == 1) 3003 return 0; 3004 3005 if (*dev->dev_ops->allmulticast_enable == NULL) 3006 return -ENOTSUP; 3007 diag = (*dev->dev_ops->allmulticast_enable)(dev); 3008 dev->data->all_multicast = (diag == 0) ? 1 : 0; 3009 3010 diag = eth_err(port_id, diag); 3011 3012 rte_eth_trace_allmulticast_enable(port_id, dev->data->all_multicast, 3013 diag); 3014 3015 return diag; 3016 } 3017 3018 int 3019 rte_eth_allmulticast_disable(uint16_t port_id) 3020 { 3021 struct rte_eth_dev *dev; 3022 int diag; 3023 3024 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3025 dev = &rte_eth_devices[port_id]; 3026 3027 if (dev->data->all_multicast == 0) 3028 return 0; 3029 3030 if (*dev->dev_ops->allmulticast_disable == NULL) 3031 return -ENOTSUP; 3032 dev->data->all_multicast = 0; 3033 diag = (*dev->dev_ops->allmulticast_disable)(dev); 3034 if (diag != 0) 3035 dev->data->all_multicast = 1; 3036 3037 diag = eth_err(port_id, diag); 3038 3039 rte_eth_trace_allmulticast_disable(port_id, dev->data->all_multicast, 3040 diag); 3041 3042 return diag; 3043 } 3044 3045 int 3046 rte_eth_allmulticast_get(uint16_t port_id) 3047 { 3048 struct rte_eth_dev *dev; 3049 3050 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3051 dev = &rte_eth_devices[port_id]; 3052 3053 rte_eth_trace_allmulticast_get(port_id, dev->data->all_multicast); 3054 3055 return dev->data->all_multicast; 3056 } 3057 3058 int 3059 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link) 3060 { 3061 struct rte_eth_dev *dev; 3062 3063 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3064 dev = &rte_eth_devices[port_id]; 3065 3066 if (eth_link == NULL) { 3067 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u link to NULL", 3068 port_id); 3069 return -EINVAL; 3070 } 3071 3072 if (dev->data->dev_conf.intr_conf.lsc && dev->data->dev_started) 3073 rte_eth_linkstatus_get(dev, eth_link); 3074 else { 3075 if (*dev->dev_ops->link_update == NULL) 3076 return -ENOTSUP; 3077 (*dev->dev_ops->link_update)(dev, 1); 3078 *eth_link = dev->data->dev_link; 3079 } 3080 3081 rte_eth_trace_link_get(port_id, eth_link); 3082 3083 return 0; 3084 } 3085 3086 int 3087 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link) 3088 { 3089 struct rte_eth_dev *dev; 3090 3091 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3092 dev = &rte_eth_devices[port_id]; 3093 3094 if (eth_link == NULL) { 3095 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u link to NULL", 3096 port_id); 3097 return -EINVAL; 3098 } 3099 3100 if (dev->data->dev_conf.intr_conf.lsc && dev->data->dev_started) 3101 rte_eth_linkstatus_get(dev, eth_link); 3102 else { 3103 if (*dev->dev_ops->link_update == NULL) 3104 return -ENOTSUP; 3105 (*dev->dev_ops->link_update)(dev, 0); 3106 *eth_link = dev->data->dev_link; 3107 } 3108 3109 rte_eth_trace_link_get_nowait(port_id, eth_link); 3110 3111 return 0; 3112 } 3113 3114 const char * 3115 rte_eth_link_speed_to_str(uint32_t link_speed) 3116 { 3117 const char *ret; 3118 3119 switch (link_speed) { 3120 case RTE_ETH_SPEED_NUM_NONE: 3121 ret = "None"; 3122 break; 3123 case RTE_ETH_SPEED_NUM_10M: 3124 ret = "10 Mbps"; 3125 break; 3126 case RTE_ETH_SPEED_NUM_100M: 3127 ret = "100 Mbps"; 3128 break; 3129 case RTE_ETH_SPEED_NUM_1G: 3130 ret = "1 Gbps"; 3131 break; 3132 case RTE_ETH_SPEED_NUM_2_5G: 3133 ret = "2.5 Gbps"; 3134 break; 3135 case RTE_ETH_SPEED_NUM_5G: 3136 ret = "5 Gbps"; 3137 break; 3138 case RTE_ETH_SPEED_NUM_10G: 3139 ret = "10 Gbps"; 3140 break; 3141 case RTE_ETH_SPEED_NUM_20G: 3142 ret = "20 Gbps"; 3143 break; 3144 case RTE_ETH_SPEED_NUM_25G: 3145 ret = "25 Gbps"; 3146 break; 3147 case RTE_ETH_SPEED_NUM_40G: 3148 ret = "40 Gbps"; 3149 break; 3150 case RTE_ETH_SPEED_NUM_50G: 3151 ret = "50 Gbps"; 3152 break; 3153 case RTE_ETH_SPEED_NUM_56G: 3154 ret = "56 Gbps"; 3155 break; 3156 case RTE_ETH_SPEED_NUM_100G: 3157 ret = "100 Gbps"; 3158 break; 3159 case RTE_ETH_SPEED_NUM_200G: 3160 ret = "200 Gbps"; 3161 break; 3162 case RTE_ETH_SPEED_NUM_400G: 3163 ret = "400 Gbps"; 3164 break; 3165 case RTE_ETH_SPEED_NUM_UNKNOWN: 3166 ret = "Unknown"; 3167 break; 3168 default: 3169 ret = "Invalid"; 3170 } 3171 3172 rte_eth_trace_link_speed_to_str(link_speed, ret); 3173 3174 return ret; 3175 } 3176 3177 int 3178 rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link) 3179 { 3180 int ret; 3181 3182 if (str == NULL) { 3183 RTE_ETHDEV_LOG_LINE(ERR, "Cannot convert link to NULL string"); 3184 return -EINVAL; 3185 } 3186 3187 if (len == 0) { 3188 RTE_ETHDEV_LOG_LINE(ERR, 3189 "Cannot convert link to string with zero size"); 3190 return -EINVAL; 3191 } 3192 3193 if (eth_link == NULL) { 3194 RTE_ETHDEV_LOG_LINE(ERR, "Cannot convert to string from NULL link"); 3195 return -EINVAL; 3196 } 3197 3198 if (eth_link->link_status == RTE_ETH_LINK_DOWN) 3199 ret = snprintf(str, len, "Link down"); 3200 else 3201 ret = snprintf(str, len, "Link up at %s %s %s", 3202 rte_eth_link_speed_to_str(eth_link->link_speed), 3203 (eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? 3204 "FDX" : "HDX", 3205 (eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ? 3206 "Autoneg" : "Fixed"); 3207 3208 rte_eth_trace_link_to_str(len, eth_link, str, ret); 3209 3210 return ret; 3211 } 3212 3213 int 3214 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats) 3215 { 3216 struct rte_eth_dev *dev; 3217 int ret; 3218 3219 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3220 dev = &rte_eth_devices[port_id]; 3221 3222 if (stats == NULL) { 3223 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u stats to NULL", 3224 port_id); 3225 return -EINVAL; 3226 } 3227 3228 memset(stats, 0, sizeof(*stats)); 3229 3230 if (*dev->dev_ops->stats_get == NULL) 3231 return -ENOTSUP; 3232 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed; 3233 ret = eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats)); 3234 3235 rte_eth_trace_stats_get(port_id, stats, ret); 3236 3237 return ret; 3238 } 3239 3240 int 3241 rte_eth_stats_reset(uint16_t port_id) 3242 { 3243 struct rte_eth_dev *dev; 3244 int ret; 3245 3246 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3247 dev = &rte_eth_devices[port_id]; 3248 3249 if (*dev->dev_ops->stats_reset == NULL) 3250 return -ENOTSUP; 3251 ret = (*dev->dev_ops->stats_reset)(dev); 3252 if (ret != 0) 3253 return eth_err(port_id, ret); 3254 3255 dev->data->rx_mbuf_alloc_failed = 0; 3256 3257 rte_eth_trace_stats_reset(port_id); 3258 3259 return 0; 3260 } 3261 3262 static inline int 3263 eth_dev_get_xstats_basic_count(struct rte_eth_dev *dev) 3264 { 3265 uint16_t nb_rxqs, nb_txqs; 3266 int count; 3267 3268 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3269 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3270 3271 count = RTE_NB_STATS; 3272 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) { 3273 count += nb_rxqs * RTE_NB_RXQ_STATS; 3274 count += nb_txqs * RTE_NB_TXQ_STATS; 3275 } 3276 3277 return count; 3278 } 3279 3280 static int 3281 eth_dev_get_xstats_count(uint16_t port_id) 3282 { 3283 struct rte_eth_dev *dev; 3284 int count; 3285 3286 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3287 dev = &rte_eth_devices[port_id]; 3288 if (dev->dev_ops->xstats_get_names != NULL) { 3289 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0); 3290 if (count < 0) 3291 return eth_err(port_id, count); 3292 } else 3293 count = 0; 3294 3295 3296 count += eth_dev_get_xstats_basic_count(dev); 3297 3298 return count; 3299 } 3300 3301 int 3302 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name, 3303 uint64_t *id) 3304 { 3305 int cnt_xstats, idx_xstat; 3306 3307 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3308 3309 if (xstat_name == NULL) { 3310 RTE_ETHDEV_LOG_LINE(ERR, 3311 "Cannot get ethdev port %u xstats ID from NULL xstat name", 3312 port_id); 3313 return -ENOMEM; 3314 } 3315 3316 if (id == NULL) { 3317 RTE_ETHDEV_LOG_LINE(ERR, 3318 "Cannot get ethdev port %u xstats ID to NULL", 3319 port_id); 3320 return -ENOMEM; 3321 } 3322 3323 /* Get count */ 3324 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL); 3325 if (cnt_xstats < 0) { 3326 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get count of xstats"); 3327 return -ENODEV; 3328 } 3329 3330 /* Get id-name lookup table */ 3331 struct rte_eth_xstat_name xstats_names[cnt_xstats]; 3332 3333 if (cnt_xstats != rte_eth_xstats_get_names_by_id( 3334 port_id, xstats_names, cnt_xstats, NULL)) { 3335 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get xstats lookup"); 3336 return -1; 3337 } 3338 3339 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) { 3340 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) { 3341 *id = idx_xstat; 3342 3343 rte_eth_trace_xstats_get_id_by_name(port_id, 3344 xstat_name, *id); 3345 3346 return 0; 3347 }; 3348 } 3349 3350 return -EINVAL; 3351 } 3352 3353 /* retrieve basic stats names */ 3354 static int 3355 eth_basic_stats_get_names(struct rte_eth_dev *dev, 3356 struct rte_eth_xstat_name *xstats_names) 3357 { 3358 int cnt_used_entries = 0; 3359 uint32_t idx, id_queue; 3360 uint16_t num_q; 3361 3362 for (idx = 0; idx < RTE_NB_STATS; idx++) { 3363 strlcpy(xstats_names[cnt_used_entries].name, 3364 eth_dev_stats_strings[idx].name, 3365 sizeof(xstats_names[0].name)); 3366 cnt_used_entries++; 3367 } 3368 3369 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0) 3370 return cnt_used_entries; 3371 3372 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3373 for (id_queue = 0; id_queue < num_q; id_queue++) { 3374 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) { 3375 snprintf(xstats_names[cnt_used_entries].name, 3376 sizeof(xstats_names[0].name), 3377 "rx_q%u_%s", 3378 id_queue, eth_dev_rxq_stats_strings[idx].name); 3379 cnt_used_entries++; 3380 } 3381 3382 } 3383 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3384 for (id_queue = 0; id_queue < num_q; id_queue++) { 3385 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) { 3386 snprintf(xstats_names[cnt_used_entries].name, 3387 sizeof(xstats_names[0].name), 3388 "tx_q%u_%s", 3389 id_queue, eth_dev_txq_stats_strings[idx].name); 3390 cnt_used_entries++; 3391 } 3392 } 3393 return cnt_used_entries; 3394 } 3395 3396 /* retrieve ethdev extended statistics names */ 3397 int 3398 rte_eth_xstats_get_names_by_id(uint16_t port_id, 3399 struct rte_eth_xstat_name *xstats_names, unsigned int size, 3400 uint64_t *ids) 3401 { 3402 struct rte_eth_xstat_name *xstats_names_copy; 3403 unsigned int no_basic_stat_requested = 1; 3404 unsigned int no_ext_stat_requested = 1; 3405 unsigned int expected_entries; 3406 unsigned int basic_count; 3407 struct rte_eth_dev *dev; 3408 unsigned int i; 3409 int ret; 3410 3411 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3412 dev = &rte_eth_devices[port_id]; 3413 3414 basic_count = eth_dev_get_xstats_basic_count(dev); 3415 ret = eth_dev_get_xstats_count(port_id); 3416 if (ret < 0) 3417 return ret; 3418 expected_entries = (unsigned int)ret; 3419 3420 /* Return max number of stats if no ids given */ 3421 if (!ids) { 3422 if (!xstats_names) 3423 return expected_entries; 3424 else if (xstats_names && size < expected_entries) 3425 return expected_entries; 3426 } 3427 3428 if (ids && !xstats_names) 3429 return -EINVAL; 3430 3431 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) { 3432 uint64_t ids_copy[size]; 3433 3434 for (i = 0; i < size; i++) { 3435 if (ids[i] < basic_count) { 3436 no_basic_stat_requested = 0; 3437 break; 3438 } 3439 3440 /* 3441 * Convert ids to xstats ids that PMD knows. 3442 * ids known by user are basic + extended stats. 3443 */ 3444 ids_copy[i] = ids[i] - basic_count; 3445 } 3446 3447 if (no_basic_stat_requested) 3448 return (*dev->dev_ops->xstats_get_names_by_id)(dev, 3449 ids_copy, xstats_names, size); 3450 } 3451 3452 /* Retrieve all stats */ 3453 if (!ids) { 3454 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names, 3455 expected_entries); 3456 if (num_stats < 0 || num_stats > (int)expected_entries) 3457 return num_stats; 3458 else 3459 return expected_entries; 3460 } 3461 3462 xstats_names_copy = calloc(expected_entries, 3463 sizeof(struct rte_eth_xstat_name)); 3464 3465 if (!xstats_names_copy) { 3466 RTE_ETHDEV_LOG_LINE(ERR, "Can't allocate memory"); 3467 return -ENOMEM; 3468 } 3469 3470 if (ids) { 3471 for (i = 0; i < size; i++) { 3472 if (ids[i] >= basic_count) { 3473 no_ext_stat_requested = 0; 3474 break; 3475 } 3476 } 3477 } 3478 3479 /* Fill xstats_names_copy structure */ 3480 if (ids && no_ext_stat_requested) { 3481 eth_basic_stats_get_names(dev, xstats_names_copy); 3482 } else { 3483 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy, 3484 expected_entries); 3485 if (ret < 0) { 3486 free(xstats_names_copy); 3487 return ret; 3488 } 3489 } 3490 3491 /* Filter stats */ 3492 for (i = 0; i < size; i++) { 3493 if (ids[i] >= expected_entries) { 3494 RTE_ETHDEV_LOG_LINE(ERR, "Id value isn't valid"); 3495 free(xstats_names_copy); 3496 return -1; 3497 } 3498 xstats_names[i] = xstats_names_copy[ids[i]]; 3499 3500 rte_eth_trace_xstats_get_names_by_id(port_id, &xstats_names[i], 3501 ids[i]); 3502 } 3503 3504 free(xstats_names_copy); 3505 return size; 3506 } 3507 3508 int 3509 rte_eth_xstats_get_names(uint16_t port_id, 3510 struct rte_eth_xstat_name *xstats_names, 3511 unsigned int size) 3512 { 3513 struct rte_eth_dev *dev; 3514 int cnt_used_entries; 3515 int cnt_expected_entries; 3516 int cnt_driver_entries; 3517 int i; 3518 3519 cnt_expected_entries = eth_dev_get_xstats_count(port_id); 3520 if (xstats_names == NULL || cnt_expected_entries < 0 || 3521 (int)size < cnt_expected_entries) 3522 return cnt_expected_entries; 3523 3524 /* port_id checked in eth_dev_get_xstats_count() */ 3525 dev = &rte_eth_devices[port_id]; 3526 3527 cnt_used_entries = eth_basic_stats_get_names(dev, xstats_names); 3528 3529 if (dev->dev_ops->xstats_get_names != NULL) { 3530 /* If there are any driver-specific xstats, append them 3531 * to end of list. 3532 */ 3533 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)( 3534 dev, 3535 xstats_names + cnt_used_entries, 3536 size - cnt_used_entries); 3537 if (cnt_driver_entries < 0) 3538 return eth_err(port_id, cnt_driver_entries); 3539 cnt_used_entries += cnt_driver_entries; 3540 } 3541 3542 for (i = 0; i < cnt_used_entries; i++) 3543 rte_eth_trace_xstats_get_names(port_id, i, &xstats_names[i], 3544 size, cnt_used_entries); 3545 3546 return cnt_used_entries; 3547 } 3548 3549 3550 static int 3551 eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats) 3552 { 3553 struct rte_eth_dev *dev; 3554 struct rte_eth_stats eth_stats; 3555 unsigned int count = 0, i, q; 3556 uint64_t val, *stats_ptr; 3557 uint16_t nb_rxqs, nb_txqs; 3558 int ret; 3559 3560 ret = rte_eth_stats_get(port_id, ð_stats); 3561 if (ret < 0) 3562 return ret; 3563 3564 dev = &rte_eth_devices[port_id]; 3565 3566 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3567 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3568 3569 /* global stats */ 3570 for (i = 0; i < RTE_NB_STATS; i++) { 3571 stats_ptr = RTE_PTR_ADD(ð_stats, 3572 eth_dev_stats_strings[i].offset); 3573 val = *stats_ptr; 3574 xstats[count++].value = val; 3575 } 3576 3577 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0) 3578 return count; 3579 3580 /* per-rxq stats */ 3581 for (q = 0; q < nb_rxqs; q++) { 3582 for (i = 0; i < RTE_NB_RXQ_STATS; i++) { 3583 stats_ptr = RTE_PTR_ADD(ð_stats, 3584 eth_dev_rxq_stats_strings[i].offset + 3585 q * sizeof(uint64_t)); 3586 val = *stats_ptr; 3587 xstats[count++].value = val; 3588 } 3589 } 3590 3591 /* per-txq stats */ 3592 for (q = 0; q < nb_txqs; q++) { 3593 for (i = 0; i < RTE_NB_TXQ_STATS; i++) { 3594 stats_ptr = RTE_PTR_ADD(ð_stats, 3595 eth_dev_txq_stats_strings[i].offset + 3596 q * sizeof(uint64_t)); 3597 val = *stats_ptr; 3598 xstats[count++].value = val; 3599 } 3600 } 3601 return count; 3602 } 3603 3604 /* retrieve ethdev extended statistics */ 3605 int 3606 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids, 3607 uint64_t *values, unsigned int size) 3608 { 3609 unsigned int no_basic_stat_requested = 1; 3610 unsigned int no_ext_stat_requested = 1; 3611 unsigned int num_xstats_filled; 3612 unsigned int basic_count; 3613 uint16_t expected_entries; 3614 struct rte_eth_dev *dev; 3615 unsigned int i; 3616 int ret; 3617 3618 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3619 dev = &rte_eth_devices[port_id]; 3620 3621 ret = eth_dev_get_xstats_count(port_id); 3622 if (ret < 0) 3623 return ret; 3624 expected_entries = (uint16_t)ret; 3625 struct rte_eth_xstat xstats[expected_entries]; 3626 basic_count = eth_dev_get_xstats_basic_count(dev); 3627 3628 /* Return max number of stats if no ids given */ 3629 if (!ids) { 3630 if (!values) 3631 return expected_entries; 3632 else if (values && size < expected_entries) 3633 return expected_entries; 3634 } 3635 3636 if (ids && !values) 3637 return -EINVAL; 3638 3639 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) { 3640 unsigned int basic_count = eth_dev_get_xstats_basic_count(dev); 3641 uint64_t ids_copy[size]; 3642 3643 for (i = 0; i < size; i++) { 3644 if (ids[i] < basic_count) { 3645 no_basic_stat_requested = 0; 3646 break; 3647 } 3648 3649 /* 3650 * Convert ids to xstats ids that PMD knows. 3651 * ids known by user are basic + extended stats. 3652 */ 3653 ids_copy[i] = ids[i] - basic_count; 3654 } 3655 3656 if (no_basic_stat_requested) 3657 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy, 3658 values, size); 3659 } 3660 3661 if (ids) { 3662 for (i = 0; i < size; i++) { 3663 if (ids[i] >= basic_count) { 3664 no_ext_stat_requested = 0; 3665 break; 3666 } 3667 } 3668 } 3669 3670 /* Fill the xstats structure */ 3671 if (ids && no_ext_stat_requested) 3672 ret = eth_basic_stats_get(port_id, xstats); 3673 else 3674 ret = rte_eth_xstats_get(port_id, xstats, expected_entries); 3675 3676 if (ret < 0) 3677 return ret; 3678 num_xstats_filled = (unsigned int)ret; 3679 3680 /* Return all stats */ 3681 if (!ids) { 3682 for (i = 0; i < num_xstats_filled; i++) 3683 values[i] = xstats[i].value; 3684 return expected_entries; 3685 } 3686 3687 /* Filter stats */ 3688 for (i = 0; i < size; i++) { 3689 if (ids[i] >= expected_entries) { 3690 RTE_ETHDEV_LOG_LINE(ERR, "Id value isn't valid"); 3691 return -1; 3692 } 3693 values[i] = xstats[ids[i]].value; 3694 } 3695 3696 rte_eth_trace_xstats_get_by_id(port_id, ids, values, size); 3697 3698 return size; 3699 } 3700 3701 int 3702 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats, 3703 unsigned int n) 3704 { 3705 struct rte_eth_dev *dev; 3706 unsigned int count, i; 3707 signed int xcount = 0; 3708 int ret; 3709 3710 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3711 if (xstats == NULL && n > 0) 3712 return -EINVAL; 3713 dev = &rte_eth_devices[port_id]; 3714 3715 count = eth_dev_get_xstats_basic_count(dev); 3716 3717 /* implemented by the driver */ 3718 if (dev->dev_ops->xstats_get != NULL) { 3719 /* Retrieve the xstats from the driver at the end of the 3720 * xstats struct. 3721 */ 3722 xcount = (*dev->dev_ops->xstats_get)(dev, 3723 (n > count) ? xstats + count : NULL, 3724 (n > count) ? n - count : 0); 3725 3726 if (xcount < 0) 3727 return eth_err(port_id, xcount); 3728 } 3729 3730 if (n < count + xcount || xstats == NULL) 3731 return count + xcount; 3732 3733 /* now fill the xstats structure */ 3734 ret = eth_basic_stats_get(port_id, xstats); 3735 if (ret < 0) 3736 return ret; 3737 count = ret; 3738 3739 for (i = 0; i < count; i++) 3740 xstats[i].id = i; 3741 /* add an offset to driver-specific stats */ 3742 for ( ; i < count + xcount; i++) 3743 xstats[i].id += count; 3744 3745 for (i = 0; i < n; i++) 3746 rte_eth_trace_xstats_get(port_id, xstats[i]); 3747 3748 return count + xcount; 3749 } 3750 3751 /* reset ethdev extended statistics */ 3752 int 3753 rte_eth_xstats_reset(uint16_t port_id) 3754 { 3755 struct rte_eth_dev *dev; 3756 3757 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3758 dev = &rte_eth_devices[port_id]; 3759 3760 /* implemented by the driver */ 3761 if (dev->dev_ops->xstats_reset != NULL) { 3762 int ret = eth_err(port_id, (*dev->dev_ops->xstats_reset)(dev)); 3763 3764 rte_eth_trace_xstats_reset(port_id, ret); 3765 3766 return ret; 3767 } 3768 3769 /* fallback to default */ 3770 return rte_eth_stats_reset(port_id); 3771 } 3772 3773 static int 3774 eth_dev_set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, 3775 uint8_t stat_idx, uint8_t is_rx) 3776 { 3777 struct rte_eth_dev *dev; 3778 3779 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3780 dev = &rte_eth_devices[port_id]; 3781 3782 if (is_rx && (queue_id >= dev->data->nb_rx_queues)) 3783 return -EINVAL; 3784 3785 if (!is_rx && (queue_id >= dev->data->nb_tx_queues)) 3786 return -EINVAL; 3787 3788 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 3789 return -EINVAL; 3790 3791 if (*dev->dev_ops->queue_stats_mapping_set == NULL) 3792 return -ENOTSUP; 3793 return (*dev->dev_ops->queue_stats_mapping_set) (dev, queue_id, stat_idx, is_rx); 3794 } 3795 3796 int 3797 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id, 3798 uint8_t stat_idx) 3799 { 3800 int ret; 3801 3802 ret = eth_err(port_id, eth_dev_set_queue_stats_mapping(port_id, 3803 tx_queue_id, 3804 stat_idx, STAT_QMAP_TX)); 3805 3806 rte_ethdev_trace_set_tx_queue_stats_mapping(port_id, tx_queue_id, 3807 stat_idx, ret); 3808 3809 return ret; 3810 } 3811 3812 int 3813 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id, 3814 uint8_t stat_idx) 3815 { 3816 int ret; 3817 3818 ret = eth_err(port_id, eth_dev_set_queue_stats_mapping(port_id, 3819 rx_queue_id, 3820 stat_idx, STAT_QMAP_RX)); 3821 3822 rte_ethdev_trace_set_rx_queue_stats_mapping(port_id, rx_queue_id, 3823 stat_idx, ret); 3824 3825 return ret; 3826 } 3827 3828 int 3829 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size) 3830 { 3831 struct rte_eth_dev *dev; 3832 int ret; 3833 3834 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3835 dev = &rte_eth_devices[port_id]; 3836 3837 if (fw_version == NULL && fw_size > 0) { 3838 RTE_ETHDEV_LOG_LINE(ERR, 3839 "Cannot get ethdev port %u FW version to NULL when string size is non zero", 3840 port_id); 3841 return -EINVAL; 3842 } 3843 3844 if (*dev->dev_ops->fw_version_get == NULL) 3845 return -ENOTSUP; 3846 ret = eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev, 3847 fw_version, fw_size)); 3848 3849 rte_ethdev_trace_fw_version_get(port_id, fw_version, fw_size, ret); 3850 3851 return ret; 3852 } 3853 3854 int 3855 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info) 3856 { 3857 struct rte_eth_dev *dev; 3858 const struct rte_eth_desc_lim lim = { 3859 .nb_max = UINT16_MAX, 3860 .nb_min = 0, 3861 .nb_align = 1, 3862 .nb_seg_max = UINT16_MAX, 3863 .nb_mtu_seg_max = UINT16_MAX, 3864 }; 3865 int diag; 3866 3867 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3868 dev = &rte_eth_devices[port_id]; 3869 3870 if (dev_info == NULL) { 3871 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u info to NULL", 3872 port_id); 3873 return -EINVAL; 3874 } 3875 3876 /* 3877 * Init dev_info before port_id check since caller does not have 3878 * return status and does not know if get is successful or not. 3879 */ 3880 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 3881 dev_info->switch_info.domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 3882 3883 dev_info->rx_desc_lim = lim; 3884 dev_info->tx_desc_lim = lim; 3885 dev_info->device = dev->device; 3886 dev_info->min_mtu = RTE_ETHER_MIN_LEN - RTE_ETHER_HDR_LEN - 3887 RTE_ETHER_CRC_LEN; 3888 dev_info->max_mtu = UINT16_MAX; 3889 dev_info->rss_algo_capa = RTE_ETH_HASH_ALGO_CAPA_MASK(DEFAULT); 3890 dev_info->max_rx_bufsize = UINT32_MAX; 3891 3892 if (*dev->dev_ops->dev_infos_get == NULL) 3893 return -ENOTSUP; 3894 diag = (*dev->dev_ops->dev_infos_get)(dev, dev_info); 3895 if (diag != 0) { 3896 /* Cleanup already filled in device information */ 3897 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 3898 return eth_err(port_id, diag); 3899 } 3900 3901 /* Maximum number of queues should be <= RTE_MAX_QUEUES_PER_PORT */ 3902 dev_info->max_rx_queues = RTE_MIN(dev_info->max_rx_queues, 3903 RTE_MAX_QUEUES_PER_PORT); 3904 dev_info->max_tx_queues = RTE_MIN(dev_info->max_tx_queues, 3905 RTE_MAX_QUEUES_PER_PORT); 3906 3907 dev_info->driver_name = dev->device->driver->name; 3908 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3909 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3910 3911 dev_info->dev_flags = &dev->data->dev_flags; 3912 3913 rte_ethdev_trace_info_get(port_id, dev_info); 3914 3915 return 0; 3916 } 3917 3918 int 3919 rte_eth_dev_conf_get(uint16_t port_id, struct rte_eth_conf *dev_conf) 3920 { 3921 struct rte_eth_dev *dev; 3922 3923 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3924 dev = &rte_eth_devices[port_id]; 3925 3926 if (dev_conf == NULL) { 3927 RTE_ETHDEV_LOG_LINE(ERR, 3928 "Cannot get ethdev port %u configuration to NULL", 3929 port_id); 3930 return -EINVAL; 3931 } 3932 3933 memcpy(dev_conf, &dev->data->dev_conf, sizeof(struct rte_eth_conf)); 3934 3935 rte_ethdev_trace_conf_get(port_id, dev_conf); 3936 3937 return 0; 3938 } 3939 3940 int 3941 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask, 3942 uint32_t *ptypes, int num) 3943 { 3944 size_t i; 3945 int j; 3946 struct rte_eth_dev *dev; 3947 const uint32_t *all_ptypes; 3948 size_t no_of_elements = 0; 3949 3950 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3951 dev = &rte_eth_devices[port_id]; 3952 3953 if (ptypes == NULL && num > 0) { 3954 RTE_ETHDEV_LOG_LINE(ERR, 3955 "Cannot get ethdev port %u supported packet types to NULL when array size is non zero", 3956 port_id); 3957 return -EINVAL; 3958 } 3959 3960 if (*dev->dev_ops->dev_supported_ptypes_get == NULL) 3961 return 0; 3962 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev, 3963 &no_of_elements); 3964 3965 if (!all_ptypes) 3966 return 0; 3967 3968 for (i = 0, j = 0; i < no_of_elements; ++i) 3969 if (all_ptypes[i] & ptype_mask) { 3970 if (j < num) { 3971 ptypes[j] = all_ptypes[i]; 3972 3973 rte_ethdev_trace_get_supported_ptypes(port_id, 3974 j, num, ptypes[j]); 3975 } 3976 j++; 3977 } 3978 3979 return j; 3980 } 3981 3982 int 3983 rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask, 3984 uint32_t *set_ptypes, unsigned int num) 3985 { 3986 const uint32_t valid_ptype_masks[] = { 3987 RTE_PTYPE_L2_MASK, 3988 RTE_PTYPE_L3_MASK, 3989 RTE_PTYPE_L4_MASK, 3990 RTE_PTYPE_TUNNEL_MASK, 3991 RTE_PTYPE_INNER_L2_MASK, 3992 RTE_PTYPE_INNER_L3_MASK, 3993 RTE_PTYPE_INNER_L4_MASK, 3994 }; 3995 const uint32_t *all_ptypes; 3996 struct rte_eth_dev *dev; 3997 uint32_t unused_mask; 3998 size_t i; 3999 unsigned int j; 4000 int ret; 4001 size_t no_of_elements = 0; 4002 4003 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4004 dev = &rte_eth_devices[port_id]; 4005 4006 if (num > 0 && set_ptypes == NULL) { 4007 RTE_ETHDEV_LOG_LINE(ERR, 4008 "Cannot get ethdev port %u set packet types to NULL when array size is non zero", 4009 port_id); 4010 return -EINVAL; 4011 } 4012 4013 if (*dev->dev_ops->dev_supported_ptypes_get == NULL || 4014 *dev->dev_ops->dev_ptypes_set == NULL) { 4015 ret = 0; 4016 goto ptype_unknown; 4017 } 4018 4019 if (ptype_mask == 0) { 4020 ret = (*dev->dev_ops->dev_ptypes_set)(dev, 4021 ptype_mask); 4022 goto ptype_unknown; 4023 } 4024 4025 unused_mask = ptype_mask; 4026 for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) { 4027 uint32_t mask = ptype_mask & valid_ptype_masks[i]; 4028 if (mask && mask != valid_ptype_masks[i]) { 4029 ret = -EINVAL; 4030 goto ptype_unknown; 4031 } 4032 unused_mask &= ~valid_ptype_masks[i]; 4033 } 4034 4035 if (unused_mask) { 4036 ret = -EINVAL; 4037 goto ptype_unknown; 4038 } 4039 4040 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev, 4041 &no_of_elements); 4042 if (all_ptypes == NULL) { 4043 ret = 0; 4044 goto ptype_unknown; 4045 } 4046 4047 /* 4048 * Accommodate as many set_ptypes as possible. If the supplied 4049 * set_ptypes array is insufficient fill it partially. 4050 */ 4051 for (i = 0, j = 0; set_ptypes != NULL && 4052 (i < no_of_elements); ++i) { 4053 if (ptype_mask & all_ptypes[i]) { 4054 if (j < num - 1) { 4055 set_ptypes[j] = all_ptypes[i]; 4056 4057 rte_ethdev_trace_set_ptypes(port_id, j, num, 4058 set_ptypes[j]); 4059 4060 j++; 4061 continue; 4062 } 4063 break; 4064 } 4065 } 4066 4067 if (set_ptypes != NULL && j < num) 4068 set_ptypes[j] = RTE_PTYPE_UNKNOWN; 4069 4070 return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask); 4071 4072 ptype_unknown: 4073 if (num > 0) 4074 set_ptypes[0] = RTE_PTYPE_UNKNOWN; 4075 4076 return ret; 4077 } 4078 4079 int 4080 rte_eth_macaddrs_get(uint16_t port_id, struct rte_ether_addr *ma, 4081 unsigned int num) 4082 { 4083 int32_t ret; 4084 struct rte_eth_dev *dev; 4085 struct rte_eth_dev_info dev_info; 4086 4087 if (ma == NULL) { 4088 RTE_ETHDEV_LOG_LINE(ERR, "%s: invalid parameters", __func__); 4089 return -EINVAL; 4090 } 4091 4092 /* will check for us that port_id is a valid one */ 4093 ret = rte_eth_dev_info_get(port_id, &dev_info); 4094 if (ret != 0) 4095 return ret; 4096 4097 dev = &rte_eth_devices[port_id]; 4098 num = RTE_MIN(dev_info.max_mac_addrs, num); 4099 memcpy(ma, dev->data->mac_addrs, num * sizeof(ma[0])); 4100 4101 rte_eth_trace_macaddrs_get(port_id, num); 4102 4103 return num; 4104 } 4105 4106 int 4107 rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr) 4108 { 4109 struct rte_eth_dev *dev; 4110 4111 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4112 dev = &rte_eth_devices[port_id]; 4113 4114 if (mac_addr == NULL) { 4115 RTE_ETHDEV_LOG_LINE(ERR, 4116 "Cannot get ethdev port %u MAC address to NULL", 4117 port_id); 4118 return -EINVAL; 4119 } 4120 4121 rte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr); 4122 4123 rte_eth_trace_macaddr_get(port_id, mac_addr); 4124 4125 return 0; 4126 } 4127 4128 int 4129 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu) 4130 { 4131 struct rte_eth_dev *dev; 4132 4133 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4134 dev = &rte_eth_devices[port_id]; 4135 4136 if (mtu == NULL) { 4137 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u MTU to NULL", 4138 port_id); 4139 return -EINVAL; 4140 } 4141 4142 *mtu = dev->data->mtu; 4143 4144 rte_ethdev_trace_get_mtu(port_id, *mtu); 4145 4146 return 0; 4147 } 4148 4149 int 4150 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu) 4151 { 4152 int ret; 4153 struct rte_eth_dev_info dev_info; 4154 struct rte_eth_dev *dev; 4155 4156 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4157 dev = &rte_eth_devices[port_id]; 4158 if (*dev->dev_ops->mtu_set == NULL) 4159 return -ENOTSUP; 4160 4161 /* 4162 * Check if the device supports dev_infos_get, if it does not 4163 * skip min_mtu/max_mtu validation here as this requires values 4164 * that are populated within the call to rte_eth_dev_info_get() 4165 * which relies on dev->dev_ops->dev_infos_get. 4166 */ 4167 if (*dev->dev_ops->dev_infos_get != NULL) { 4168 ret = rte_eth_dev_info_get(port_id, &dev_info); 4169 if (ret != 0) 4170 return ret; 4171 4172 ret = eth_dev_validate_mtu(port_id, &dev_info, mtu); 4173 if (ret != 0) 4174 return ret; 4175 } 4176 4177 if (dev->data->dev_configured == 0) { 4178 RTE_ETHDEV_LOG_LINE(ERR, 4179 "Port %u must be configured before MTU set", 4180 port_id); 4181 return -EINVAL; 4182 } 4183 4184 ret = (*dev->dev_ops->mtu_set)(dev, mtu); 4185 if (ret == 0) 4186 dev->data->mtu = mtu; 4187 4188 ret = eth_err(port_id, ret); 4189 4190 rte_ethdev_trace_set_mtu(port_id, mtu, ret); 4191 4192 return ret; 4193 } 4194 4195 int 4196 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on) 4197 { 4198 struct rte_eth_dev *dev; 4199 int ret; 4200 4201 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4202 dev = &rte_eth_devices[port_id]; 4203 4204 if (!(dev->data->dev_conf.rxmode.offloads & 4205 RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) { 4206 RTE_ETHDEV_LOG_LINE(ERR, "Port %u: VLAN-filtering disabled", 4207 port_id); 4208 return -ENOSYS; 4209 } 4210 4211 if (vlan_id > 4095) { 4212 RTE_ETHDEV_LOG_LINE(ERR, "Port_id=%u invalid vlan_id=%u > 4095", 4213 port_id, vlan_id); 4214 return -EINVAL; 4215 } 4216 if (*dev->dev_ops->vlan_filter_set == NULL) 4217 return -ENOTSUP; 4218 4219 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on); 4220 if (ret == 0) { 4221 struct rte_vlan_filter_conf *vfc; 4222 int vidx; 4223 int vbit; 4224 4225 vfc = &dev->data->vlan_filter_conf; 4226 vidx = vlan_id / 64; 4227 vbit = vlan_id % 64; 4228 4229 if (on) 4230 vfc->ids[vidx] |= RTE_BIT64(vbit); 4231 else 4232 vfc->ids[vidx] &= ~RTE_BIT64(vbit); 4233 } 4234 4235 ret = eth_err(port_id, ret); 4236 4237 rte_ethdev_trace_vlan_filter(port_id, vlan_id, on, ret); 4238 4239 return ret; 4240 } 4241 4242 int 4243 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id, 4244 int on) 4245 { 4246 struct rte_eth_dev *dev; 4247 4248 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4249 dev = &rte_eth_devices[port_id]; 4250 4251 if (rx_queue_id >= dev->data->nb_rx_queues) { 4252 RTE_ETHDEV_LOG_LINE(ERR, "Invalid rx_queue_id=%u", rx_queue_id); 4253 return -EINVAL; 4254 } 4255 4256 if (*dev->dev_ops->vlan_strip_queue_set == NULL) 4257 return -ENOTSUP; 4258 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on); 4259 4260 rte_ethdev_trace_set_vlan_strip_on_queue(port_id, rx_queue_id, on); 4261 4262 return 0; 4263 } 4264 4265 int 4266 rte_eth_dev_set_vlan_ether_type(uint16_t port_id, 4267 enum rte_vlan_type vlan_type, 4268 uint16_t tpid) 4269 { 4270 struct rte_eth_dev *dev; 4271 int ret; 4272 4273 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4274 dev = &rte_eth_devices[port_id]; 4275 4276 if (*dev->dev_ops->vlan_tpid_set == NULL) 4277 return -ENOTSUP; 4278 ret = eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type, 4279 tpid)); 4280 4281 rte_ethdev_trace_set_vlan_ether_type(port_id, vlan_type, tpid, ret); 4282 4283 return ret; 4284 } 4285 4286 int 4287 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask) 4288 { 4289 struct rte_eth_dev_info dev_info; 4290 struct rte_eth_dev *dev; 4291 int ret = 0; 4292 int mask = 0; 4293 int cur, org = 0; 4294 uint64_t orig_offloads; 4295 uint64_t dev_offloads; 4296 uint64_t new_offloads; 4297 4298 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4299 dev = &rte_eth_devices[port_id]; 4300 4301 /* save original values in case of failure */ 4302 orig_offloads = dev->data->dev_conf.rxmode.offloads; 4303 dev_offloads = orig_offloads; 4304 4305 /* check which option changed by application */ 4306 cur = !!(offload_mask & RTE_ETH_VLAN_STRIP_OFFLOAD); 4307 org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); 4308 if (cur != org) { 4309 if (cur) 4310 dev_offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 4311 else 4312 dev_offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 4313 mask |= RTE_ETH_VLAN_STRIP_MASK; 4314 } 4315 4316 cur = !!(offload_mask & RTE_ETH_VLAN_FILTER_OFFLOAD); 4317 org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER); 4318 if (cur != org) { 4319 if (cur) 4320 dev_offloads |= RTE_ETH_RX_OFFLOAD_VLAN_FILTER; 4321 else 4322 dev_offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_FILTER; 4323 mask |= RTE_ETH_VLAN_FILTER_MASK; 4324 } 4325 4326 cur = !!(offload_mask & RTE_ETH_VLAN_EXTEND_OFFLOAD); 4327 org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND); 4328 if (cur != org) { 4329 if (cur) 4330 dev_offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; 4331 else 4332 dev_offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; 4333 mask |= RTE_ETH_VLAN_EXTEND_MASK; 4334 } 4335 4336 cur = !!(offload_mask & RTE_ETH_QINQ_STRIP_OFFLOAD); 4337 org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP); 4338 if (cur != org) { 4339 if (cur) 4340 dev_offloads |= RTE_ETH_RX_OFFLOAD_QINQ_STRIP; 4341 else 4342 dev_offloads &= ~RTE_ETH_RX_OFFLOAD_QINQ_STRIP; 4343 mask |= RTE_ETH_QINQ_STRIP_MASK; 4344 } 4345 4346 /*no change*/ 4347 if (mask == 0) 4348 return ret; 4349 4350 ret = rte_eth_dev_info_get(port_id, &dev_info); 4351 if (ret != 0) 4352 return ret; 4353 4354 /* Rx VLAN offloading must be within its device capabilities */ 4355 if ((dev_offloads & dev_info.rx_offload_capa) != dev_offloads) { 4356 new_offloads = dev_offloads & ~orig_offloads; 4357 RTE_ETHDEV_LOG_LINE(ERR, 4358 "Ethdev port_id=%u requested new added VLAN offloads " 4359 "0x%" PRIx64 " must be within Rx offloads capabilities " 4360 "0x%" PRIx64 " in %s()", 4361 port_id, new_offloads, dev_info.rx_offload_capa, 4362 __func__); 4363 return -EINVAL; 4364 } 4365 4366 if (*dev->dev_ops->vlan_offload_set == NULL) 4367 return -ENOTSUP; 4368 dev->data->dev_conf.rxmode.offloads = dev_offloads; 4369 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask); 4370 if (ret) { 4371 /* hit an error restore original values */ 4372 dev->data->dev_conf.rxmode.offloads = orig_offloads; 4373 } 4374 4375 ret = eth_err(port_id, ret); 4376 4377 rte_ethdev_trace_set_vlan_offload(port_id, offload_mask, ret); 4378 4379 return ret; 4380 } 4381 4382 int 4383 rte_eth_dev_get_vlan_offload(uint16_t port_id) 4384 { 4385 struct rte_eth_dev *dev; 4386 uint64_t *dev_offloads; 4387 int ret = 0; 4388 4389 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4390 dev = &rte_eth_devices[port_id]; 4391 dev_offloads = &dev->data->dev_conf.rxmode.offloads; 4392 4393 if (*dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 4394 ret |= RTE_ETH_VLAN_STRIP_OFFLOAD; 4395 4396 if (*dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 4397 ret |= RTE_ETH_VLAN_FILTER_OFFLOAD; 4398 4399 if (*dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 4400 ret |= RTE_ETH_VLAN_EXTEND_OFFLOAD; 4401 4402 if (*dev_offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) 4403 ret |= RTE_ETH_QINQ_STRIP_OFFLOAD; 4404 4405 rte_ethdev_trace_get_vlan_offload(port_id, ret); 4406 4407 return ret; 4408 } 4409 4410 int 4411 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on) 4412 { 4413 struct rte_eth_dev *dev; 4414 int ret; 4415 4416 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4417 dev = &rte_eth_devices[port_id]; 4418 4419 if (*dev->dev_ops->vlan_pvid_set == NULL) 4420 return -ENOTSUP; 4421 ret = eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on)); 4422 4423 rte_ethdev_trace_set_vlan_pvid(port_id, pvid, on, ret); 4424 4425 return ret; 4426 } 4427 4428 int 4429 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 4430 { 4431 struct rte_eth_dev *dev; 4432 int ret; 4433 4434 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4435 dev = &rte_eth_devices[port_id]; 4436 4437 if (fc_conf == NULL) { 4438 RTE_ETHDEV_LOG_LINE(ERR, 4439 "Cannot get ethdev port %u flow control config to NULL", 4440 port_id); 4441 return -EINVAL; 4442 } 4443 4444 if (*dev->dev_ops->flow_ctrl_get == NULL) 4445 return -ENOTSUP; 4446 memset(fc_conf, 0, sizeof(*fc_conf)); 4447 ret = eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf)); 4448 4449 rte_ethdev_trace_flow_ctrl_get(port_id, fc_conf, ret); 4450 4451 return ret; 4452 } 4453 4454 int 4455 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 4456 { 4457 struct rte_eth_dev *dev; 4458 int ret; 4459 4460 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4461 dev = &rte_eth_devices[port_id]; 4462 4463 if (fc_conf == NULL) { 4464 RTE_ETHDEV_LOG_LINE(ERR, 4465 "Cannot set ethdev port %u flow control from NULL config", 4466 port_id); 4467 return -EINVAL; 4468 } 4469 4470 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) { 4471 RTE_ETHDEV_LOG_LINE(ERR, "Invalid send_xon, only 0/1 allowed"); 4472 return -EINVAL; 4473 } 4474 4475 if (*dev->dev_ops->flow_ctrl_set == NULL) 4476 return -ENOTSUP; 4477 ret = eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf)); 4478 4479 rte_ethdev_trace_flow_ctrl_set(port_id, fc_conf, ret); 4480 4481 return ret; 4482 } 4483 4484 int 4485 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, 4486 struct rte_eth_pfc_conf *pfc_conf) 4487 { 4488 struct rte_eth_dev *dev; 4489 int ret; 4490 4491 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4492 dev = &rte_eth_devices[port_id]; 4493 4494 if (pfc_conf == NULL) { 4495 RTE_ETHDEV_LOG_LINE(ERR, 4496 "Cannot set ethdev port %u priority flow control from NULL config", 4497 port_id); 4498 return -EINVAL; 4499 } 4500 4501 if (pfc_conf->priority > (RTE_ETH_DCB_NUM_USER_PRIORITIES - 1)) { 4502 RTE_ETHDEV_LOG_LINE(ERR, "Invalid priority, only 0-7 allowed"); 4503 return -EINVAL; 4504 } 4505 4506 /* High water, low water validation are device specific */ 4507 if (*dev->dev_ops->priority_flow_ctrl_set == NULL) 4508 return -ENOTSUP; 4509 ret = eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set) 4510 (dev, pfc_conf)); 4511 4512 rte_ethdev_trace_priority_flow_ctrl_set(port_id, pfc_conf, ret); 4513 4514 return ret; 4515 } 4516 4517 static int 4518 validate_rx_pause_config(struct rte_eth_dev_info *dev_info, uint8_t tc_max, 4519 struct rte_eth_pfc_queue_conf *pfc_queue_conf) 4520 { 4521 if ((pfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) || 4522 (pfc_queue_conf->mode == RTE_ETH_FC_FULL)) { 4523 if (pfc_queue_conf->rx_pause.tx_qid >= dev_info->nb_tx_queues) { 4524 RTE_ETHDEV_LOG_LINE(ERR, 4525 "PFC Tx queue not in range for Rx pause requested:%d configured:%d", 4526 pfc_queue_conf->rx_pause.tx_qid, 4527 dev_info->nb_tx_queues); 4528 return -EINVAL; 4529 } 4530 4531 if (pfc_queue_conf->rx_pause.tc >= tc_max) { 4532 RTE_ETHDEV_LOG_LINE(ERR, 4533 "PFC TC not in range for Rx pause requested:%d max:%d", 4534 pfc_queue_conf->rx_pause.tc, tc_max); 4535 return -EINVAL; 4536 } 4537 } 4538 4539 return 0; 4540 } 4541 4542 static int 4543 validate_tx_pause_config(struct rte_eth_dev_info *dev_info, uint8_t tc_max, 4544 struct rte_eth_pfc_queue_conf *pfc_queue_conf) 4545 { 4546 if ((pfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) || 4547 (pfc_queue_conf->mode == RTE_ETH_FC_FULL)) { 4548 if (pfc_queue_conf->tx_pause.rx_qid >= dev_info->nb_rx_queues) { 4549 RTE_ETHDEV_LOG_LINE(ERR, 4550 "PFC Rx queue not in range for Tx pause requested:%d configured:%d", 4551 pfc_queue_conf->tx_pause.rx_qid, 4552 dev_info->nb_rx_queues); 4553 return -EINVAL; 4554 } 4555 4556 if (pfc_queue_conf->tx_pause.tc >= tc_max) { 4557 RTE_ETHDEV_LOG_LINE(ERR, 4558 "PFC TC not in range for Tx pause requested:%d max:%d", 4559 pfc_queue_conf->tx_pause.tc, tc_max); 4560 return -EINVAL; 4561 } 4562 } 4563 4564 return 0; 4565 } 4566 4567 int 4568 rte_eth_dev_priority_flow_ctrl_queue_info_get(uint16_t port_id, 4569 struct rte_eth_pfc_queue_info *pfc_queue_info) 4570 { 4571 struct rte_eth_dev *dev; 4572 int ret; 4573 4574 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4575 dev = &rte_eth_devices[port_id]; 4576 4577 if (pfc_queue_info == NULL) { 4578 RTE_ETHDEV_LOG_LINE(ERR, "PFC info param is NULL for port (%u)", 4579 port_id); 4580 return -EINVAL; 4581 } 4582 4583 if (*dev->dev_ops->priority_flow_ctrl_queue_info_get == NULL) 4584 return -ENOTSUP; 4585 ret = eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_info_get) 4586 (dev, pfc_queue_info)); 4587 4588 rte_ethdev_trace_priority_flow_ctrl_queue_info_get(port_id, 4589 pfc_queue_info, ret); 4590 4591 return ret; 4592 } 4593 4594 int 4595 rte_eth_dev_priority_flow_ctrl_queue_configure(uint16_t port_id, 4596 struct rte_eth_pfc_queue_conf *pfc_queue_conf) 4597 { 4598 struct rte_eth_pfc_queue_info pfc_info; 4599 struct rte_eth_dev_info dev_info; 4600 struct rte_eth_dev *dev; 4601 int ret; 4602 4603 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4604 dev = &rte_eth_devices[port_id]; 4605 4606 if (pfc_queue_conf == NULL) { 4607 RTE_ETHDEV_LOG_LINE(ERR, "PFC parameters are NULL for port (%u)", 4608 port_id); 4609 return -EINVAL; 4610 } 4611 4612 ret = rte_eth_dev_info_get(port_id, &dev_info); 4613 if (ret != 0) 4614 return ret; 4615 4616 ret = rte_eth_dev_priority_flow_ctrl_queue_info_get(port_id, &pfc_info); 4617 if (ret != 0) 4618 return ret; 4619 4620 if (pfc_info.tc_max == 0) { 4621 RTE_ETHDEV_LOG_LINE(ERR, "Ethdev port %u does not support PFC TC values", 4622 port_id); 4623 return -ENOTSUP; 4624 } 4625 4626 /* Check requested mode supported or not */ 4627 if (pfc_info.mode_capa == RTE_ETH_FC_RX_PAUSE && 4628 pfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) { 4629 RTE_ETHDEV_LOG_LINE(ERR, "PFC Tx pause unsupported for port (%d)", 4630 port_id); 4631 return -EINVAL; 4632 } 4633 4634 if (pfc_info.mode_capa == RTE_ETH_FC_TX_PAUSE && 4635 pfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) { 4636 RTE_ETHDEV_LOG_LINE(ERR, "PFC Rx pause unsupported for port (%d)", 4637 port_id); 4638 return -EINVAL; 4639 } 4640 4641 /* Validate Rx pause parameters */ 4642 if (pfc_info.mode_capa == RTE_ETH_FC_FULL || 4643 pfc_info.mode_capa == RTE_ETH_FC_RX_PAUSE) { 4644 ret = validate_rx_pause_config(&dev_info, pfc_info.tc_max, 4645 pfc_queue_conf); 4646 if (ret != 0) 4647 return ret; 4648 } 4649 4650 /* Validate Tx pause parameters */ 4651 if (pfc_info.mode_capa == RTE_ETH_FC_FULL || 4652 pfc_info.mode_capa == RTE_ETH_FC_TX_PAUSE) { 4653 ret = validate_tx_pause_config(&dev_info, pfc_info.tc_max, 4654 pfc_queue_conf); 4655 if (ret != 0) 4656 return ret; 4657 } 4658 4659 if (*dev->dev_ops->priority_flow_ctrl_queue_config == NULL) 4660 return -ENOTSUP; 4661 ret = eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_config) 4662 (dev, pfc_queue_conf)); 4663 4664 rte_ethdev_trace_priority_flow_ctrl_queue_configure(port_id, 4665 pfc_queue_conf, ret); 4666 4667 return ret; 4668 } 4669 4670 static int 4671 eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf, 4672 uint16_t reta_size) 4673 { 4674 uint16_t i, num; 4675 4676 num = (reta_size + RTE_ETH_RETA_GROUP_SIZE - 1) / RTE_ETH_RETA_GROUP_SIZE; 4677 for (i = 0; i < num; i++) { 4678 if (reta_conf[i].mask) 4679 return 0; 4680 } 4681 4682 return -EINVAL; 4683 } 4684 4685 static int 4686 eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf, 4687 uint16_t reta_size, 4688 uint16_t max_rxq) 4689 { 4690 uint16_t i, idx, shift; 4691 4692 if (max_rxq == 0) { 4693 RTE_ETHDEV_LOG_LINE(ERR, "No receive queue is available"); 4694 return -EINVAL; 4695 } 4696 4697 for (i = 0; i < reta_size; i++) { 4698 idx = i / RTE_ETH_RETA_GROUP_SIZE; 4699 shift = i % RTE_ETH_RETA_GROUP_SIZE; 4700 if ((reta_conf[idx].mask & RTE_BIT64(shift)) && 4701 (reta_conf[idx].reta[shift] >= max_rxq)) { 4702 RTE_ETHDEV_LOG_LINE(ERR, 4703 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u", 4704 idx, shift, 4705 reta_conf[idx].reta[shift], max_rxq); 4706 return -EINVAL; 4707 } 4708 } 4709 4710 return 0; 4711 } 4712 4713 int 4714 rte_eth_dev_rss_reta_update(uint16_t port_id, 4715 struct rte_eth_rss_reta_entry64 *reta_conf, 4716 uint16_t reta_size) 4717 { 4718 enum rte_eth_rx_mq_mode mq_mode; 4719 struct rte_eth_dev *dev; 4720 int ret; 4721 4722 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4723 dev = &rte_eth_devices[port_id]; 4724 4725 if (reta_conf == NULL) { 4726 RTE_ETHDEV_LOG_LINE(ERR, 4727 "Cannot update ethdev port %u RSS RETA to NULL", 4728 port_id); 4729 return -EINVAL; 4730 } 4731 4732 if (reta_size == 0) { 4733 RTE_ETHDEV_LOG_LINE(ERR, 4734 "Cannot update ethdev port %u RSS RETA with zero size", 4735 port_id); 4736 return -EINVAL; 4737 } 4738 4739 /* Check mask bits */ 4740 ret = eth_check_reta_mask(reta_conf, reta_size); 4741 if (ret < 0) 4742 return ret; 4743 4744 /* Check entry value */ 4745 ret = eth_check_reta_entry(reta_conf, reta_size, 4746 dev->data->nb_rx_queues); 4747 if (ret < 0) 4748 return ret; 4749 4750 mq_mode = dev->data->dev_conf.rxmode.mq_mode; 4751 if (!(mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) { 4752 RTE_ETHDEV_LOG_LINE(ERR, "Multi-queue RSS mode isn't enabled."); 4753 return -ENOTSUP; 4754 } 4755 4756 if (*dev->dev_ops->reta_update == NULL) 4757 return -ENOTSUP; 4758 ret = eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf, 4759 reta_size)); 4760 4761 rte_ethdev_trace_rss_reta_update(port_id, reta_conf, reta_size, ret); 4762 4763 return ret; 4764 } 4765 4766 int 4767 rte_eth_dev_rss_reta_query(uint16_t port_id, 4768 struct rte_eth_rss_reta_entry64 *reta_conf, 4769 uint16_t reta_size) 4770 { 4771 struct rte_eth_dev *dev; 4772 int ret; 4773 4774 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4775 dev = &rte_eth_devices[port_id]; 4776 4777 if (reta_conf == NULL) { 4778 RTE_ETHDEV_LOG_LINE(ERR, 4779 "Cannot query ethdev port %u RSS RETA from NULL config", 4780 port_id); 4781 return -EINVAL; 4782 } 4783 4784 /* Check mask bits */ 4785 ret = eth_check_reta_mask(reta_conf, reta_size); 4786 if (ret < 0) 4787 return ret; 4788 4789 if (*dev->dev_ops->reta_query == NULL) 4790 return -ENOTSUP; 4791 ret = eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf, 4792 reta_size)); 4793 4794 rte_ethdev_trace_rss_reta_query(port_id, reta_conf, reta_size, ret); 4795 4796 return ret; 4797 } 4798 4799 int 4800 rte_eth_dev_rss_hash_update(uint16_t port_id, 4801 struct rte_eth_rss_conf *rss_conf) 4802 { 4803 struct rte_eth_dev *dev; 4804 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, }; 4805 enum rte_eth_rx_mq_mode mq_mode; 4806 int ret; 4807 4808 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4809 dev = &rte_eth_devices[port_id]; 4810 4811 if (rss_conf == NULL) { 4812 RTE_ETHDEV_LOG_LINE(ERR, 4813 "Cannot update ethdev port %u RSS hash from NULL config", 4814 port_id); 4815 return -EINVAL; 4816 } 4817 4818 ret = rte_eth_dev_info_get(port_id, &dev_info); 4819 if (ret != 0) 4820 return ret; 4821 4822 rss_conf->rss_hf = rte_eth_rss_hf_refine(rss_conf->rss_hf); 4823 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) != 4824 dev_info.flow_type_rss_offloads) { 4825 RTE_ETHDEV_LOG_LINE(ERR, 4826 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64, 4827 port_id, rss_conf->rss_hf, 4828 dev_info.flow_type_rss_offloads); 4829 return -EINVAL; 4830 } 4831 4832 mq_mode = dev->data->dev_conf.rxmode.mq_mode; 4833 if (!(mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) { 4834 RTE_ETHDEV_LOG_LINE(ERR, "Multi-queue RSS mode isn't enabled."); 4835 return -ENOTSUP; 4836 } 4837 4838 if (rss_conf->rss_key != NULL && 4839 rss_conf->rss_key_len != dev_info.hash_key_size) { 4840 RTE_ETHDEV_LOG_LINE(ERR, 4841 "Ethdev port_id=%u invalid RSS key len: %u, valid value: %u", 4842 port_id, rss_conf->rss_key_len, dev_info.hash_key_size); 4843 return -EINVAL; 4844 } 4845 4846 if ((size_t)rss_conf->algorithm >= CHAR_BIT * sizeof(dev_info.rss_algo_capa) || 4847 (dev_info.rss_algo_capa & 4848 RTE_ETH_HASH_ALGO_TO_CAPA(rss_conf->algorithm)) == 0) { 4849 RTE_ETHDEV_LOG_LINE(ERR, 4850 "Ethdev port_id=%u configured RSS hash algorithm (%u)" 4851 "is not in the algorithm capability (0x%" PRIx32 ")", 4852 port_id, rss_conf->algorithm, dev_info.rss_algo_capa); 4853 return -EINVAL; 4854 } 4855 4856 if (*dev->dev_ops->rss_hash_update == NULL) 4857 return -ENOTSUP; 4858 ret = eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev, 4859 rss_conf)); 4860 4861 rte_ethdev_trace_rss_hash_update(port_id, rss_conf, ret); 4862 4863 return ret; 4864 } 4865 4866 int 4867 rte_eth_dev_rss_hash_conf_get(uint16_t port_id, 4868 struct rte_eth_rss_conf *rss_conf) 4869 { 4870 struct rte_eth_dev_info dev_info = { 0 }; 4871 struct rte_eth_dev *dev; 4872 int ret; 4873 4874 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4875 dev = &rte_eth_devices[port_id]; 4876 4877 if (rss_conf == NULL) { 4878 RTE_ETHDEV_LOG_LINE(ERR, 4879 "Cannot get ethdev port %u RSS hash config to NULL", 4880 port_id); 4881 return -EINVAL; 4882 } 4883 4884 ret = rte_eth_dev_info_get(port_id, &dev_info); 4885 if (ret != 0) 4886 return ret; 4887 4888 if (rss_conf->rss_key != NULL && 4889 rss_conf->rss_key_len < dev_info.hash_key_size) { 4890 RTE_ETHDEV_LOG_LINE(ERR, 4891 "Ethdev port_id=%u invalid RSS key len: %u, should not be less than: %u", 4892 port_id, rss_conf->rss_key_len, dev_info.hash_key_size); 4893 return -EINVAL; 4894 } 4895 4896 rss_conf->algorithm = RTE_ETH_HASH_FUNCTION_DEFAULT; 4897 4898 if (*dev->dev_ops->rss_hash_conf_get == NULL) 4899 return -ENOTSUP; 4900 ret = eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev, 4901 rss_conf)); 4902 4903 rte_ethdev_trace_rss_hash_conf_get(port_id, rss_conf, ret); 4904 4905 return ret; 4906 } 4907 4908 const char * 4909 rte_eth_dev_rss_algo_name(enum rte_eth_hash_function rss_algo) 4910 { 4911 const char *name = "Unknown function"; 4912 unsigned int i; 4913 4914 for (i = 0; i < RTE_DIM(rte_eth_dev_rss_algo_names); i++) { 4915 if (rss_algo == rte_eth_dev_rss_algo_names[i].algo) 4916 return rte_eth_dev_rss_algo_names[i].name; 4917 } 4918 4919 return name; 4920 } 4921 4922 int 4923 rte_eth_find_rss_algo(const char *name, uint32_t *algo) 4924 { 4925 unsigned int i; 4926 4927 for (i = 0; i < RTE_DIM(rte_eth_dev_rss_algo_names); i++) { 4928 if (strcmp(name, rte_eth_dev_rss_algo_names[i].name) == 0) { 4929 *algo = rte_eth_dev_rss_algo_names[i].algo; 4930 return 0; 4931 } 4932 } 4933 4934 return -EINVAL; 4935 } 4936 4937 int 4938 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id, 4939 struct rte_eth_udp_tunnel *udp_tunnel) 4940 { 4941 struct rte_eth_dev *dev; 4942 int ret; 4943 4944 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4945 dev = &rte_eth_devices[port_id]; 4946 4947 if (udp_tunnel == NULL) { 4948 RTE_ETHDEV_LOG_LINE(ERR, 4949 "Cannot add ethdev port %u UDP tunnel port from NULL UDP tunnel", 4950 port_id); 4951 return -EINVAL; 4952 } 4953 4954 if (udp_tunnel->prot_type >= RTE_ETH_TUNNEL_TYPE_MAX) { 4955 RTE_ETHDEV_LOG_LINE(ERR, "Invalid tunnel type"); 4956 return -EINVAL; 4957 } 4958 4959 if (*dev->dev_ops->udp_tunnel_port_add == NULL) 4960 return -ENOTSUP; 4961 ret = eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev, 4962 udp_tunnel)); 4963 4964 rte_ethdev_trace_udp_tunnel_port_add(port_id, udp_tunnel, ret); 4965 4966 return ret; 4967 } 4968 4969 int 4970 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, 4971 struct rte_eth_udp_tunnel *udp_tunnel) 4972 { 4973 struct rte_eth_dev *dev; 4974 int ret; 4975 4976 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4977 dev = &rte_eth_devices[port_id]; 4978 4979 if (udp_tunnel == NULL) { 4980 RTE_ETHDEV_LOG_LINE(ERR, 4981 "Cannot delete ethdev port %u UDP tunnel port from NULL UDP tunnel", 4982 port_id); 4983 return -EINVAL; 4984 } 4985 4986 if (udp_tunnel->prot_type >= RTE_ETH_TUNNEL_TYPE_MAX) { 4987 RTE_ETHDEV_LOG_LINE(ERR, "Invalid tunnel type"); 4988 return -EINVAL; 4989 } 4990 4991 if (*dev->dev_ops->udp_tunnel_port_del == NULL) 4992 return -ENOTSUP; 4993 ret = eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev, 4994 udp_tunnel)); 4995 4996 rte_ethdev_trace_udp_tunnel_port_delete(port_id, udp_tunnel, ret); 4997 4998 return ret; 4999 } 5000 5001 int 5002 rte_eth_led_on(uint16_t port_id) 5003 { 5004 struct rte_eth_dev *dev; 5005 int ret; 5006 5007 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5008 dev = &rte_eth_devices[port_id]; 5009 5010 if (*dev->dev_ops->dev_led_on == NULL) 5011 return -ENOTSUP; 5012 ret = eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev)); 5013 5014 rte_eth_trace_led_on(port_id, ret); 5015 5016 return ret; 5017 } 5018 5019 int 5020 rte_eth_led_off(uint16_t port_id) 5021 { 5022 struct rte_eth_dev *dev; 5023 int ret; 5024 5025 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5026 dev = &rte_eth_devices[port_id]; 5027 5028 if (*dev->dev_ops->dev_led_off == NULL) 5029 return -ENOTSUP; 5030 ret = eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev)); 5031 5032 rte_eth_trace_led_off(port_id, ret); 5033 5034 return ret; 5035 } 5036 5037 int 5038 rte_eth_fec_get_capability(uint16_t port_id, 5039 struct rte_eth_fec_capa *speed_fec_capa, 5040 unsigned int num) 5041 { 5042 struct rte_eth_dev *dev; 5043 int ret; 5044 5045 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5046 dev = &rte_eth_devices[port_id]; 5047 5048 if (speed_fec_capa == NULL && num > 0) { 5049 RTE_ETHDEV_LOG_LINE(ERR, 5050 "Cannot get ethdev port %u FEC capability to NULL when array size is non zero", 5051 port_id); 5052 return -EINVAL; 5053 } 5054 5055 if (*dev->dev_ops->fec_get_capability == NULL) 5056 return -ENOTSUP; 5057 ret = (*dev->dev_ops->fec_get_capability)(dev, speed_fec_capa, num); 5058 5059 rte_eth_trace_fec_get_capability(port_id, speed_fec_capa, num, ret); 5060 5061 return ret; 5062 } 5063 5064 int 5065 rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa) 5066 { 5067 struct rte_eth_dev *dev; 5068 int ret; 5069 5070 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5071 dev = &rte_eth_devices[port_id]; 5072 5073 if (fec_capa == NULL) { 5074 RTE_ETHDEV_LOG_LINE(ERR, 5075 "Cannot get ethdev port %u current FEC mode to NULL", 5076 port_id); 5077 return -EINVAL; 5078 } 5079 5080 if (*dev->dev_ops->fec_get == NULL) 5081 return -ENOTSUP; 5082 ret = eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa)); 5083 5084 rte_eth_trace_fec_get(port_id, fec_capa, ret); 5085 5086 return ret; 5087 } 5088 5089 int 5090 rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa) 5091 { 5092 struct rte_eth_dev *dev; 5093 int ret; 5094 5095 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5096 dev = &rte_eth_devices[port_id]; 5097 5098 if (fec_capa == 0) { 5099 RTE_ETHDEV_LOG_LINE(ERR, "At least one FEC mode should be specified"); 5100 return -EINVAL; 5101 } 5102 5103 if (*dev->dev_ops->fec_set == NULL) 5104 return -ENOTSUP; 5105 ret = eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa)); 5106 5107 rte_eth_trace_fec_set(port_id, fec_capa, ret); 5108 5109 return ret; 5110 } 5111 5112 /* 5113 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 5114 * an empty spot. 5115 */ 5116 static int 5117 eth_dev_get_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr) 5118 { 5119 struct rte_eth_dev_info dev_info; 5120 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 5121 unsigned i; 5122 int ret; 5123 5124 ret = rte_eth_dev_info_get(port_id, &dev_info); 5125 if (ret != 0) 5126 return -1; 5127 5128 for (i = 0; i < dev_info.max_mac_addrs; i++) 5129 if (memcmp(addr, &dev->data->mac_addrs[i], 5130 RTE_ETHER_ADDR_LEN) == 0) 5131 return i; 5132 5133 return -1; 5134 } 5135 5136 static const struct rte_ether_addr null_mac_addr; 5137 5138 int 5139 rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr, 5140 uint32_t pool) 5141 { 5142 struct rte_eth_dev *dev; 5143 int index; 5144 uint64_t pool_mask; 5145 int ret; 5146 5147 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5148 dev = &rte_eth_devices[port_id]; 5149 5150 if (addr == NULL) { 5151 RTE_ETHDEV_LOG_LINE(ERR, 5152 "Cannot add ethdev port %u MAC address from NULL address", 5153 port_id); 5154 return -EINVAL; 5155 } 5156 5157 if (*dev->dev_ops->mac_addr_add == NULL) 5158 return -ENOTSUP; 5159 5160 if (rte_is_zero_ether_addr(addr)) { 5161 RTE_ETHDEV_LOG_LINE(ERR, "Port %u: Cannot add NULL MAC address", 5162 port_id); 5163 return -EINVAL; 5164 } 5165 if (pool >= RTE_ETH_64_POOLS) { 5166 RTE_ETHDEV_LOG_LINE(ERR, "Pool ID must be 0-%d", RTE_ETH_64_POOLS - 1); 5167 return -EINVAL; 5168 } 5169 5170 index = eth_dev_get_mac_addr_index(port_id, addr); 5171 if (index < 0) { 5172 index = eth_dev_get_mac_addr_index(port_id, &null_mac_addr); 5173 if (index < 0) { 5174 RTE_ETHDEV_LOG_LINE(ERR, "Port %u: MAC address array full", 5175 port_id); 5176 return -ENOSPC; 5177 } 5178 } else { 5179 pool_mask = dev->data->mac_pool_sel[index]; 5180 5181 /* Check if both MAC address and pool is already there, and do nothing */ 5182 if (pool_mask & RTE_BIT64(pool)) 5183 return 0; 5184 } 5185 5186 /* Update NIC */ 5187 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool); 5188 5189 if (ret == 0) { 5190 /* Update address in NIC data structure */ 5191 rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]); 5192 5193 /* Update pool bitmap in NIC data structure */ 5194 dev->data->mac_pool_sel[index] |= RTE_BIT64(pool); 5195 } 5196 5197 ret = eth_err(port_id, ret); 5198 5199 rte_ethdev_trace_mac_addr_add(port_id, addr, pool, ret); 5200 5201 return ret; 5202 } 5203 5204 int 5205 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr) 5206 { 5207 struct rte_eth_dev *dev; 5208 int index; 5209 5210 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5211 dev = &rte_eth_devices[port_id]; 5212 5213 if (addr == NULL) { 5214 RTE_ETHDEV_LOG_LINE(ERR, 5215 "Cannot remove ethdev port %u MAC address from NULL address", 5216 port_id); 5217 return -EINVAL; 5218 } 5219 5220 if (*dev->dev_ops->mac_addr_remove == NULL) 5221 return -ENOTSUP; 5222 5223 index = eth_dev_get_mac_addr_index(port_id, addr); 5224 if (index == 0) { 5225 RTE_ETHDEV_LOG_LINE(ERR, 5226 "Port %u: Cannot remove default MAC address", 5227 port_id); 5228 return -EADDRINUSE; 5229 } else if (index < 0) 5230 return 0; /* Do nothing if address wasn't found */ 5231 5232 /* Update NIC */ 5233 (*dev->dev_ops->mac_addr_remove)(dev, index); 5234 5235 /* Update address in NIC data structure */ 5236 rte_ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]); 5237 5238 /* reset pool bitmap */ 5239 dev->data->mac_pool_sel[index] = 0; 5240 5241 rte_ethdev_trace_mac_addr_remove(port_id, addr); 5242 5243 return 0; 5244 } 5245 5246 int 5247 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr) 5248 { 5249 struct rte_eth_dev *dev; 5250 int index; 5251 int ret; 5252 5253 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5254 dev = &rte_eth_devices[port_id]; 5255 5256 if (addr == NULL) { 5257 RTE_ETHDEV_LOG_LINE(ERR, 5258 "Cannot set ethdev port %u default MAC address from NULL address", 5259 port_id); 5260 return -EINVAL; 5261 } 5262 5263 if (!rte_is_valid_assigned_ether_addr(addr)) 5264 return -EINVAL; 5265 5266 if (*dev->dev_ops->mac_addr_set == NULL) 5267 return -ENOTSUP; 5268 5269 /* Keep address unique in dev->data->mac_addrs[]. */ 5270 index = eth_dev_get_mac_addr_index(port_id, addr); 5271 if (index > 0) { 5272 RTE_ETHDEV_LOG_LINE(ERR, 5273 "New default address for port %u was already in the address list. Please remove it first.", 5274 port_id); 5275 return -EEXIST; 5276 } 5277 5278 ret = (*dev->dev_ops->mac_addr_set)(dev, addr); 5279 if (ret < 0) 5280 return ret; 5281 5282 /* Update default address in NIC data structure */ 5283 rte_ether_addr_copy(addr, &dev->data->mac_addrs[0]); 5284 5285 rte_ethdev_trace_default_mac_addr_set(port_id, addr); 5286 5287 return 0; 5288 } 5289 5290 5291 /* 5292 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 5293 * an empty spot. 5294 */ 5295 static int 5296 eth_dev_get_hash_mac_addr_index(uint16_t port_id, 5297 const struct rte_ether_addr *addr) 5298 { 5299 struct rte_eth_dev_info dev_info; 5300 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 5301 unsigned i; 5302 int ret; 5303 5304 ret = rte_eth_dev_info_get(port_id, &dev_info); 5305 if (ret != 0) 5306 return -1; 5307 5308 if (!dev->data->hash_mac_addrs) 5309 return -1; 5310 5311 for (i = 0; i < dev_info.max_hash_mac_addrs; i++) 5312 if (memcmp(addr, &dev->data->hash_mac_addrs[i], 5313 RTE_ETHER_ADDR_LEN) == 0) 5314 return i; 5315 5316 return -1; 5317 } 5318 5319 int 5320 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr, 5321 uint8_t on) 5322 { 5323 int index; 5324 int ret; 5325 struct rte_eth_dev *dev; 5326 5327 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5328 dev = &rte_eth_devices[port_id]; 5329 5330 if (addr == NULL) { 5331 RTE_ETHDEV_LOG_LINE(ERR, 5332 "Cannot set ethdev port %u unicast hash table from NULL address", 5333 port_id); 5334 return -EINVAL; 5335 } 5336 5337 if (rte_is_zero_ether_addr(addr)) { 5338 RTE_ETHDEV_LOG_LINE(ERR, "Port %u: Cannot add NULL MAC address", 5339 port_id); 5340 return -EINVAL; 5341 } 5342 5343 index = eth_dev_get_hash_mac_addr_index(port_id, addr); 5344 /* Check if it's already there, and do nothing */ 5345 if ((index >= 0) && on) 5346 return 0; 5347 5348 if (index < 0) { 5349 if (!on) { 5350 RTE_ETHDEV_LOG_LINE(ERR, 5351 "Port %u: the MAC address was not set in UTA", 5352 port_id); 5353 return -EINVAL; 5354 } 5355 5356 index = eth_dev_get_hash_mac_addr_index(port_id, &null_mac_addr); 5357 if (index < 0) { 5358 RTE_ETHDEV_LOG_LINE(ERR, "Port %u: MAC address array full", 5359 port_id); 5360 return -ENOSPC; 5361 } 5362 } 5363 5364 if (*dev->dev_ops->uc_hash_table_set == NULL) 5365 return -ENOTSUP; 5366 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on); 5367 if (ret == 0) { 5368 /* Update address in NIC data structure */ 5369 if (on) 5370 rte_ether_addr_copy(addr, 5371 &dev->data->hash_mac_addrs[index]); 5372 else 5373 rte_ether_addr_copy(&null_mac_addr, 5374 &dev->data->hash_mac_addrs[index]); 5375 } 5376 5377 ret = eth_err(port_id, ret); 5378 5379 rte_ethdev_trace_uc_hash_table_set(port_id, on, ret); 5380 5381 return ret; 5382 } 5383 5384 int 5385 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on) 5386 { 5387 struct rte_eth_dev *dev; 5388 int ret; 5389 5390 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5391 dev = &rte_eth_devices[port_id]; 5392 5393 if (*dev->dev_ops->uc_all_hash_table_set == NULL) 5394 return -ENOTSUP; 5395 ret = eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev, on)); 5396 5397 rte_ethdev_trace_uc_all_hash_table_set(port_id, on, ret); 5398 5399 return ret; 5400 } 5401 5402 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, 5403 uint32_t tx_rate) 5404 { 5405 struct rte_eth_dev *dev; 5406 struct rte_eth_dev_info dev_info; 5407 struct rte_eth_link link; 5408 int ret; 5409 5410 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5411 dev = &rte_eth_devices[port_id]; 5412 5413 ret = rte_eth_dev_info_get(port_id, &dev_info); 5414 if (ret != 0) 5415 return ret; 5416 5417 link = dev->data->dev_link; 5418 5419 if (queue_idx > dev_info.max_tx_queues) { 5420 RTE_ETHDEV_LOG_LINE(ERR, 5421 "Set queue rate limit:port %u: invalid queue ID=%u", 5422 port_id, queue_idx); 5423 return -EINVAL; 5424 } 5425 5426 if (tx_rate > link.link_speed) { 5427 RTE_ETHDEV_LOG_LINE(ERR, 5428 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d", 5429 tx_rate, link.link_speed); 5430 return -EINVAL; 5431 } 5432 5433 if (*dev->dev_ops->set_queue_rate_limit == NULL) 5434 return -ENOTSUP; 5435 ret = eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev, 5436 queue_idx, tx_rate)); 5437 5438 rte_eth_trace_set_queue_rate_limit(port_id, queue_idx, tx_rate, ret); 5439 5440 return ret; 5441 } 5442 5443 int rte_eth_rx_avail_thresh_set(uint16_t port_id, uint16_t queue_id, 5444 uint8_t avail_thresh) 5445 { 5446 struct rte_eth_dev *dev; 5447 int ret; 5448 5449 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5450 dev = &rte_eth_devices[port_id]; 5451 5452 if (queue_id > dev->data->nb_rx_queues) { 5453 RTE_ETHDEV_LOG_LINE(ERR, 5454 "Set queue avail thresh: port %u: invalid queue ID=%u.", 5455 port_id, queue_id); 5456 return -EINVAL; 5457 } 5458 5459 if (avail_thresh > 99) { 5460 RTE_ETHDEV_LOG_LINE(ERR, 5461 "Set queue avail thresh: port %u: threshold should be <= 99.", 5462 port_id); 5463 return -EINVAL; 5464 } 5465 if (*dev->dev_ops->rx_queue_avail_thresh_set == NULL) 5466 return -ENOTSUP; 5467 ret = eth_err(port_id, (*dev->dev_ops->rx_queue_avail_thresh_set)(dev, 5468 queue_id, avail_thresh)); 5469 5470 rte_eth_trace_rx_avail_thresh_set(port_id, queue_id, avail_thresh, ret); 5471 5472 return ret; 5473 } 5474 5475 int rte_eth_rx_avail_thresh_query(uint16_t port_id, uint16_t *queue_id, 5476 uint8_t *avail_thresh) 5477 { 5478 struct rte_eth_dev *dev; 5479 int ret; 5480 5481 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5482 dev = &rte_eth_devices[port_id]; 5483 5484 if (queue_id == NULL) 5485 return -EINVAL; 5486 if (*queue_id >= dev->data->nb_rx_queues) 5487 *queue_id = 0; 5488 5489 if (*dev->dev_ops->rx_queue_avail_thresh_query == NULL) 5490 return -ENOTSUP; 5491 ret = eth_err(port_id, (*dev->dev_ops->rx_queue_avail_thresh_query)(dev, 5492 queue_id, avail_thresh)); 5493 5494 rte_eth_trace_rx_avail_thresh_query(port_id, *queue_id, ret); 5495 5496 return ret; 5497 } 5498 5499 RTE_INIT(eth_dev_init_fp_ops) 5500 { 5501 uint32_t i; 5502 5503 for (i = 0; i != RTE_DIM(rte_eth_fp_ops); i++) 5504 eth_dev_fp_ops_reset(rte_eth_fp_ops + i); 5505 } 5506 5507 RTE_INIT(eth_dev_init_cb_lists) 5508 { 5509 uint16_t i; 5510 5511 for (i = 0; i < RTE_MAX_ETHPORTS; i++) 5512 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs); 5513 } 5514 5515 int 5516 rte_eth_dev_callback_register(uint16_t port_id, 5517 enum rte_eth_event_type event, 5518 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 5519 { 5520 struct rte_eth_dev *dev; 5521 struct rte_eth_dev_callback *user_cb; 5522 uint16_t next_port; 5523 uint16_t last_port; 5524 5525 if (cb_fn == NULL) { 5526 RTE_ETHDEV_LOG_LINE(ERR, 5527 "Cannot register ethdev port %u callback from NULL", 5528 port_id); 5529 return -EINVAL; 5530 } 5531 5532 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 5533 RTE_ETHDEV_LOG_LINE(ERR, "Invalid port_id=%d", port_id); 5534 return -EINVAL; 5535 } 5536 5537 if (port_id == RTE_ETH_ALL) { 5538 next_port = 0; 5539 last_port = RTE_MAX_ETHPORTS - 1; 5540 } else { 5541 next_port = last_port = port_id; 5542 } 5543 5544 rte_spinlock_lock(ð_dev_cb_lock); 5545 5546 do { 5547 dev = &rte_eth_devices[next_port]; 5548 5549 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) { 5550 if (user_cb->cb_fn == cb_fn && 5551 user_cb->cb_arg == cb_arg && 5552 user_cb->event == event) { 5553 break; 5554 } 5555 } 5556 5557 /* create a new callback. */ 5558 if (user_cb == NULL) { 5559 user_cb = rte_zmalloc("INTR_USER_CALLBACK", 5560 sizeof(struct rte_eth_dev_callback), 0); 5561 if (user_cb != NULL) { 5562 user_cb->cb_fn = cb_fn; 5563 user_cb->cb_arg = cb_arg; 5564 user_cb->event = event; 5565 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs), 5566 user_cb, next); 5567 } else { 5568 rte_spinlock_unlock(ð_dev_cb_lock); 5569 rte_eth_dev_callback_unregister(port_id, event, 5570 cb_fn, cb_arg); 5571 return -ENOMEM; 5572 } 5573 5574 } 5575 } while (++next_port <= last_port); 5576 5577 rte_spinlock_unlock(ð_dev_cb_lock); 5578 5579 rte_ethdev_trace_callback_register(port_id, event, cb_fn, cb_arg); 5580 5581 return 0; 5582 } 5583 5584 int 5585 rte_eth_dev_callback_unregister(uint16_t port_id, 5586 enum rte_eth_event_type event, 5587 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 5588 { 5589 int ret; 5590 struct rte_eth_dev *dev; 5591 struct rte_eth_dev_callback *cb, *next; 5592 uint16_t next_port; 5593 uint16_t last_port; 5594 5595 if (cb_fn == NULL) { 5596 RTE_ETHDEV_LOG_LINE(ERR, 5597 "Cannot unregister ethdev port %u callback from NULL", 5598 port_id); 5599 return -EINVAL; 5600 } 5601 5602 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 5603 RTE_ETHDEV_LOG_LINE(ERR, "Invalid port_id=%d", port_id); 5604 return -EINVAL; 5605 } 5606 5607 if (port_id == RTE_ETH_ALL) { 5608 next_port = 0; 5609 last_port = RTE_MAX_ETHPORTS - 1; 5610 } else { 5611 next_port = last_port = port_id; 5612 } 5613 5614 rte_spinlock_lock(ð_dev_cb_lock); 5615 5616 do { 5617 dev = &rte_eth_devices[next_port]; 5618 ret = 0; 5619 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL; 5620 cb = next) { 5621 5622 next = TAILQ_NEXT(cb, next); 5623 5624 if (cb->cb_fn != cb_fn || cb->event != event || 5625 (cb_arg != (void *)-1 && cb->cb_arg != cb_arg)) 5626 continue; 5627 5628 /* 5629 * if this callback is not executing right now, 5630 * then remove it. 5631 */ 5632 if (cb->active == 0) { 5633 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next); 5634 rte_free(cb); 5635 } else { 5636 ret = -EAGAIN; 5637 } 5638 } 5639 } while (++next_port <= last_port); 5640 5641 rte_spinlock_unlock(ð_dev_cb_lock); 5642 5643 rte_ethdev_trace_callback_unregister(port_id, event, cb_fn, cb_arg, 5644 ret); 5645 5646 return ret; 5647 } 5648 5649 int 5650 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data) 5651 { 5652 uint32_t vec; 5653 struct rte_eth_dev *dev; 5654 struct rte_intr_handle *intr_handle; 5655 uint16_t qid; 5656 int rc; 5657 5658 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5659 dev = &rte_eth_devices[port_id]; 5660 5661 if (!dev->intr_handle) { 5662 RTE_ETHDEV_LOG_LINE(ERR, "Rx Intr handle unset"); 5663 return -ENOTSUP; 5664 } 5665 5666 intr_handle = dev->intr_handle; 5667 if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) { 5668 RTE_ETHDEV_LOG_LINE(ERR, "Rx Intr vector unset"); 5669 return -EPERM; 5670 } 5671 5672 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { 5673 vec = rte_intr_vec_list_index_get(intr_handle, qid); 5674 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 5675 5676 rte_ethdev_trace_rx_intr_ctl(port_id, qid, epfd, op, data, rc); 5677 5678 if (rc && rc != -EEXIST) { 5679 RTE_ETHDEV_LOG_LINE(ERR, 5680 "p %u q %u Rx ctl error op %d epfd %d vec %u", 5681 port_id, qid, op, epfd, vec); 5682 } 5683 } 5684 5685 return 0; 5686 } 5687 5688 int 5689 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id) 5690 { 5691 struct rte_intr_handle *intr_handle; 5692 struct rte_eth_dev *dev; 5693 unsigned int efd_idx; 5694 uint32_t vec; 5695 int fd; 5696 5697 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 5698 dev = &rte_eth_devices[port_id]; 5699 5700 if (queue_id >= dev->data->nb_rx_queues) { 5701 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", queue_id); 5702 return -1; 5703 } 5704 5705 if (!dev->intr_handle) { 5706 RTE_ETHDEV_LOG_LINE(ERR, "Rx Intr handle unset"); 5707 return -1; 5708 } 5709 5710 intr_handle = dev->intr_handle; 5711 if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) { 5712 RTE_ETHDEV_LOG_LINE(ERR, "Rx Intr vector unset"); 5713 return -1; 5714 } 5715 5716 vec = rte_intr_vec_list_index_get(intr_handle, queue_id); 5717 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ? 5718 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec; 5719 fd = rte_intr_efds_index_get(intr_handle, efd_idx); 5720 5721 rte_ethdev_trace_rx_intr_ctl_q_get_fd(port_id, queue_id, fd); 5722 5723 return fd; 5724 } 5725 5726 int 5727 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id, 5728 int epfd, int op, void *data) 5729 { 5730 uint32_t vec; 5731 struct rte_eth_dev *dev; 5732 struct rte_intr_handle *intr_handle; 5733 int rc; 5734 5735 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5736 dev = &rte_eth_devices[port_id]; 5737 5738 if (queue_id >= dev->data->nb_rx_queues) { 5739 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", queue_id); 5740 return -EINVAL; 5741 } 5742 5743 if (!dev->intr_handle) { 5744 RTE_ETHDEV_LOG_LINE(ERR, "Rx Intr handle unset"); 5745 return -ENOTSUP; 5746 } 5747 5748 intr_handle = dev->intr_handle; 5749 if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) { 5750 RTE_ETHDEV_LOG_LINE(ERR, "Rx Intr vector unset"); 5751 return -EPERM; 5752 } 5753 5754 vec = rte_intr_vec_list_index_get(intr_handle, queue_id); 5755 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 5756 5757 rte_ethdev_trace_rx_intr_ctl_q(port_id, queue_id, epfd, op, data, rc); 5758 5759 if (rc && rc != -EEXIST) { 5760 RTE_ETHDEV_LOG_LINE(ERR, 5761 "p %u q %u Rx ctl error op %d epfd %d vec %u", 5762 port_id, queue_id, op, epfd, vec); 5763 return rc; 5764 } 5765 5766 return 0; 5767 } 5768 5769 int 5770 rte_eth_dev_rx_intr_enable(uint16_t port_id, 5771 uint16_t queue_id) 5772 { 5773 struct rte_eth_dev *dev; 5774 int ret; 5775 5776 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5777 dev = &rte_eth_devices[port_id]; 5778 5779 ret = eth_dev_validate_rx_queue(dev, queue_id); 5780 if (ret != 0) 5781 return ret; 5782 5783 if (*dev->dev_ops->rx_queue_intr_enable == NULL) 5784 return -ENOTSUP; 5785 ret = eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev, queue_id)); 5786 5787 rte_ethdev_trace_rx_intr_enable(port_id, queue_id, ret); 5788 5789 return ret; 5790 } 5791 5792 int 5793 rte_eth_dev_rx_intr_disable(uint16_t port_id, 5794 uint16_t queue_id) 5795 { 5796 struct rte_eth_dev *dev; 5797 int ret; 5798 5799 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5800 dev = &rte_eth_devices[port_id]; 5801 5802 ret = eth_dev_validate_rx_queue(dev, queue_id); 5803 if (ret != 0) 5804 return ret; 5805 5806 if (*dev->dev_ops->rx_queue_intr_disable == NULL) 5807 return -ENOTSUP; 5808 ret = eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev, queue_id)); 5809 5810 rte_ethdev_trace_rx_intr_disable(port_id, queue_id, ret); 5811 5812 return ret; 5813 } 5814 5815 5816 const struct rte_eth_rxtx_callback * 5817 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id, 5818 rte_rx_callback_fn fn, void *user_param) 5819 { 5820 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5821 rte_errno = ENOTSUP; 5822 return NULL; 5823 #endif 5824 struct rte_eth_dev *dev; 5825 5826 /* check input parameters */ 5827 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 5828 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 5829 rte_errno = EINVAL; 5830 return NULL; 5831 } 5832 dev = &rte_eth_devices[port_id]; 5833 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) { 5834 rte_errno = EINVAL; 5835 return NULL; 5836 } 5837 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 5838 5839 if (cb == NULL) { 5840 rte_errno = ENOMEM; 5841 return NULL; 5842 } 5843 5844 cb->fn.rx = fn; 5845 cb->param = user_param; 5846 5847 rte_spinlock_lock(ð_dev_rx_cb_lock); 5848 /* Add the callbacks in fifo order. */ 5849 struct rte_eth_rxtx_callback *tail = 5850 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 5851 5852 if (!tail) { 5853 /* Stores to cb->fn and cb->param should complete before 5854 * cb is visible to data plane. 5855 */ 5856 rte_atomic_store_explicit( 5857 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id], 5858 cb, rte_memory_order_release); 5859 5860 } else { 5861 while (tail->next) 5862 tail = tail->next; 5863 /* Stores to cb->fn and cb->param should complete before 5864 * cb is visible to data plane. 5865 */ 5866 rte_atomic_store_explicit(&tail->next, cb, rte_memory_order_release); 5867 } 5868 rte_spinlock_unlock(ð_dev_rx_cb_lock); 5869 5870 rte_eth_trace_add_rx_callback(port_id, queue_id, fn, user_param, cb); 5871 5872 return cb; 5873 } 5874 5875 const struct rte_eth_rxtx_callback * 5876 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id, 5877 rte_rx_callback_fn fn, void *user_param) 5878 { 5879 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5880 rte_errno = ENOTSUP; 5881 return NULL; 5882 #endif 5883 /* check input parameters */ 5884 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 5885 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 5886 rte_errno = EINVAL; 5887 return NULL; 5888 } 5889 5890 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 5891 5892 if (cb == NULL) { 5893 rte_errno = ENOMEM; 5894 return NULL; 5895 } 5896 5897 cb->fn.rx = fn; 5898 cb->param = user_param; 5899 5900 rte_spinlock_lock(ð_dev_rx_cb_lock); 5901 /* Add the callbacks at first position */ 5902 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 5903 /* Stores to cb->fn, cb->param and cb->next should complete before 5904 * cb is visible to data plane threads. 5905 */ 5906 rte_atomic_store_explicit( 5907 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id], 5908 cb, rte_memory_order_release); 5909 rte_spinlock_unlock(ð_dev_rx_cb_lock); 5910 5911 rte_eth_trace_add_first_rx_callback(port_id, queue_id, fn, user_param, 5912 cb); 5913 5914 return cb; 5915 } 5916 5917 const struct rte_eth_rxtx_callback * 5918 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id, 5919 rte_tx_callback_fn fn, void *user_param) 5920 { 5921 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5922 rte_errno = ENOTSUP; 5923 return NULL; 5924 #endif 5925 struct rte_eth_dev *dev; 5926 5927 /* check input parameters */ 5928 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 5929 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) { 5930 rte_errno = EINVAL; 5931 return NULL; 5932 } 5933 5934 dev = &rte_eth_devices[port_id]; 5935 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) { 5936 rte_errno = EINVAL; 5937 return NULL; 5938 } 5939 5940 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 5941 5942 if (cb == NULL) { 5943 rte_errno = ENOMEM; 5944 return NULL; 5945 } 5946 5947 cb->fn.tx = fn; 5948 cb->param = user_param; 5949 5950 rte_spinlock_lock(ð_dev_tx_cb_lock); 5951 /* Add the callbacks in fifo order. */ 5952 struct rte_eth_rxtx_callback *tail = 5953 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id]; 5954 5955 if (!tail) { 5956 /* Stores to cb->fn and cb->param should complete before 5957 * cb is visible to data plane. 5958 */ 5959 rte_atomic_store_explicit( 5960 &rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id], 5961 cb, rte_memory_order_release); 5962 5963 } else { 5964 while (tail->next) 5965 tail = tail->next; 5966 /* Stores to cb->fn and cb->param should complete before 5967 * cb is visible to data plane. 5968 */ 5969 rte_atomic_store_explicit(&tail->next, cb, rte_memory_order_release); 5970 } 5971 rte_spinlock_unlock(ð_dev_tx_cb_lock); 5972 5973 rte_eth_trace_add_tx_callback(port_id, queue_id, fn, user_param, cb); 5974 5975 return cb; 5976 } 5977 5978 int 5979 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id, 5980 const struct rte_eth_rxtx_callback *user_cb) 5981 { 5982 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5983 return -ENOTSUP; 5984 #endif 5985 /* Check input parameters. */ 5986 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5987 if (user_cb == NULL || 5988 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) 5989 return -EINVAL; 5990 5991 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 5992 struct rte_eth_rxtx_callback *cb; 5993 RTE_ATOMIC(struct rte_eth_rxtx_callback *) *prev_cb; 5994 int ret = -EINVAL; 5995 5996 rte_spinlock_lock(ð_dev_rx_cb_lock); 5997 prev_cb = &dev->post_rx_burst_cbs[queue_id]; 5998 for (; *prev_cb != NULL; prev_cb = &cb->next) { 5999 cb = *prev_cb; 6000 if (cb == user_cb) { 6001 /* Remove the user cb from the callback list. */ 6002 rte_atomic_store_explicit(prev_cb, cb->next, rte_memory_order_relaxed); 6003 ret = 0; 6004 break; 6005 } 6006 } 6007 rte_spinlock_unlock(ð_dev_rx_cb_lock); 6008 6009 rte_eth_trace_remove_rx_callback(port_id, queue_id, user_cb, ret); 6010 6011 return ret; 6012 } 6013 6014 int 6015 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id, 6016 const struct rte_eth_rxtx_callback *user_cb) 6017 { 6018 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 6019 return -ENOTSUP; 6020 #endif 6021 /* Check input parameters. */ 6022 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6023 if (user_cb == NULL || 6024 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) 6025 return -EINVAL; 6026 6027 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 6028 int ret = -EINVAL; 6029 struct rte_eth_rxtx_callback *cb; 6030 RTE_ATOMIC(struct rte_eth_rxtx_callback *) *prev_cb; 6031 6032 rte_spinlock_lock(ð_dev_tx_cb_lock); 6033 prev_cb = &dev->pre_tx_burst_cbs[queue_id]; 6034 for (; *prev_cb != NULL; prev_cb = &cb->next) { 6035 cb = *prev_cb; 6036 if (cb == user_cb) { 6037 /* Remove the user cb from the callback list. */ 6038 rte_atomic_store_explicit(prev_cb, cb->next, rte_memory_order_relaxed); 6039 ret = 0; 6040 break; 6041 } 6042 } 6043 rte_spinlock_unlock(ð_dev_tx_cb_lock); 6044 6045 rte_eth_trace_remove_tx_callback(port_id, queue_id, user_cb, ret); 6046 6047 return ret; 6048 } 6049 6050 int 6051 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id, 6052 struct rte_eth_rxq_info *qinfo) 6053 { 6054 struct rte_eth_dev *dev; 6055 6056 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6057 dev = &rte_eth_devices[port_id]; 6058 6059 if (queue_id >= dev->data->nb_rx_queues) { 6060 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", queue_id); 6061 return -EINVAL; 6062 } 6063 6064 if (qinfo == NULL) { 6065 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u Rx queue %u info to NULL", 6066 port_id, queue_id); 6067 return -EINVAL; 6068 } 6069 6070 if (dev->data->rx_queues == NULL || 6071 dev->data->rx_queues[queue_id] == NULL) { 6072 RTE_ETHDEV_LOG_LINE(ERR, 6073 "Rx queue %"PRIu16" of device with port_id=%" 6074 PRIu16" has not been setup", 6075 queue_id, port_id); 6076 return -EINVAL; 6077 } 6078 6079 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) { 6080 RTE_ETHDEV_LOG_LINE(INFO, 6081 "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16, 6082 queue_id, port_id); 6083 return -EINVAL; 6084 } 6085 6086 if (*dev->dev_ops->rxq_info_get == NULL) 6087 return -ENOTSUP; 6088 6089 memset(qinfo, 0, sizeof(*qinfo)); 6090 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo); 6091 qinfo->queue_state = dev->data->rx_queue_state[queue_id]; 6092 6093 rte_eth_trace_rx_queue_info_get(port_id, queue_id, qinfo); 6094 6095 return 0; 6096 } 6097 6098 int 6099 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id, 6100 struct rte_eth_txq_info *qinfo) 6101 { 6102 struct rte_eth_dev *dev; 6103 6104 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6105 dev = &rte_eth_devices[port_id]; 6106 6107 if (queue_id >= dev->data->nb_tx_queues) { 6108 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Tx queue_id=%u", queue_id); 6109 return -EINVAL; 6110 } 6111 6112 if (qinfo == NULL) { 6113 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get ethdev port %u Tx queue %u info to NULL", 6114 port_id, queue_id); 6115 return -EINVAL; 6116 } 6117 6118 if (dev->data->tx_queues == NULL || 6119 dev->data->tx_queues[queue_id] == NULL) { 6120 RTE_ETHDEV_LOG_LINE(ERR, 6121 "Tx queue %"PRIu16" of device with port_id=%" 6122 PRIu16" has not been setup", 6123 queue_id, port_id); 6124 return -EINVAL; 6125 } 6126 6127 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) { 6128 RTE_ETHDEV_LOG_LINE(INFO, 6129 "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16, 6130 queue_id, port_id); 6131 return -EINVAL; 6132 } 6133 6134 if (*dev->dev_ops->txq_info_get == NULL) 6135 return -ENOTSUP; 6136 6137 memset(qinfo, 0, sizeof(*qinfo)); 6138 dev->dev_ops->txq_info_get(dev, queue_id, qinfo); 6139 qinfo->queue_state = dev->data->tx_queue_state[queue_id]; 6140 6141 rte_eth_trace_tx_queue_info_get(port_id, queue_id, qinfo); 6142 6143 return 0; 6144 } 6145 6146 int 6147 rte_eth_recycle_rx_queue_info_get(uint16_t port_id, uint16_t queue_id, 6148 struct rte_eth_recycle_rxq_info *recycle_rxq_info) 6149 { 6150 struct rte_eth_dev *dev; 6151 int ret; 6152 6153 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6154 dev = &rte_eth_devices[port_id]; 6155 6156 ret = eth_dev_validate_rx_queue(dev, queue_id); 6157 if (unlikely(ret != 0)) 6158 return ret; 6159 6160 if (*dev->dev_ops->recycle_rxq_info_get == NULL) 6161 return -ENOTSUP; 6162 6163 dev->dev_ops->recycle_rxq_info_get(dev, queue_id, recycle_rxq_info); 6164 6165 return 0; 6166 } 6167 6168 int 6169 rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id, 6170 struct rte_eth_burst_mode *mode) 6171 { 6172 struct rte_eth_dev *dev; 6173 int ret; 6174 6175 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6176 dev = &rte_eth_devices[port_id]; 6177 6178 if (queue_id >= dev->data->nb_rx_queues) { 6179 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", queue_id); 6180 return -EINVAL; 6181 } 6182 6183 if (mode == NULL) { 6184 RTE_ETHDEV_LOG_LINE(ERR, 6185 "Cannot get ethdev port %u Rx queue %u burst mode to NULL", 6186 port_id, queue_id); 6187 return -EINVAL; 6188 } 6189 6190 if (*dev->dev_ops->rx_burst_mode_get == NULL) 6191 return -ENOTSUP; 6192 memset(mode, 0, sizeof(*mode)); 6193 ret = eth_err(port_id, 6194 dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode)); 6195 6196 rte_eth_trace_rx_burst_mode_get(port_id, queue_id, mode, ret); 6197 6198 return ret; 6199 } 6200 6201 int 6202 rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id, 6203 struct rte_eth_burst_mode *mode) 6204 { 6205 struct rte_eth_dev *dev; 6206 int ret; 6207 6208 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6209 dev = &rte_eth_devices[port_id]; 6210 6211 if (queue_id >= dev->data->nb_tx_queues) { 6212 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Tx queue_id=%u", queue_id); 6213 return -EINVAL; 6214 } 6215 6216 if (mode == NULL) { 6217 RTE_ETHDEV_LOG_LINE(ERR, 6218 "Cannot get ethdev port %u Tx queue %u burst mode to NULL", 6219 port_id, queue_id); 6220 return -EINVAL; 6221 } 6222 6223 if (*dev->dev_ops->tx_burst_mode_get == NULL) 6224 return -ENOTSUP; 6225 memset(mode, 0, sizeof(*mode)); 6226 ret = eth_err(port_id, 6227 dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode)); 6228 6229 rte_eth_trace_tx_burst_mode_get(port_id, queue_id, mode, ret); 6230 6231 return ret; 6232 } 6233 6234 int 6235 rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id, 6236 struct rte_power_monitor_cond *pmc) 6237 { 6238 struct rte_eth_dev *dev; 6239 int ret; 6240 6241 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6242 dev = &rte_eth_devices[port_id]; 6243 6244 if (queue_id >= dev->data->nb_rx_queues) { 6245 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", queue_id); 6246 return -EINVAL; 6247 } 6248 6249 if (pmc == NULL) { 6250 RTE_ETHDEV_LOG_LINE(ERR, 6251 "Cannot get ethdev port %u Rx queue %u power monitor condition to NULL", 6252 port_id, queue_id); 6253 return -EINVAL; 6254 } 6255 6256 if (*dev->dev_ops->get_monitor_addr == NULL) 6257 return -ENOTSUP; 6258 ret = eth_err(port_id, 6259 dev->dev_ops->get_monitor_addr(dev->data->rx_queues[queue_id], pmc)); 6260 6261 rte_eth_trace_get_monitor_addr(port_id, queue_id, pmc, ret); 6262 6263 return ret; 6264 } 6265 6266 int 6267 rte_eth_dev_set_mc_addr_list(uint16_t port_id, 6268 struct rte_ether_addr *mc_addr_set, 6269 uint32_t nb_mc_addr) 6270 { 6271 struct rte_eth_dev *dev; 6272 int ret; 6273 6274 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6275 dev = &rte_eth_devices[port_id]; 6276 6277 if (*dev->dev_ops->set_mc_addr_list == NULL) 6278 return -ENOTSUP; 6279 ret = eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev, 6280 mc_addr_set, nb_mc_addr)); 6281 6282 rte_ethdev_trace_set_mc_addr_list(port_id, mc_addr_set, nb_mc_addr, 6283 ret); 6284 6285 return ret; 6286 } 6287 6288 int 6289 rte_eth_timesync_enable(uint16_t port_id) 6290 { 6291 struct rte_eth_dev *dev; 6292 int ret; 6293 6294 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6295 dev = &rte_eth_devices[port_id]; 6296 6297 if (*dev->dev_ops->timesync_enable == NULL) 6298 return -ENOTSUP; 6299 ret = eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev)); 6300 6301 rte_eth_trace_timesync_enable(port_id, ret); 6302 6303 return ret; 6304 } 6305 6306 int 6307 rte_eth_timesync_disable(uint16_t port_id) 6308 { 6309 struct rte_eth_dev *dev; 6310 int ret; 6311 6312 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6313 dev = &rte_eth_devices[port_id]; 6314 6315 if (*dev->dev_ops->timesync_disable == NULL) 6316 return -ENOTSUP; 6317 ret = eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev)); 6318 6319 rte_eth_trace_timesync_disable(port_id, ret); 6320 6321 return ret; 6322 } 6323 6324 int 6325 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp, 6326 uint32_t flags) 6327 { 6328 struct rte_eth_dev *dev; 6329 int ret; 6330 6331 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6332 dev = &rte_eth_devices[port_id]; 6333 6334 if (timestamp == NULL) { 6335 RTE_ETHDEV_LOG_LINE(ERR, 6336 "Cannot read ethdev port %u Rx timestamp to NULL", 6337 port_id); 6338 return -EINVAL; 6339 } 6340 6341 if (*dev->dev_ops->timesync_read_rx_timestamp == NULL) 6342 return -ENOTSUP; 6343 6344 ret = eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp) 6345 (dev, timestamp, flags)); 6346 6347 rte_eth_trace_timesync_read_rx_timestamp(port_id, timestamp, flags, 6348 ret); 6349 6350 return ret; 6351 } 6352 6353 int 6354 rte_eth_timesync_read_tx_timestamp(uint16_t port_id, 6355 struct timespec *timestamp) 6356 { 6357 struct rte_eth_dev *dev; 6358 int ret; 6359 6360 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6361 dev = &rte_eth_devices[port_id]; 6362 6363 if (timestamp == NULL) { 6364 RTE_ETHDEV_LOG_LINE(ERR, 6365 "Cannot read ethdev port %u Tx timestamp to NULL", 6366 port_id); 6367 return -EINVAL; 6368 } 6369 6370 if (*dev->dev_ops->timesync_read_tx_timestamp == NULL) 6371 return -ENOTSUP; 6372 6373 ret = eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp) 6374 (dev, timestamp)); 6375 6376 rte_eth_trace_timesync_read_tx_timestamp(port_id, timestamp, ret); 6377 6378 return ret; 6379 6380 } 6381 6382 int 6383 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta) 6384 { 6385 struct rte_eth_dev *dev; 6386 int ret; 6387 6388 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6389 dev = &rte_eth_devices[port_id]; 6390 6391 if (*dev->dev_ops->timesync_adjust_time == NULL) 6392 return -ENOTSUP; 6393 ret = eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev, delta)); 6394 6395 rte_eth_trace_timesync_adjust_time(port_id, delta, ret); 6396 6397 return ret; 6398 } 6399 6400 int 6401 rte_eth_timesync_adjust_freq(uint16_t port_id, int64_t ppm) 6402 { 6403 struct rte_eth_dev *dev; 6404 int ret; 6405 6406 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6407 dev = &rte_eth_devices[port_id]; 6408 6409 if (*dev->dev_ops->timesync_adjust_freq == NULL) 6410 return -ENOTSUP; 6411 ret = eth_err(port_id, (*dev->dev_ops->timesync_adjust_freq)(dev, ppm)); 6412 6413 rte_eth_trace_timesync_adjust_freq(port_id, ppm, ret); 6414 6415 return ret; 6416 } 6417 6418 int 6419 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp) 6420 { 6421 struct rte_eth_dev *dev; 6422 int ret; 6423 6424 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6425 dev = &rte_eth_devices[port_id]; 6426 6427 if (timestamp == NULL) { 6428 RTE_ETHDEV_LOG_LINE(ERR, 6429 "Cannot read ethdev port %u timesync time to NULL", 6430 port_id); 6431 return -EINVAL; 6432 } 6433 6434 if (*dev->dev_ops->timesync_read_time == NULL) 6435 return -ENOTSUP; 6436 ret = eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev, 6437 timestamp)); 6438 6439 rte_eth_trace_timesync_read_time(port_id, timestamp, ret); 6440 6441 return ret; 6442 } 6443 6444 int 6445 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp) 6446 { 6447 struct rte_eth_dev *dev; 6448 int ret; 6449 6450 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6451 dev = &rte_eth_devices[port_id]; 6452 6453 if (timestamp == NULL) { 6454 RTE_ETHDEV_LOG_LINE(ERR, 6455 "Cannot write ethdev port %u timesync from NULL time", 6456 port_id); 6457 return -EINVAL; 6458 } 6459 6460 if (*dev->dev_ops->timesync_write_time == NULL) 6461 return -ENOTSUP; 6462 ret = eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev, 6463 timestamp)); 6464 6465 rte_eth_trace_timesync_write_time(port_id, timestamp, ret); 6466 6467 return ret; 6468 } 6469 6470 int 6471 rte_eth_read_clock(uint16_t port_id, uint64_t *clock) 6472 { 6473 struct rte_eth_dev *dev; 6474 int ret; 6475 6476 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6477 dev = &rte_eth_devices[port_id]; 6478 6479 if (clock == NULL) { 6480 RTE_ETHDEV_LOG_LINE(ERR, "Cannot read ethdev port %u clock to NULL", 6481 port_id); 6482 return -EINVAL; 6483 } 6484 6485 if (*dev->dev_ops->read_clock == NULL) 6486 return -ENOTSUP; 6487 ret = eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock)); 6488 6489 rte_eth_trace_read_clock(port_id, clock, ret); 6490 6491 return ret; 6492 } 6493 6494 int 6495 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) 6496 { 6497 struct rte_dev_reg_info reg_info = { 0 }; 6498 int ret; 6499 6500 if (info == NULL) { 6501 RTE_ETHDEV_LOG_LINE(ERR, 6502 "Cannot get ethdev port %u register info to NULL", 6503 port_id); 6504 return -EINVAL; 6505 } 6506 6507 reg_info.length = info->length; 6508 reg_info.data = info->data; 6509 6510 ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); 6511 if (ret != 0) 6512 return ret; 6513 6514 info->length = reg_info.length; 6515 info->width = reg_info.width; 6516 info->version = reg_info.version; 6517 info->offset = reg_info.offset; 6518 6519 return 0; 6520 } 6521 6522 int 6523 rte_eth_dev_get_reg_info_ext(uint16_t port_id, struct rte_dev_reg_info *info) 6524 { 6525 struct rte_eth_dev *dev; 6526 uint32_t i; 6527 int ret; 6528 6529 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6530 dev = &rte_eth_devices[port_id]; 6531 6532 if (info == NULL) { 6533 RTE_ETHDEV_LOG_LINE(ERR, 6534 "Cannot get ethdev port %u register info to NULL", 6535 port_id); 6536 return -EINVAL; 6537 } 6538 6539 if (info->names != NULL && info->length != 0) 6540 memset(info->names, 0, sizeof(struct rte_eth_reg_name) * info->length); 6541 6542 if (*dev->dev_ops->get_reg == NULL) 6543 return -ENOTSUP; 6544 ret = eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info)); 6545 6546 rte_ethdev_trace_get_reg_info(port_id, info, ret); 6547 6548 /* Report the default names if drivers not report. */ 6549 if (ret == 0 && info->names != NULL && strlen(info->names[0].name) == 0) { 6550 for (i = 0; i < info->length; i++) 6551 snprintf(info->names[i].name, RTE_ETH_REG_NAME_SIZE, 6552 "index_%u", info->offset + i); 6553 } 6554 return ret; 6555 } 6556 6557 int 6558 rte_eth_dev_get_eeprom_length(uint16_t port_id) 6559 { 6560 struct rte_eth_dev *dev; 6561 int ret; 6562 6563 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6564 dev = &rte_eth_devices[port_id]; 6565 6566 if (*dev->dev_ops->get_eeprom_length == NULL) 6567 return -ENOTSUP; 6568 ret = eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev)); 6569 6570 rte_ethdev_trace_get_eeprom_length(port_id, ret); 6571 6572 return ret; 6573 } 6574 6575 int 6576 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 6577 { 6578 struct rte_eth_dev *dev; 6579 int ret; 6580 6581 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6582 dev = &rte_eth_devices[port_id]; 6583 6584 if (info == NULL) { 6585 RTE_ETHDEV_LOG_LINE(ERR, 6586 "Cannot get ethdev port %u EEPROM info to NULL", 6587 port_id); 6588 return -EINVAL; 6589 } 6590 6591 if (*dev->dev_ops->get_eeprom == NULL) 6592 return -ENOTSUP; 6593 ret = eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info)); 6594 6595 rte_ethdev_trace_get_eeprom(port_id, info, ret); 6596 6597 return ret; 6598 } 6599 6600 int 6601 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 6602 { 6603 struct rte_eth_dev *dev; 6604 int ret; 6605 6606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6607 dev = &rte_eth_devices[port_id]; 6608 6609 if (info == NULL) { 6610 RTE_ETHDEV_LOG_LINE(ERR, 6611 "Cannot set ethdev port %u EEPROM from NULL info", 6612 port_id); 6613 return -EINVAL; 6614 } 6615 6616 if (*dev->dev_ops->set_eeprom == NULL) 6617 return -ENOTSUP; 6618 ret = eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info)); 6619 6620 rte_ethdev_trace_set_eeprom(port_id, info, ret); 6621 6622 return ret; 6623 } 6624 6625 int 6626 rte_eth_dev_get_module_info(uint16_t port_id, 6627 struct rte_eth_dev_module_info *modinfo) 6628 { 6629 struct rte_eth_dev *dev; 6630 int ret; 6631 6632 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6633 dev = &rte_eth_devices[port_id]; 6634 6635 if (modinfo == NULL) { 6636 RTE_ETHDEV_LOG_LINE(ERR, 6637 "Cannot get ethdev port %u EEPROM module info to NULL", 6638 port_id); 6639 return -EINVAL; 6640 } 6641 6642 if (*dev->dev_ops->get_module_info == NULL) 6643 return -ENOTSUP; 6644 ret = (*dev->dev_ops->get_module_info)(dev, modinfo); 6645 6646 rte_ethdev_trace_get_module_info(port_id, modinfo, ret); 6647 6648 return ret; 6649 } 6650 6651 int 6652 rte_eth_dev_get_module_eeprom(uint16_t port_id, 6653 struct rte_dev_eeprom_info *info) 6654 { 6655 struct rte_eth_dev *dev; 6656 int ret; 6657 6658 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6659 dev = &rte_eth_devices[port_id]; 6660 6661 if (info == NULL) { 6662 RTE_ETHDEV_LOG_LINE(ERR, 6663 "Cannot get ethdev port %u module EEPROM info to NULL", 6664 port_id); 6665 return -EINVAL; 6666 } 6667 6668 if (info->data == NULL) { 6669 RTE_ETHDEV_LOG_LINE(ERR, 6670 "Cannot get ethdev port %u module EEPROM data to NULL", 6671 port_id); 6672 return -EINVAL; 6673 } 6674 6675 if (info->length == 0) { 6676 RTE_ETHDEV_LOG_LINE(ERR, 6677 "Cannot get ethdev port %u module EEPROM to data with zero size", 6678 port_id); 6679 return -EINVAL; 6680 } 6681 6682 if (*dev->dev_ops->get_module_eeprom == NULL) 6683 return -ENOTSUP; 6684 ret = (*dev->dev_ops->get_module_eeprom)(dev, info); 6685 6686 rte_ethdev_trace_get_module_eeprom(port_id, info, ret); 6687 6688 return ret; 6689 } 6690 6691 int 6692 rte_eth_dev_get_dcb_info(uint16_t port_id, 6693 struct rte_eth_dcb_info *dcb_info) 6694 { 6695 struct rte_eth_dev *dev; 6696 int ret; 6697 6698 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6699 dev = &rte_eth_devices[port_id]; 6700 6701 if (dcb_info == NULL) { 6702 RTE_ETHDEV_LOG_LINE(ERR, 6703 "Cannot get ethdev port %u DCB info to NULL", 6704 port_id); 6705 return -EINVAL; 6706 } 6707 6708 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info)); 6709 6710 if (*dev->dev_ops->get_dcb_info == NULL) 6711 return -ENOTSUP; 6712 ret = eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info)); 6713 6714 rte_ethdev_trace_get_dcb_info(port_id, dcb_info, ret); 6715 6716 return ret; 6717 } 6718 6719 static void 6720 eth_dev_adjust_nb_desc(uint16_t *nb_desc, 6721 const struct rte_eth_desc_lim *desc_lim) 6722 { 6723 /* Upcast to uint32 to avoid potential overflow with RTE_ALIGN_CEIL(). */ 6724 uint32_t nb_desc_32 = (uint32_t)*nb_desc; 6725 6726 if (desc_lim->nb_align != 0) 6727 nb_desc_32 = RTE_ALIGN_CEIL(nb_desc_32, desc_lim->nb_align); 6728 6729 if (desc_lim->nb_max != 0) 6730 nb_desc_32 = RTE_MIN(nb_desc_32, desc_lim->nb_max); 6731 6732 nb_desc_32 = RTE_MAX(nb_desc_32, desc_lim->nb_min); 6733 6734 /* Assign clipped u32 back to u16. */ 6735 *nb_desc = (uint16_t)nb_desc_32; 6736 } 6737 6738 int 6739 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id, 6740 uint16_t *nb_rx_desc, 6741 uint16_t *nb_tx_desc) 6742 { 6743 struct rte_eth_dev_info dev_info; 6744 int ret; 6745 6746 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6747 6748 ret = rte_eth_dev_info_get(port_id, &dev_info); 6749 if (ret != 0) 6750 return ret; 6751 6752 if (nb_rx_desc != NULL) 6753 eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim); 6754 6755 if (nb_tx_desc != NULL) 6756 eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim); 6757 6758 rte_ethdev_trace_adjust_nb_rx_tx_desc(port_id); 6759 6760 return 0; 6761 } 6762 6763 int 6764 rte_eth_dev_hairpin_capability_get(uint16_t port_id, 6765 struct rte_eth_hairpin_cap *cap) 6766 { 6767 struct rte_eth_dev *dev; 6768 int ret; 6769 6770 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6771 dev = &rte_eth_devices[port_id]; 6772 6773 if (cap == NULL) { 6774 RTE_ETHDEV_LOG_LINE(ERR, 6775 "Cannot get ethdev port %u hairpin capability to NULL", 6776 port_id); 6777 return -EINVAL; 6778 } 6779 6780 if (*dev->dev_ops->hairpin_cap_get == NULL) 6781 return -ENOTSUP; 6782 memset(cap, 0, sizeof(*cap)); 6783 ret = eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap)); 6784 6785 rte_ethdev_trace_hairpin_capability_get(port_id, cap, ret); 6786 6787 return ret; 6788 } 6789 6790 int 6791 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool) 6792 { 6793 struct rte_eth_dev *dev; 6794 int ret; 6795 6796 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6797 dev = &rte_eth_devices[port_id]; 6798 6799 if (pool == NULL) { 6800 RTE_ETHDEV_LOG_LINE(ERR, 6801 "Cannot test ethdev port %u mempool operation from NULL pool", 6802 port_id); 6803 return -EINVAL; 6804 } 6805 6806 if (*dev->dev_ops->pool_ops_supported == NULL) 6807 return 1; /* all pools are supported */ 6808 6809 ret = (*dev->dev_ops->pool_ops_supported)(dev, pool); 6810 6811 rte_ethdev_trace_pool_ops_supported(port_id, pool, ret); 6812 6813 return ret; 6814 } 6815 6816 int 6817 rte_eth_representor_info_get(uint16_t port_id, 6818 struct rte_eth_representor_info *info) 6819 { 6820 struct rte_eth_dev *dev; 6821 int ret; 6822 6823 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6824 dev = &rte_eth_devices[port_id]; 6825 6826 if (*dev->dev_ops->representor_info_get == NULL) 6827 return -ENOTSUP; 6828 ret = eth_err(port_id, (*dev->dev_ops->representor_info_get)(dev, info)); 6829 6830 rte_eth_trace_representor_info_get(port_id, info, ret); 6831 6832 return ret; 6833 } 6834 6835 int 6836 rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t *features) 6837 { 6838 struct rte_eth_dev *dev; 6839 int ret; 6840 6841 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6842 dev = &rte_eth_devices[port_id]; 6843 6844 if (dev->data->dev_configured != 0) { 6845 RTE_ETHDEV_LOG_LINE(ERR, 6846 "The port (ID=%"PRIu16") is already configured", 6847 port_id); 6848 return -EBUSY; 6849 } 6850 6851 if (features == NULL) { 6852 RTE_ETHDEV_LOG_LINE(ERR, "Invalid features (NULL)"); 6853 return -EINVAL; 6854 } 6855 6856 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0 && 6857 rte_flow_restore_info_dynflag_register() < 0) 6858 *features &= ~RTE_ETH_RX_METADATA_TUNNEL_ID; 6859 6860 if (*dev->dev_ops->rx_metadata_negotiate == NULL) 6861 return -ENOTSUP; 6862 ret = eth_err(port_id, 6863 (*dev->dev_ops->rx_metadata_negotiate)(dev, features)); 6864 6865 rte_eth_trace_rx_metadata_negotiate(port_id, *features, ret); 6866 6867 return ret; 6868 } 6869 6870 int 6871 rte_eth_ip_reassembly_capability_get(uint16_t port_id, 6872 struct rte_eth_ip_reassembly_params *reassembly_capa) 6873 { 6874 struct rte_eth_dev *dev; 6875 int ret; 6876 6877 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6878 dev = &rte_eth_devices[port_id]; 6879 6880 if (dev->data->dev_configured == 0) { 6881 RTE_ETHDEV_LOG_LINE(ERR, 6882 "port_id=%u is not configured, cannot get IP reassembly capability", 6883 port_id); 6884 return -EINVAL; 6885 } 6886 6887 if (reassembly_capa == NULL) { 6888 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get reassembly capability to NULL"); 6889 return -EINVAL; 6890 } 6891 6892 if (*dev->dev_ops->ip_reassembly_capability_get == NULL) 6893 return -ENOTSUP; 6894 memset(reassembly_capa, 0, sizeof(struct rte_eth_ip_reassembly_params)); 6895 6896 ret = eth_err(port_id, (*dev->dev_ops->ip_reassembly_capability_get) 6897 (dev, reassembly_capa)); 6898 6899 rte_eth_trace_ip_reassembly_capability_get(port_id, reassembly_capa, 6900 ret); 6901 6902 return ret; 6903 } 6904 6905 int 6906 rte_eth_ip_reassembly_conf_get(uint16_t port_id, 6907 struct rte_eth_ip_reassembly_params *conf) 6908 { 6909 struct rte_eth_dev *dev; 6910 int ret; 6911 6912 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6913 dev = &rte_eth_devices[port_id]; 6914 6915 if (dev->data->dev_configured == 0) { 6916 RTE_ETHDEV_LOG_LINE(ERR, 6917 "port_id=%u is not configured, cannot get IP reassembly configuration", 6918 port_id); 6919 return -EINVAL; 6920 } 6921 6922 if (conf == NULL) { 6923 RTE_ETHDEV_LOG_LINE(ERR, "Cannot get reassembly info to NULL"); 6924 return -EINVAL; 6925 } 6926 6927 if (*dev->dev_ops->ip_reassembly_conf_get == NULL) 6928 return -ENOTSUP; 6929 memset(conf, 0, sizeof(struct rte_eth_ip_reassembly_params)); 6930 ret = eth_err(port_id, 6931 (*dev->dev_ops->ip_reassembly_conf_get)(dev, conf)); 6932 6933 rte_eth_trace_ip_reassembly_conf_get(port_id, conf, ret); 6934 6935 return ret; 6936 } 6937 6938 int 6939 rte_eth_ip_reassembly_conf_set(uint16_t port_id, 6940 const struct rte_eth_ip_reassembly_params *conf) 6941 { 6942 struct rte_eth_dev *dev; 6943 int ret; 6944 6945 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6946 dev = &rte_eth_devices[port_id]; 6947 6948 if (dev->data->dev_configured == 0) { 6949 RTE_ETHDEV_LOG_LINE(ERR, 6950 "port_id=%u is not configured, cannot set IP reassembly configuration", 6951 port_id); 6952 return -EINVAL; 6953 } 6954 6955 if (dev->data->dev_started != 0) { 6956 RTE_ETHDEV_LOG_LINE(ERR, 6957 "port_id=%u is started, cannot configure IP reassembly params.", 6958 port_id); 6959 return -EINVAL; 6960 } 6961 6962 if (conf == NULL) { 6963 RTE_ETHDEV_LOG_LINE(ERR, 6964 "Invalid IP reassembly configuration (NULL)"); 6965 return -EINVAL; 6966 } 6967 6968 if (*dev->dev_ops->ip_reassembly_conf_set == NULL) 6969 return -ENOTSUP; 6970 ret = eth_err(port_id, 6971 (*dev->dev_ops->ip_reassembly_conf_set)(dev, conf)); 6972 6973 rte_eth_trace_ip_reassembly_conf_set(port_id, conf, ret); 6974 6975 return ret; 6976 } 6977 6978 int 6979 rte_eth_dev_priv_dump(uint16_t port_id, FILE *file) 6980 { 6981 struct rte_eth_dev *dev; 6982 6983 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6984 dev = &rte_eth_devices[port_id]; 6985 6986 if (file == NULL) { 6987 RTE_ETHDEV_LOG_LINE(ERR, "Invalid file (NULL)"); 6988 return -EINVAL; 6989 } 6990 6991 if (*dev->dev_ops->eth_dev_priv_dump == NULL) 6992 return -ENOTSUP; 6993 return eth_err(port_id, (*dev->dev_ops->eth_dev_priv_dump)(dev, file)); 6994 } 6995 6996 int 6997 rte_eth_rx_descriptor_dump(uint16_t port_id, uint16_t queue_id, 6998 uint16_t offset, uint16_t num, FILE *file) 6999 { 7000 struct rte_eth_dev *dev; 7001 7002 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 7003 dev = &rte_eth_devices[port_id]; 7004 7005 if (queue_id >= dev->data->nb_rx_queues) { 7006 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Rx queue_id=%u", queue_id); 7007 return -EINVAL; 7008 } 7009 7010 if (file == NULL) { 7011 RTE_ETHDEV_LOG_LINE(ERR, "Invalid file (NULL)"); 7012 return -EINVAL; 7013 } 7014 7015 if (*dev->dev_ops->eth_rx_descriptor_dump == NULL) 7016 return -ENOTSUP; 7017 7018 return eth_err(port_id, (*dev->dev_ops->eth_rx_descriptor_dump)(dev, 7019 queue_id, offset, num, file)); 7020 } 7021 7022 int 7023 rte_eth_tx_descriptor_dump(uint16_t port_id, uint16_t queue_id, 7024 uint16_t offset, uint16_t num, FILE *file) 7025 { 7026 struct rte_eth_dev *dev; 7027 7028 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 7029 dev = &rte_eth_devices[port_id]; 7030 7031 if (queue_id >= dev->data->nb_tx_queues) { 7032 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Tx queue_id=%u", queue_id); 7033 return -EINVAL; 7034 } 7035 7036 if (file == NULL) { 7037 RTE_ETHDEV_LOG_LINE(ERR, "Invalid file (NULL)"); 7038 return -EINVAL; 7039 } 7040 7041 if (*dev->dev_ops->eth_tx_descriptor_dump == NULL) 7042 return -ENOTSUP; 7043 7044 return eth_err(port_id, (*dev->dev_ops->eth_tx_descriptor_dump)(dev, 7045 queue_id, offset, num, file)); 7046 } 7047 7048 int 7049 rte_eth_buffer_split_get_supported_hdr_ptypes(uint16_t port_id, uint32_t *ptypes, int num) 7050 { 7051 size_t i; 7052 int j; 7053 struct rte_eth_dev *dev; 7054 const uint32_t *all_types; 7055 size_t no_of_elements = 0; 7056 7057 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 7058 dev = &rte_eth_devices[port_id]; 7059 7060 if (ptypes == NULL && num > 0) { 7061 RTE_ETHDEV_LOG_LINE(ERR, 7062 "Cannot get ethdev port %u supported header protocol types to NULL when array size is non zero", 7063 port_id); 7064 return -EINVAL; 7065 } 7066 7067 if (*dev->dev_ops->buffer_split_supported_hdr_ptypes_get == NULL) 7068 return -ENOTSUP; 7069 all_types = (*dev->dev_ops->buffer_split_supported_hdr_ptypes_get)(dev, 7070 &no_of_elements); 7071 7072 if (all_types == NULL) 7073 return 0; 7074 7075 for (i = 0, j = 0; i < no_of_elements; ++i) { 7076 if (j < num) { 7077 ptypes[j] = all_types[i]; 7078 7079 rte_eth_trace_buffer_split_get_supported_hdr_ptypes( 7080 port_id, j, ptypes[j]); 7081 } 7082 j++; 7083 } 7084 7085 return j; 7086 } 7087 7088 int rte_eth_dev_count_aggr_ports(uint16_t port_id) 7089 { 7090 struct rte_eth_dev *dev; 7091 int ret; 7092 7093 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 7094 dev = &rte_eth_devices[port_id]; 7095 7096 if (*dev->dev_ops->count_aggr_ports == NULL) 7097 return 0; 7098 ret = eth_err(port_id, (*dev->dev_ops->count_aggr_ports)(dev)); 7099 7100 rte_eth_trace_count_aggr_ports(port_id, ret); 7101 7102 return ret; 7103 } 7104 7105 int rte_eth_dev_map_aggr_tx_affinity(uint16_t port_id, uint16_t tx_queue_id, 7106 uint8_t affinity) 7107 { 7108 struct rte_eth_dev *dev; 7109 int aggr_ports; 7110 int ret; 7111 7112 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 7113 dev = &rte_eth_devices[port_id]; 7114 7115 if (tx_queue_id >= dev->data->nb_tx_queues) { 7116 RTE_ETHDEV_LOG_LINE(ERR, "Invalid Tx queue_id=%u", tx_queue_id); 7117 return -EINVAL; 7118 } 7119 7120 if (*dev->dev_ops->map_aggr_tx_affinity == NULL) 7121 return -ENOTSUP; 7122 7123 if (dev->data->dev_configured == 0) { 7124 RTE_ETHDEV_LOG_LINE(ERR, 7125 "Port %u must be configured before Tx affinity mapping", 7126 port_id); 7127 return -EINVAL; 7128 } 7129 7130 if (dev->data->dev_started) { 7131 RTE_ETHDEV_LOG_LINE(ERR, 7132 "Port %u must be stopped to allow configuration", 7133 port_id); 7134 return -EBUSY; 7135 } 7136 7137 aggr_ports = rte_eth_dev_count_aggr_ports(port_id); 7138 if (aggr_ports == 0) { 7139 RTE_ETHDEV_LOG_LINE(ERR, 7140 "Port %u has no aggregated port", 7141 port_id); 7142 return -ENOTSUP; 7143 } 7144 7145 if (affinity > aggr_ports) { 7146 RTE_ETHDEV_LOG_LINE(ERR, 7147 "Port %u map invalid affinity %u exceeds the maximum number %u", 7148 port_id, affinity, aggr_ports); 7149 return -EINVAL; 7150 } 7151 7152 ret = eth_err(port_id, (*dev->dev_ops->map_aggr_tx_affinity)(dev, 7153 tx_queue_id, affinity)); 7154 7155 rte_eth_trace_map_aggr_tx_affinity(port_id, tx_queue_id, affinity, ret); 7156 7157 return ret; 7158 } 7159 7160 RTE_LOG_REGISTER_DEFAULT(rte_eth_dev_logtype, INFO); 7161