1*99a2dd95SBruce Richardson /* 2*99a2dd95SBruce Richardson * SPDX-License-Identifier: BSD-3-Clause 3*99a2dd95SBruce Richardson * Copyright (C) IBM Corporation 2014. 4*99a2dd95SBruce Richardson */ 5*99a2dd95SBruce Richardson 6*99a2dd95SBruce Richardson #ifndef _RTE_CPUFLAGS_PPC_64_H_ 7*99a2dd95SBruce Richardson #define _RTE_CPUFLAGS_PPC_64_H_ 8*99a2dd95SBruce Richardson 9*99a2dd95SBruce Richardson /** 10*99a2dd95SBruce Richardson * Enumeration of all CPU features supported 11*99a2dd95SBruce Richardson */ 12*99a2dd95SBruce Richardson enum rte_cpu_flag_t { 13*99a2dd95SBruce Richardson RTE_CPUFLAG_PPC_LE = 0, 14*99a2dd95SBruce Richardson RTE_CPUFLAG_TRUE_LE, 15*99a2dd95SBruce Richardson RTE_CPUFLAG_PSERIES_PERFMON_COMPAT, 16*99a2dd95SBruce Richardson RTE_CPUFLAG_VSX, 17*99a2dd95SBruce Richardson RTE_CPUFLAG_ARCH_2_06, 18*99a2dd95SBruce Richardson RTE_CPUFLAG_POWER6_EXT, 19*99a2dd95SBruce Richardson RTE_CPUFLAG_DFP, 20*99a2dd95SBruce Richardson RTE_CPUFLAG_PA6T, 21*99a2dd95SBruce Richardson RTE_CPUFLAG_ARCH_2_05, 22*99a2dd95SBruce Richardson RTE_CPUFLAG_ICACHE_SNOOP, 23*99a2dd95SBruce Richardson RTE_CPUFLAG_SMT, 24*99a2dd95SBruce Richardson RTE_CPUFLAG_BOOKE, 25*99a2dd95SBruce Richardson RTE_CPUFLAG_CELLBE, 26*99a2dd95SBruce Richardson RTE_CPUFLAG_POWER5_PLUS, 27*99a2dd95SBruce Richardson RTE_CPUFLAG_POWER5, 28*99a2dd95SBruce Richardson RTE_CPUFLAG_POWER4, 29*99a2dd95SBruce Richardson RTE_CPUFLAG_NOTB, 30*99a2dd95SBruce Richardson RTE_CPUFLAG_EFP_DOUBLE, 31*99a2dd95SBruce Richardson RTE_CPUFLAG_EFP_SINGLE, 32*99a2dd95SBruce Richardson RTE_CPUFLAG_SPE, 33*99a2dd95SBruce Richardson RTE_CPUFLAG_UNIFIED_CACHE, 34*99a2dd95SBruce Richardson RTE_CPUFLAG_4xxMAC, 35*99a2dd95SBruce Richardson RTE_CPUFLAG_MMU, 36*99a2dd95SBruce Richardson RTE_CPUFLAG_FPU, 37*99a2dd95SBruce Richardson RTE_CPUFLAG_ALTIVEC, 38*99a2dd95SBruce Richardson RTE_CPUFLAG_PPC601, 39*99a2dd95SBruce Richardson RTE_CPUFLAG_PPC64, 40*99a2dd95SBruce Richardson RTE_CPUFLAG_PPC32, 41*99a2dd95SBruce Richardson RTE_CPUFLAG_TAR, 42*99a2dd95SBruce Richardson RTE_CPUFLAG_LSEL, 43*99a2dd95SBruce Richardson RTE_CPUFLAG_EBB, 44*99a2dd95SBruce Richardson RTE_CPUFLAG_DSCR, 45*99a2dd95SBruce Richardson RTE_CPUFLAG_HTM, 46*99a2dd95SBruce Richardson RTE_CPUFLAG_ARCH_2_07, 47*99a2dd95SBruce Richardson }; 48*99a2dd95SBruce Richardson 49*99a2dd95SBruce Richardson #include "generic/rte_cpuflags.h" 50*99a2dd95SBruce Richardson 51*99a2dd95SBruce Richardson #endif /* _RTE_CPUFLAGS_PPC_64_H_ */ 52