1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #ifndef _RTE_PREFETCH_H_ 6 #define _RTE_PREFETCH_H_ 7 8 #include <rte_compat.h> 9 10 /** 11 * @file 12 * 13 * Prefetch operations. 14 * 15 * This file defines an API for prefetch macros / inline-functions, 16 * which are architecture-dependent. Prefetching occurs when a 17 * processor requests an instruction or data from memory to cache 18 * before it is actually needed, potentially speeding up the execution of the 19 * program. 20 */ 21 22 /** 23 * Prefetch a cache line into all cache levels. 24 * @param p 25 * Address to prefetch 26 */ 27 static inline void rte_prefetch0(const volatile void *p); 28 29 /** 30 * Prefetch a cache line into all cache levels except the 0th cache level. 31 * @param p 32 * Address to prefetch 33 */ 34 static inline void rte_prefetch1(const volatile void *p); 35 36 /** 37 * Prefetch a cache line into all cache levels except the 0th and 1th cache 38 * levels. 39 * @param p 40 * Address to prefetch 41 */ 42 static inline void rte_prefetch2(const volatile void *p); 43 44 /** 45 * Prefetch a cache line into all cache levels (non-temporal/transient version) 46 * 47 * The non-temporal prefetch is intended as a prefetch hint that processor will 48 * use the prefetched data only once or short period, unlike the 49 * rte_prefetch0() function which imply that prefetched data to use repeatedly. 50 * 51 * @param p 52 * Address to prefetch 53 */ 54 static inline void rte_prefetch_non_temporal(const volatile void *p); 55 56 /** 57 * @warning 58 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 59 * 60 * Prefetch a cache line into all cache levels, with intention to write. This 61 * prefetch variant hints to the CPU that the program is expecting to write to 62 * the cache line being prefetched. 63 * 64 * @param p Address to prefetch 65 */ 66 __rte_experimental 67 static inline void 68 rte_prefetch0_write(const void *p) 69 { 70 /* 1 indicates intention to write, 3 sets target cache level to L1. See 71 * GCC docs where these integer constants are described in more detail: 72 * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html 73 */ 74 #ifdef RTE_TOOLCHAIN_MSVC 75 rte_prefetch0(p); 76 #else 77 __builtin_prefetch(p, 1, 3); 78 #endif 79 } 80 81 /** 82 * @warning 83 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 84 * 85 * Prefetch a cache line into all cache levels, except the 0th, with intention 86 * to write. This prefetch variant hints to the CPU that the program is 87 * expecting to write to the cache line being prefetched. 88 * 89 * @param p Address to prefetch 90 */ 91 __rte_experimental 92 static inline void 93 rte_prefetch1_write(const void *p) 94 { 95 /* 1 indicates intention to write, 2 sets target cache level to L2. See 96 * GCC docs where these integer constants are described in more detail: 97 * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html 98 */ 99 #ifdef RTE_TOOLCHAIN_MSVC 100 rte_prefetch1(p); 101 #else 102 __builtin_prefetch(p, 1, 2); 103 #endif 104 } 105 106 /** 107 * @warning 108 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 109 * 110 * Prefetch a cache line into all cache levels, except the 0th and 1st, with 111 * intention to write. This prefetch variant hints to the CPU that the program 112 * is expecting to write to the cache line being prefetched. 113 * 114 * @param p Address to prefetch 115 */ 116 __rte_experimental 117 static inline void 118 rte_prefetch2_write(const void *p) 119 { 120 /* 1 indicates intention to write, 1 sets target cache level to L3. See 121 * GCC docs where these integer constants are described in more detail: 122 * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html 123 */ 124 #ifdef RTE_TOOLCHAIN_MSVC 125 rte_prefetch2(p); 126 #else 127 __builtin_prefetch(p, 1, 1); 128 #endif 129 } 130 131 /** 132 * @warning 133 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 134 * 135 * Demote a cache line to a more distant level of cache from the processor. 136 * CLDEMOTE hints to hardware to move (demote) a cache line from the closest to 137 * the processor to a level more distant from the processor. It is a hint and 138 * not guaranteed. rte_cldemote is intended to move the cache line to the more 139 * remote cache, where it expects sharing to be efficient and to indicate that 140 * a line may be accessed by a different core in the future. 141 * 142 * @param p 143 * Address to demote 144 */ 145 __rte_experimental 146 static inline void 147 rte_cldemote(const volatile void *p); 148 149 #endif /* _RTE_PREFETCH_H_ */ 150