173d844fdSHarman Kalra /* SPDX-License-Identifier: BSD-3-Clause 273d844fdSHarman Kalra * Copyright(c) 2010-2014 Intel Corporation 373d844fdSHarman Kalra */ 473d844fdSHarman Kalra 573d844fdSHarman Kalra #ifndef EAL_INTERRUPTS_H 673d844fdSHarman Kalra #define EAL_INTERRUPTS_H 773d844fdSHarman Kalra 873d844fdSHarman Kalra struct rte_intr_handle { 973d844fdSHarman Kalra union { 1073d844fdSHarman Kalra struct { 1199e6c7e3SHarman Kalra int dev_fd; /**< VFIO/UIO cfg device file descriptor */ 1273d844fdSHarman Kalra int fd; /**< interrupt event file descriptor */ 1373d844fdSHarman Kalra }; 1473d844fdSHarman Kalra void *windows_handle; /**< device driver handle */ 1573d844fdSHarman Kalra }; 1673d844fdSHarman Kalra uint32_t alloc_flags; /**< flags passed at allocation */ 1773d844fdSHarman Kalra enum rte_intr_handle_type type; /**< handle type */ 1873d844fdSHarman Kalra uint32_t max_intr; /**< max interrupt requested */ 1973d844fdSHarman Kalra uint32_t nb_efd; /**< number of available efd(event fd) */ 2073d844fdSHarman Kalra uint8_t efd_counter_size; /**< size of efd counter, used for vdev */ 2173d844fdSHarman Kalra uint16_t nb_intr; 2273d844fdSHarman Kalra /**< Max vector count, default RTE_MAX_RXTX_INTR_VEC_ID */ 23*8cb5d08dSHarman Kalra int *efds; /**< intr vectors/efds mapping */ 24*8cb5d08dSHarman Kalra struct rte_epoll_event *elist; /**< intr vector epoll event */ 2573d844fdSHarman Kalra uint16_t vec_list_size; 2673d844fdSHarman Kalra int *intr_vec; /**< intr vector number array */ 2773d844fdSHarman Kalra }; 2873d844fdSHarman Kalra 2973d844fdSHarman Kalra #endif /* EAL_INTERRUPTS_H */ 30