1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _MAIN_H_ 35 #define _MAIN_H_ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 #include <rte_sched.h> 42 43 #define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1 44 45 /* 46 * Configurable number of RX/TX ring descriptors 47 */ 48 #define APP_INTERACTIVE_DEFAULT 0 49 50 #define APP_RX_DESC_DEFAULT 128 51 #define APP_TX_DESC_DEFAULT 256 52 53 #define APP_RING_SIZE (8*1024) 54 #define NB_MBUF (2*1024*1024) 55 56 #define MAX_PKT_RX_BURST 64 57 #define PKT_ENQUEUE 64 58 #define PKT_DEQUEUE 32 59 #define MAX_PKT_TX_BURST 64 60 61 #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */ 62 #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */ 63 #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */ 64 65 #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */ 66 #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */ 67 #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */ 68 69 #define BURST_TX_DRAIN_US 100 70 71 #define MAX_DATA_STREAMS (RTE_MAX_LCORE/2) 72 #define MAX_SCHED_SUBPORTS 8 73 #define MAX_SCHED_PIPES 4096 74 75 #ifndef APP_COLLECT_STAT 76 #define APP_COLLECT_STAT 1 77 #endif 78 79 #if APP_COLLECT_STAT 80 #define APP_STATS_ADD(stat,val) (stat) += (val) 81 #else 82 #define APP_STATS_ADD(stat,val) do {(void) (val);} while (0) 83 #endif 84 85 #define APP_QAVG_NTIMES 10 86 #define APP_QAVG_PERIOD 100 87 88 struct thread_stat 89 { 90 uint64_t nb_rx; 91 uint64_t nb_drop; 92 }; 93 94 95 struct thread_conf 96 { 97 uint32_t counter; 98 uint32_t n_mbufs; 99 struct rte_mbuf **m_table; 100 101 uint8_t rx_port; 102 uint8_t tx_port; 103 uint16_t rx_queue; 104 uint16_t tx_queue; 105 struct rte_ring *rx_ring; 106 struct rte_ring *tx_ring; 107 struct rte_sched_port *sched_port; 108 109 #if APP_COLLECT_STAT 110 struct thread_stat stat; 111 #endif 112 } __rte_cache_aligned; 113 114 115 struct flow_conf 116 { 117 uint32_t rx_core; 118 uint32_t wt_core; 119 uint32_t tx_core; 120 uint8_t rx_port; 121 uint8_t tx_port; 122 uint16_t rx_queue; 123 uint16_t tx_queue; 124 struct rte_ring *rx_ring; 125 struct rte_ring *tx_ring; 126 struct rte_sched_port *sched_port; 127 struct rte_mempool *mbuf_pool; 128 129 struct thread_conf rx_thread; 130 struct thread_conf wt_thread; 131 struct thread_conf tx_thread; 132 }; 133 134 135 struct ring_conf 136 { 137 uint32_t rx_size; 138 uint32_t ring_size; 139 uint32_t tx_size; 140 }; 141 142 struct burst_conf 143 { 144 uint16_t rx_burst; 145 uint16_t ring_burst; 146 uint16_t qos_dequeue; 147 uint16_t tx_burst; 148 }; 149 150 struct ring_thresh 151 { 152 uint8_t pthresh; /**< Ring prefetch threshold. */ 153 uint8_t hthresh; /**< Ring host threshold. */ 154 uint8_t wthresh; /**< Ring writeback threshold. */ 155 }; 156 157 extern uint8_t interactive; 158 extern uint32_t qavg_period; 159 extern uint32_t qavg_ntimes; 160 extern uint32_t nb_pfc; 161 extern const char *cfg_profile; 162 extern int mp_size; 163 extern struct flow_conf qos_conf[]; 164 extern int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 165 166 extern struct ring_conf ring_conf; 167 extern struct burst_conf burst_conf; 168 extern struct ring_thresh rx_thresh; 169 extern struct ring_thresh tx_thresh; 170 171 extern struct rte_sched_port_params port_params; 172 173 int app_parse_args(int argc, char **argv); 174 int app_init(void); 175 176 void prompt(void); 177 void app_rx_thread(struct thread_conf **qconf); 178 void app_tx_thread(struct thread_conf **qconf); 179 void app_worker_thread(struct thread_conf **qconf); 180 void app_mixed_thread(struct thread_conf **qconf); 181 182 void app_stat(void); 183 int subport_stat(uint8_t port_id, uint32_t subport_id); 184 int pipe_stat(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id); 185 int qavg_q(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id, uint8_t tc, uint8_t q); 186 int qavg_tcpipe(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id, uint8_t tc); 187 int qavg_pipe(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id); 188 int qavg_tcsubport(uint8_t port_id, uint32_t subport_id, uint8_t tc); 189 int qavg_subport(uint8_t port_id, uint32_t subport_id); 190 191 #ifdef __cplusplus 192 } 193 #endif 194 195 #endif /* _MAIN_H_ */ 196