13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #ifndef _MAIN_H_ 6de3cfa2cSIntel #define _MAIN_H_ 7de3cfa2cSIntel 8*719834a6SMattias Rönnblom #include <rte_sched.h> 9*719834a6SMattias Rönnblom 10de3cfa2cSIntel #ifdef __cplusplus 11de3cfa2cSIntel extern "C" { 12de3cfa2cSIntel #endif 13de3cfa2cSIntel 14de3cfa2cSIntel #define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1 15de3cfa2cSIntel 16de3cfa2cSIntel /* 17de3cfa2cSIntel * Configurable number of RX/TX ring descriptors 18de3cfa2cSIntel */ 19cfd5c971SIntel #define APP_INTERACTIVE_DEFAULT 0 20cfd5c971SIntel 21867a6c66SKevin Laatz #define APP_RX_DESC_DEFAULT 1024 22867a6c66SKevin Laatz #define APP_TX_DESC_DEFAULT 1024 23de3cfa2cSIntel 24de3cfa2cSIntel #define APP_RING_SIZE (8*1024) 25e93b24a3SIntel #define NB_MBUF (2*1024*1024) 26de3cfa2cSIntel 27de3cfa2cSIntel #define MAX_PKT_RX_BURST 64 28de3cfa2cSIntel #define PKT_ENQUEUE 64 2947fbbfe7SBruce Richardson #define PKT_DEQUEUE 63 30de3cfa2cSIntel #define MAX_PKT_TX_BURST 64 31de3cfa2cSIntel 32de3cfa2cSIntel #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */ 33de3cfa2cSIntel #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */ 34de3cfa2cSIntel #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */ 35de3cfa2cSIntel 36de3cfa2cSIntel #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */ 37de3cfa2cSIntel #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */ 38de3cfa2cSIntel #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */ 39de3cfa2cSIntel 404e43299dSBruce Richardson #define MAX_DATA_STREAMS RTE_MAX_LCORE/2 41de3cfa2cSIntel #define MAX_SCHED_SUBPORTS 8 42de3cfa2cSIntel #define MAX_SCHED_PIPES 4096 43be1e5332SJasvinder Singh #define MAX_SCHED_PIPE_PROFILES 256 44802d214dSSavinay Dharmappa #define MAX_SCHED_SUBPORT_PROFILES 8 45de3cfa2cSIntel 46de3cfa2cSIntel #ifndef APP_COLLECT_STAT 47de3cfa2cSIntel #define APP_COLLECT_STAT 1 48de3cfa2cSIntel #endif 49de3cfa2cSIntel 50de3cfa2cSIntel #if APP_COLLECT_STAT 51de3cfa2cSIntel #define APP_STATS_ADD(stat,val) (stat) += (val) 52de3cfa2cSIntel #else 53de3cfa2cSIntel #define APP_STATS_ADD(stat,val) do {(void) (val);} while (0) 54de3cfa2cSIntel #endif 55de3cfa2cSIntel 56cfd5c971SIntel #define APP_QAVG_NTIMES 10 57cfd5c971SIntel #define APP_QAVG_PERIOD 100 58cfd5c971SIntel 59de3cfa2cSIntel struct thread_stat 60de3cfa2cSIntel { 61de3cfa2cSIntel uint64_t nb_rx; 62de3cfa2cSIntel uint64_t nb_drop; 63de3cfa2cSIntel }; 64de3cfa2cSIntel 65de3cfa2cSIntel 667e06c0deSTyler Retzlaff struct __rte_cache_aligned thread_conf 67de3cfa2cSIntel { 68f8244c63SZhiyong Yang uint16_t rx_port; 69f8244c63SZhiyong Yang uint16_t tx_port; 70de3cfa2cSIntel uint16_t rx_queue; 71de3cfa2cSIntel uint16_t tx_queue; 72de3cfa2cSIntel struct rte_ring *rx_ring; 73de3cfa2cSIntel struct rte_ring *tx_ring; 74de3cfa2cSIntel struct rte_sched_port *sched_port; 75de3cfa2cSIntel 76de3cfa2cSIntel #if APP_COLLECT_STAT 77de3cfa2cSIntel struct thread_stat stat; 78de3cfa2cSIntel #endif 797e06c0deSTyler Retzlaff }; 80de3cfa2cSIntel 81de3cfa2cSIntel 82de3cfa2cSIntel struct flow_conf 83de3cfa2cSIntel { 84de3cfa2cSIntel uint32_t rx_core; 85de3cfa2cSIntel uint32_t wt_core; 86de3cfa2cSIntel uint32_t tx_core; 87f8244c63SZhiyong Yang uint16_t rx_port; 88f8244c63SZhiyong Yang uint16_t tx_port; 89de3cfa2cSIntel uint16_t rx_queue; 90de3cfa2cSIntel uint16_t tx_queue; 91de3cfa2cSIntel struct rte_ring *rx_ring; 92de3cfa2cSIntel struct rte_ring *tx_ring; 93de3cfa2cSIntel struct rte_sched_port *sched_port; 94de3cfa2cSIntel struct rte_mempool *mbuf_pool; 95de3cfa2cSIntel 96de3cfa2cSIntel struct thread_conf rx_thread; 97de3cfa2cSIntel struct thread_conf wt_thread; 98de3cfa2cSIntel struct thread_conf tx_thread; 99de3cfa2cSIntel }; 100de3cfa2cSIntel 101de3cfa2cSIntel 102de3cfa2cSIntel struct ring_conf 103de3cfa2cSIntel { 104de3cfa2cSIntel uint32_t rx_size; 105de3cfa2cSIntel uint32_t ring_size; 106de3cfa2cSIntel uint32_t tx_size; 107de3cfa2cSIntel }; 108de3cfa2cSIntel 109de3cfa2cSIntel struct burst_conf 110de3cfa2cSIntel { 111de3cfa2cSIntel uint16_t rx_burst; 112de3cfa2cSIntel uint16_t ring_burst; 113de3cfa2cSIntel uint16_t qos_dequeue; 114de3cfa2cSIntel uint16_t tx_burst; 115de3cfa2cSIntel }; 116de3cfa2cSIntel 117de3cfa2cSIntel struct ring_thresh 118de3cfa2cSIntel { 119de3cfa2cSIntel uint8_t pthresh; /**< Ring prefetch threshold. */ 120de3cfa2cSIntel uint8_t hthresh; /**< Ring host threshold. */ 121de3cfa2cSIntel uint8_t wthresh; /**< Ring writeback threshold. */ 122de3cfa2cSIntel }; 123de3cfa2cSIntel 124cfd5c971SIntel extern uint8_t interactive; 125cfd5c971SIntel extern uint32_t qavg_period; 126cfd5c971SIntel extern uint32_t qavg_ntimes; 127de3cfa2cSIntel extern uint32_t nb_pfc; 128de3cfa2cSIntel extern const char *cfg_profile; 129e93b24a3SIntel extern int mp_size; 130de3cfa2cSIntel extern struct flow_conf qos_conf[]; 131de3cfa2cSIntel extern int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 132de3cfa2cSIntel 133de3cfa2cSIntel extern struct ring_conf ring_conf; 134de3cfa2cSIntel extern struct burst_conf burst_conf; 135de3cfa2cSIntel extern struct ring_thresh rx_thresh; 136de3cfa2cSIntel extern struct ring_thresh tx_thresh; 137de3cfa2cSIntel 138345187bdSTimothy Redaelli extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE]; 139345187bdSTimothy Redaelli extern uint32_t n_active_queues; 140be1e5332SJasvinder Singh 141de3cfa2cSIntel extern struct rte_sched_port_params port_params; 14206135957SWojciech Liguzinski extern struct rte_sched_cman_params cman_params; 143b0c1628bSJasvinder Singh extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS]; 144de3cfa2cSIntel 145de3cfa2cSIntel int app_parse_args(int argc, char **argv); 146de3cfa2cSIntel int app_init(void); 147de3cfa2cSIntel 148cfd5c971SIntel void prompt(void); 149de3cfa2cSIntel void app_rx_thread(struct thread_conf **qconf); 150de3cfa2cSIntel void app_tx_thread(struct thread_conf **qconf); 151de3cfa2cSIntel void app_worker_thread(struct thread_conf **qconf); 152de3cfa2cSIntel void app_mixed_thread(struct thread_conf **qconf); 153de3cfa2cSIntel 154cfd5c971SIntel void app_stat(void); 155f8244c63SZhiyong Yang int subport_stat(uint16_t port_id, uint32_t subport_id); 156f8244c63SZhiyong Yang int pipe_stat(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id); 157f8244c63SZhiyong Yang int qavg_q(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id, 158f8244c63SZhiyong Yang uint8_t tc, uint8_t q); 159f8244c63SZhiyong Yang int qavg_tcpipe(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id, 160f8244c63SZhiyong Yang uint8_t tc); 161f8244c63SZhiyong Yang int qavg_pipe(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id); 162f8244c63SZhiyong Yang int qavg_tcsubport(uint16_t port_id, uint32_t subport_id, uint8_t tc); 163f8244c63SZhiyong Yang int qavg_subport(uint16_t port_id, uint32_t subport_id); 164de3cfa2cSIntel 165de3cfa2cSIntel #ifdef __cplusplus 166de3cfa2cSIntel } 167de3cfa2cSIntel #endif 168de3cfa2cSIntel 169de3cfa2cSIntel #endif /* _MAIN_H_ */ 170