1de3cfa2cSIntel /*- 2de3cfa2cSIntel * BSD LICENSE 3de3cfa2cSIntel * 4e9d48c00SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5de3cfa2cSIntel * All rights reserved. 6de3cfa2cSIntel * 7de3cfa2cSIntel * Redistribution and use in source and binary forms, with or without 8de3cfa2cSIntel * modification, are permitted provided that the following conditions 9de3cfa2cSIntel * are met: 10de3cfa2cSIntel * 11de3cfa2cSIntel * * Redistributions of source code must retain the above copyright 12de3cfa2cSIntel * notice, this list of conditions and the following disclaimer. 13de3cfa2cSIntel * * Redistributions in binary form must reproduce the above copyright 14de3cfa2cSIntel * notice, this list of conditions and the following disclaimer in 15de3cfa2cSIntel * the documentation and/or other materials provided with the 16de3cfa2cSIntel * distribution. 17de3cfa2cSIntel * * Neither the name of Intel Corporation nor the names of its 18de3cfa2cSIntel * contributors may be used to endorse or promote products derived 19de3cfa2cSIntel * from this software without specific prior written permission. 20de3cfa2cSIntel * 21de3cfa2cSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22de3cfa2cSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23de3cfa2cSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24de3cfa2cSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25de3cfa2cSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26de3cfa2cSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27de3cfa2cSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28de3cfa2cSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29de3cfa2cSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30de3cfa2cSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31de3cfa2cSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32de3cfa2cSIntel */ 33de3cfa2cSIntel 34de3cfa2cSIntel #include <unistd.h> 35de3cfa2cSIntel #include <stdint.h> 36de3cfa2cSIntel 37de3cfa2cSIntel #include <rte_log.h> 38de3cfa2cSIntel #include <rte_mbuf.h> 39de3cfa2cSIntel #include <rte_malloc.h> 40de3cfa2cSIntel #include <rte_cycles.h> 41de3cfa2cSIntel #include <rte_ethdev.h> 42de3cfa2cSIntel #include <rte_memcpy.h> 43de3cfa2cSIntel #include <rte_byteorder.h> 44de3cfa2cSIntel #include <rte_branch_prediction.h> 45de3cfa2cSIntel 46de3cfa2cSIntel #include <rte_sched.h> 47de3cfa2cSIntel 48de3cfa2cSIntel #include "main.h" 49de3cfa2cSIntel 50de3cfa2cSIntel #define APP_MODE_NONE 0 51de3cfa2cSIntel #define APP_RX_MODE 1 52de3cfa2cSIntel #define APP_WT_MODE 2 53de3cfa2cSIntel #define APP_TX_MODE 4 54de3cfa2cSIntel 55cfd5c971SIntel uint8_t interactive = APP_INTERACTIVE_DEFAULT; 56cfd5c971SIntel uint32_t qavg_period = APP_QAVG_PERIOD; 57cfd5c971SIntel uint32_t qavg_ntimes = APP_QAVG_NTIMES; 58de3cfa2cSIntel 59de3cfa2cSIntel /* main processing loop */ 60de3cfa2cSIntel static int 61de3cfa2cSIntel app_main_loop(__attribute__((unused))void *dummy) 62de3cfa2cSIntel { 63de3cfa2cSIntel uint32_t lcore_id; 64de3cfa2cSIntel uint32_t i, mode; 65de3cfa2cSIntel uint32_t rx_idx = 0; 66de3cfa2cSIntel uint32_t wt_idx = 0; 67de3cfa2cSIntel uint32_t tx_idx = 0; 68de3cfa2cSIntel struct thread_conf *rx_confs[MAX_DATA_STREAMS]; 69de3cfa2cSIntel struct thread_conf *wt_confs[MAX_DATA_STREAMS]; 70de3cfa2cSIntel struct thread_conf *tx_confs[MAX_DATA_STREAMS]; 71de3cfa2cSIntel 72de3cfa2cSIntel memset(rx_confs, 0, sizeof(rx_confs)); 73de3cfa2cSIntel memset(wt_confs, 0, sizeof(wt_confs)); 74de3cfa2cSIntel memset(tx_confs, 0, sizeof(tx_confs)); 75de3cfa2cSIntel 76de3cfa2cSIntel 77de3cfa2cSIntel mode = APP_MODE_NONE; 78de3cfa2cSIntel lcore_id = rte_lcore_id(); 79de3cfa2cSIntel 80de3cfa2cSIntel for (i = 0; i < nb_pfc; i++) { 81de3cfa2cSIntel struct flow_conf *flow = &qos_conf[i]; 82de3cfa2cSIntel 83de3cfa2cSIntel if (flow->rx_core == lcore_id) { 84de3cfa2cSIntel flow->rx_thread.rx_port = flow->rx_port; 85de3cfa2cSIntel flow->rx_thread.rx_ring = flow->rx_ring; 86de3cfa2cSIntel flow->rx_thread.rx_queue = flow->rx_queue; 87de3cfa2cSIntel 88de3cfa2cSIntel rx_confs[rx_idx++] = &flow->rx_thread; 89de3cfa2cSIntel 90de3cfa2cSIntel mode |= APP_RX_MODE; 91de3cfa2cSIntel } 92de3cfa2cSIntel if (flow->tx_core == lcore_id) { 93de3cfa2cSIntel flow->tx_thread.tx_port = flow->tx_port; 94de3cfa2cSIntel flow->tx_thread.tx_ring = flow->tx_ring; 95de3cfa2cSIntel flow->tx_thread.tx_queue = flow->tx_queue; 96de3cfa2cSIntel 97de3cfa2cSIntel tx_confs[tx_idx++] = &flow->tx_thread; 98de3cfa2cSIntel 99de3cfa2cSIntel mode |= APP_TX_MODE; 100de3cfa2cSIntel } 101de3cfa2cSIntel if (flow->wt_core == lcore_id) { 102de3cfa2cSIntel flow->wt_thread.rx_ring = flow->rx_ring; 103de3cfa2cSIntel flow->wt_thread.tx_ring = flow->tx_ring; 104de3cfa2cSIntel flow->wt_thread.tx_port = flow->tx_port; 105de3cfa2cSIntel flow->wt_thread.sched_port = flow->sched_port; 106de3cfa2cSIntel 107de3cfa2cSIntel wt_confs[wt_idx++] = &flow->wt_thread; 108de3cfa2cSIntel 109de3cfa2cSIntel mode |= APP_WT_MODE; 110de3cfa2cSIntel } 111de3cfa2cSIntel } 112de3cfa2cSIntel 113de3cfa2cSIntel if (mode == APP_MODE_NONE) { 114de3cfa2cSIntel RTE_LOG(INFO, APP, "lcore %u has nothing to do\n", lcore_id); 115de3cfa2cSIntel return -1; 116de3cfa2cSIntel } 117de3cfa2cSIntel 118de3cfa2cSIntel if (mode == (APP_RX_MODE | APP_WT_MODE)) { 119de3cfa2cSIntel RTE_LOG(INFO, APP, "lcore %u was configured for both RX and WT !!!\n", 120de3cfa2cSIntel lcore_id); 121de3cfa2cSIntel return -1; 122de3cfa2cSIntel } 123de3cfa2cSIntel 124de3cfa2cSIntel RTE_LOG(INFO, APP, "entering main loop on lcore %u\n", lcore_id); 125de3cfa2cSIntel /* initialize mbuf memory */ 126de3cfa2cSIntel if (mode == APP_RX_MODE) { 127de3cfa2cSIntel for (i = 0; i < rx_idx; i++) { 128e8ed6c78SBruce Richardson RTE_LOG(INFO, APP, "flow %u lcoreid %u " 129e8ed6c78SBruce Richardson "reading port %"PRIu8"\n", 130de3cfa2cSIntel i, lcore_id, rx_confs[i]->rx_port); 131de3cfa2cSIntel } 132de3cfa2cSIntel 133de3cfa2cSIntel app_rx_thread(rx_confs); 134de3cfa2cSIntel } 135de3cfa2cSIntel else if (mode == (APP_TX_MODE | APP_WT_MODE)) { 136de3cfa2cSIntel for (i = 0; i < wt_idx; i++) { 137de3cfa2cSIntel wt_confs[i]->m_table = rte_malloc("table_wt", sizeof(struct rte_mbuf *) 138de3cfa2cSIntel * burst_conf.tx_burst, CACHE_LINE_SIZE); 139de3cfa2cSIntel 140de3cfa2cSIntel if (wt_confs[i]->m_table == NULL) 141de3cfa2cSIntel rte_panic("flow %u unable to allocate memory buffer\n", i); 142de3cfa2cSIntel 143e8ed6c78SBruce Richardson RTE_LOG(INFO, APP, "flow %u lcoreid %u sched+write " 144e8ed6c78SBruce Richardson "port %"PRIu8"\n", 145de3cfa2cSIntel i, lcore_id, wt_confs[i]->tx_port); 146de3cfa2cSIntel } 147de3cfa2cSIntel 148de3cfa2cSIntel app_mixed_thread(wt_confs); 149de3cfa2cSIntel } 150de3cfa2cSIntel else if (mode == APP_TX_MODE) { 151de3cfa2cSIntel for (i = 0; i < tx_idx; i++) { 152de3cfa2cSIntel tx_confs[i]->m_table = rte_malloc("table_tx", sizeof(struct rte_mbuf *) 153de3cfa2cSIntel * burst_conf.tx_burst, CACHE_LINE_SIZE); 154de3cfa2cSIntel 155de3cfa2cSIntel if (tx_confs[i]->m_table == NULL) 156de3cfa2cSIntel rte_panic("flow %u unable to allocate memory buffer\n", i); 157de3cfa2cSIntel 158e8ed6c78SBruce Richardson RTE_LOG(INFO, APP, "flow %u lcoreid %u " 159e8ed6c78SBruce Richardson "writing port %"PRIu8"\n", 160de3cfa2cSIntel i, lcore_id, tx_confs[i]->tx_port); 161de3cfa2cSIntel } 162de3cfa2cSIntel 163de3cfa2cSIntel app_tx_thread(tx_confs); 164de3cfa2cSIntel } 165de3cfa2cSIntel else if (mode == APP_WT_MODE){ 166de3cfa2cSIntel for (i = 0; i < wt_idx; i++) { 167de3cfa2cSIntel RTE_LOG(INFO, APP, "flow %u lcoreid %u scheduling \n", i, lcore_id); 168de3cfa2cSIntel } 169de3cfa2cSIntel 170de3cfa2cSIntel app_worker_thread(wt_confs); 171de3cfa2cSIntel } 172de3cfa2cSIntel 173de3cfa2cSIntel return 0; 174de3cfa2cSIntel } 175de3cfa2cSIntel 176cfd5c971SIntel void 177de3cfa2cSIntel app_stat(void) 178de3cfa2cSIntel { 179de3cfa2cSIntel uint32_t i; 180de3cfa2cSIntel struct rte_eth_stats stats; 181de3cfa2cSIntel static struct rte_eth_stats rx_stats[MAX_DATA_STREAMS]; 182de3cfa2cSIntel static struct rte_eth_stats tx_stats[MAX_DATA_STREAMS]; 183de3cfa2cSIntel 184de3cfa2cSIntel /* print statistics */ 185de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 186de3cfa2cSIntel struct flow_conf *flow = &qos_conf[i]; 187de3cfa2cSIntel 188de3cfa2cSIntel rte_eth_stats_get(flow->rx_port, &stats); 189e8ed6c78SBruce Richardson printf("\nRX port %"PRIu8": rx: %"PRIu64 " err: %"PRIu64 190e8ed6c78SBruce Richardson " no_mbuf: %"PRIu64 "\n", 191de3cfa2cSIntel flow->rx_port, 192de3cfa2cSIntel stats.ipackets - rx_stats[i].ipackets, 193de3cfa2cSIntel stats.ierrors - rx_stats[i].ierrors, 194de3cfa2cSIntel stats.rx_nombuf - rx_stats[i].rx_nombuf); 195de3cfa2cSIntel memcpy(&rx_stats[i], &stats, sizeof(stats)); 196de3cfa2cSIntel 197de3cfa2cSIntel rte_eth_stats_get(flow->tx_port, &stats); 198e8ed6c78SBruce Richardson printf("TX port %"PRIu8": tx: %" PRIu64 " err: %" PRIu64 "\n", 199de3cfa2cSIntel flow->tx_port, 200de3cfa2cSIntel stats.opackets - tx_stats[i].opackets, 201de3cfa2cSIntel stats.oerrors - tx_stats[i].oerrors); 202de3cfa2cSIntel memcpy(&tx_stats[i], &stats, sizeof(stats)); 203de3cfa2cSIntel 204de3cfa2cSIntel //printf("MP = %d\n", rte_mempool_count(conf->app_pktmbuf_pool)); 205de3cfa2cSIntel 206de3cfa2cSIntel #if APP_COLLECT_STAT 207de3cfa2cSIntel printf("-------+------------+------------+\n"); 208de3cfa2cSIntel printf(" | received | dropped |\n"); 209de3cfa2cSIntel printf("-------+------------+------------+\n"); 210de3cfa2cSIntel printf(" RX | %10" PRIu64 " | %10" PRIu64 " |\n", 211de3cfa2cSIntel flow->rx_thread.stat.nb_rx, 212de3cfa2cSIntel flow->rx_thread.stat.nb_drop); 213de3cfa2cSIntel printf("QOS+TX | %10" PRIu64 " | %10" PRIu64 " | pps: %"PRIu64 " \n", 214de3cfa2cSIntel flow->wt_thread.stat.nb_rx, 215de3cfa2cSIntel flow->wt_thread.stat.nb_drop, 216de3cfa2cSIntel flow->wt_thread.stat.nb_rx - flow->wt_thread.stat.nb_drop); 217de3cfa2cSIntel printf("-------+------------+------------+\n"); 218de3cfa2cSIntel 219de3cfa2cSIntel memset(&flow->rx_thread.stat, 0, sizeof(struct thread_stat)); 220de3cfa2cSIntel memset(&flow->wt_thread.stat, 0, sizeof(struct thread_stat)); 221de3cfa2cSIntel #endif 222de3cfa2cSIntel } 223de3cfa2cSIntel } 224de3cfa2cSIntel 225de3cfa2cSIntel int 226*98a16481SDavid Marchand main(int argc, char **argv) 227de3cfa2cSIntel { 228de3cfa2cSIntel int ret; 229de3cfa2cSIntel 230de3cfa2cSIntel ret = app_parse_args(argc, argv); 231de3cfa2cSIntel if (ret < 0) 232de3cfa2cSIntel return -1; 233de3cfa2cSIntel 234de3cfa2cSIntel ret = app_init(); 235de3cfa2cSIntel if (ret < 0) 236de3cfa2cSIntel return -1; 237de3cfa2cSIntel 238de3cfa2cSIntel /* launch per-lcore init on every lcore */ 239de3cfa2cSIntel rte_eal_mp_remote_launch(app_main_loop, NULL, SKIP_MASTER); 240de3cfa2cSIntel 241cfd5c971SIntel if (interactive) { 242cfd5c971SIntel sleep(1); 243cfd5c971SIntel prompt(); 244cfd5c971SIntel } 245cfd5c971SIntel else { 246de3cfa2cSIntel /* print statistics every second */ 247de3cfa2cSIntel while(1) { 248de3cfa2cSIntel sleep(1); 249de3cfa2cSIntel app_stat(); 250de3cfa2cSIntel } 251de3cfa2cSIntel } 252de3cfa2cSIntel 253cfd5c971SIntel return 0; 254cfd5c971SIntel } 255de3cfa2cSIntel 256