1*3998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 2*3998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #include <unistd.h> 6de3cfa2cSIntel #include <stdint.h> 7de3cfa2cSIntel 8de3cfa2cSIntel #include <rte_log.h> 9de3cfa2cSIntel #include <rte_mbuf.h> 10de3cfa2cSIntel #include <rte_malloc.h> 11de3cfa2cSIntel #include <rte_cycles.h> 12de3cfa2cSIntel #include <rte_ethdev.h> 13de3cfa2cSIntel #include <rte_memcpy.h> 14de3cfa2cSIntel #include <rte_byteorder.h> 15de3cfa2cSIntel #include <rte_branch_prediction.h> 16de3cfa2cSIntel 17de3cfa2cSIntel #include <rte_sched.h> 18de3cfa2cSIntel 19de3cfa2cSIntel #include "main.h" 20de3cfa2cSIntel 21de3cfa2cSIntel #define APP_MODE_NONE 0 22de3cfa2cSIntel #define APP_RX_MODE 1 23de3cfa2cSIntel #define APP_WT_MODE 2 24de3cfa2cSIntel #define APP_TX_MODE 4 25de3cfa2cSIntel 26cfd5c971SIntel uint8_t interactive = APP_INTERACTIVE_DEFAULT; 27cfd5c971SIntel uint32_t qavg_period = APP_QAVG_PERIOD; 28cfd5c971SIntel uint32_t qavg_ntimes = APP_QAVG_NTIMES; 29de3cfa2cSIntel 30de3cfa2cSIntel /* main processing loop */ 31de3cfa2cSIntel static int 32de3cfa2cSIntel app_main_loop(__attribute__((unused))void *dummy) 33de3cfa2cSIntel { 34de3cfa2cSIntel uint32_t lcore_id; 35de3cfa2cSIntel uint32_t i, mode; 36de3cfa2cSIntel uint32_t rx_idx = 0; 37de3cfa2cSIntel uint32_t wt_idx = 0; 38de3cfa2cSIntel uint32_t tx_idx = 0; 39de3cfa2cSIntel struct thread_conf *rx_confs[MAX_DATA_STREAMS]; 40de3cfa2cSIntel struct thread_conf *wt_confs[MAX_DATA_STREAMS]; 41de3cfa2cSIntel struct thread_conf *tx_confs[MAX_DATA_STREAMS]; 42de3cfa2cSIntel 43de3cfa2cSIntel memset(rx_confs, 0, sizeof(rx_confs)); 44de3cfa2cSIntel memset(wt_confs, 0, sizeof(wt_confs)); 45de3cfa2cSIntel memset(tx_confs, 0, sizeof(tx_confs)); 46de3cfa2cSIntel 47de3cfa2cSIntel 48de3cfa2cSIntel mode = APP_MODE_NONE; 49de3cfa2cSIntel lcore_id = rte_lcore_id(); 50de3cfa2cSIntel 51de3cfa2cSIntel for (i = 0; i < nb_pfc; i++) { 52de3cfa2cSIntel struct flow_conf *flow = &qos_conf[i]; 53de3cfa2cSIntel 54de3cfa2cSIntel if (flow->rx_core == lcore_id) { 55de3cfa2cSIntel flow->rx_thread.rx_port = flow->rx_port; 56de3cfa2cSIntel flow->rx_thread.rx_ring = flow->rx_ring; 57de3cfa2cSIntel flow->rx_thread.rx_queue = flow->rx_queue; 58de3cfa2cSIntel 59de3cfa2cSIntel rx_confs[rx_idx++] = &flow->rx_thread; 60de3cfa2cSIntel 61de3cfa2cSIntel mode |= APP_RX_MODE; 62de3cfa2cSIntel } 63de3cfa2cSIntel if (flow->tx_core == lcore_id) { 64de3cfa2cSIntel flow->tx_thread.tx_port = flow->tx_port; 65de3cfa2cSIntel flow->tx_thread.tx_ring = flow->tx_ring; 66de3cfa2cSIntel flow->tx_thread.tx_queue = flow->tx_queue; 67de3cfa2cSIntel 68de3cfa2cSIntel tx_confs[tx_idx++] = &flow->tx_thread; 69de3cfa2cSIntel 70de3cfa2cSIntel mode |= APP_TX_MODE; 71de3cfa2cSIntel } 72de3cfa2cSIntel if (flow->wt_core == lcore_id) { 73de3cfa2cSIntel flow->wt_thread.rx_ring = flow->rx_ring; 74de3cfa2cSIntel flow->wt_thread.tx_ring = flow->tx_ring; 75de3cfa2cSIntel flow->wt_thread.tx_port = flow->tx_port; 76de3cfa2cSIntel flow->wt_thread.sched_port = flow->sched_port; 77de3cfa2cSIntel 78de3cfa2cSIntel wt_confs[wt_idx++] = &flow->wt_thread; 79de3cfa2cSIntel 80de3cfa2cSIntel mode |= APP_WT_MODE; 81de3cfa2cSIntel } 82de3cfa2cSIntel } 83de3cfa2cSIntel 84de3cfa2cSIntel if (mode == APP_MODE_NONE) { 85de3cfa2cSIntel RTE_LOG(INFO, APP, "lcore %u has nothing to do\n", lcore_id); 86de3cfa2cSIntel return -1; 87de3cfa2cSIntel } 88de3cfa2cSIntel 89de3cfa2cSIntel if (mode == (APP_RX_MODE | APP_WT_MODE)) { 90de3cfa2cSIntel RTE_LOG(INFO, APP, "lcore %u was configured for both RX and WT !!!\n", 91de3cfa2cSIntel lcore_id); 92de3cfa2cSIntel return -1; 93de3cfa2cSIntel } 94de3cfa2cSIntel 95de3cfa2cSIntel RTE_LOG(INFO, APP, "entering main loop on lcore %u\n", lcore_id); 96de3cfa2cSIntel /* initialize mbuf memory */ 97de3cfa2cSIntel if (mode == APP_RX_MODE) { 98de3cfa2cSIntel for (i = 0; i < rx_idx; i++) { 99f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "flow%u lcoreid%u reading port%u\n", 100de3cfa2cSIntel i, lcore_id, rx_confs[i]->rx_port); 101de3cfa2cSIntel } 102de3cfa2cSIntel 103de3cfa2cSIntel app_rx_thread(rx_confs); 104de3cfa2cSIntel } 105de3cfa2cSIntel else if (mode == (APP_TX_MODE | APP_WT_MODE)) { 106de3cfa2cSIntel for (i = 0; i < wt_idx; i++) { 107de3cfa2cSIntel wt_confs[i]->m_table = rte_malloc("table_wt", sizeof(struct rte_mbuf *) 108fdf20fa7SSergio Gonzalez Monroy * burst_conf.tx_burst, RTE_CACHE_LINE_SIZE); 109de3cfa2cSIntel 110de3cfa2cSIntel if (wt_confs[i]->m_table == NULL) 111de3cfa2cSIntel rte_panic("flow %u unable to allocate memory buffer\n", i); 112de3cfa2cSIntel 113f8244c63SZhiyong Yang RTE_LOG(INFO, APP, 114f8244c63SZhiyong Yang "flow %u lcoreid %u sched+write port %u\n", 115de3cfa2cSIntel i, lcore_id, wt_confs[i]->tx_port); 116de3cfa2cSIntel } 117de3cfa2cSIntel 118de3cfa2cSIntel app_mixed_thread(wt_confs); 119de3cfa2cSIntel } 120de3cfa2cSIntel else if (mode == APP_TX_MODE) { 121de3cfa2cSIntel for (i = 0; i < tx_idx; i++) { 122de3cfa2cSIntel tx_confs[i]->m_table = rte_malloc("table_tx", sizeof(struct rte_mbuf *) 123fdf20fa7SSergio Gonzalez Monroy * burst_conf.tx_burst, RTE_CACHE_LINE_SIZE); 124de3cfa2cSIntel 125de3cfa2cSIntel if (tx_confs[i]->m_table == NULL) 126de3cfa2cSIntel rte_panic("flow %u unable to allocate memory buffer\n", i); 127de3cfa2cSIntel 128f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "flow%u lcoreid%u write port%u\n", 129de3cfa2cSIntel i, lcore_id, tx_confs[i]->tx_port); 130de3cfa2cSIntel } 131de3cfa2cSIntel 132de3cfa2cSIntel app_tx_thread(tx_confs); 133de3cfa2cSIntel } 134de3cfa2cSIntel else if (mode == APP_WT_MODE){ 135de3cfa2cSIntel for (i = 0; i < wt_idx; i++) { 136de3cfa2cSIntel RTE_LOG(INFO, APP, "flow %u lcoreid %u scheduling \n", i, lcore_id); 137de3cfa2cSIntel } 138de3cfa2cSIntel 139de3cfa2cSIntel app_worker_thread(wt_confs); 140de3cfa2cSIntel } 141de3cfa2cSIntel 142de3cfa2cSIntel return 0; 143de3cfa2cSIntel } 144de3cfa2cSIntel 145cfd5c971SIntel void 146de3cfa2cSIntel app_stat(void) 147de3cfa2cSIntel { 148de3cfa2cSIntel uint32_t i; 149de3cfa2cSIntel struct rte_eth_stats stats; 150de3cfa2cSIntel static struct rte_eth_stats rx_stats[MAX_DATA_STREAMS]; 151de3cfa2cSIntel static struct rte_eth_stats tx_stats[MAX_DATA_STREAMS]; 152de3cfa2cSIntel 153de3cfa2cSIntel /* print statistics */ 154de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 155de3cfa2cSIntel struct flow_conf *flow = &qos_conf[i]; 156de3cfa2cSIntel 157de3cfa2cSIntel rte_eth_stats_get(flow->rx_port, &stats); 158f8244c63SZhiyong Yang printf("\nRX port %"PRIu16": rx: %"PRIu64 " err: %"PRIu64 159e8ed6c78SBruce Richardson " no_mbuf: %"PRIu64 "\n", 160de3cfa2cSIntel flow->rx_port, 161de3cfa2cSIntel stats.ipackets - rx_stats[i].ipackets, 162de3cfa2cSIntel stats.ierrors - rx_stats[i].ierrors, 163de3cfa2cSIntel stats.rx_nombuf - rx_stats[i].rx_nombuf); 164de3cfa2cSIntel memcpy(&rx_stats[i], &stats, sizeof(stats)); 165de3cfa2cSIntel 166de3cfa2cSIntel rte_eth_stats_get(flow->tx_port, &stats); 167f8244c63SZhiyong Yang printf("TX port %"PRIu16": tx: %" PRIu64 " err: %" PRIu64 "\n", 168de3cfa2cSIntel flow->tx_port, 169de3cfa2cSIntel stats.opackets - tx_stats[i].opackets, 170de3cfa2cSIntel stats.oerrors - tx_stats[i].oerrors); 171de3cfa2cSIntel memcpy(&tx_stats[i], &stats, sizeof(stats)); 172de3cfa2cSIntel 173de3cfa2cSIntel #if APP_COLLECT_STAT 174de3cfa2cSIntel printf("-------+------------+------------+\n"); 175de3cfa2cSIntel printf(" | received | dropped |\n"); 176de3cfa2cSIntel printf("-------+------------+------------+\n"); 177de3cfa2cSIntel printf(" RX | %10" PRIu64 " | %10" PRIu64 " |\n", 178de3cfa2cSIntel flow->rx_thread.stat.nb_rx, 179de3cfa2cSIntel flow->rx_thread.stat.nb_drop); 180de3cfa2cSIntel printf("QOS+TX | %10" PRIu64 " | %10" PRIu64 " | pps: %"PRIu64 " \n", 181de3cfa2cSIntel flow->wt_thread.stat.nb_rx, 182de3cfa2cSIntel flow->wt_thread.stat.nb_drop, 183de3cfa2cSIntel flow->wt_thread.stat.nb_rx - flow->wt_thread.stat.nb_drop); 184de3cfa2cSIntel printf("-------+------------+------------+\n"); 185de3cfa2cSIntel 186de3cfa2cSIntel memset(&flow->rx_thread.stat, 0, sizeof(struct thread_stat)); 187de3cfa2cSIntel memset(&flow->wt_thread.stat, 0, sizeof(struct thread_stat)); 188de3cfa2cSIntel #endif 189de3cfa2cSIntel } 190de3cfa2cSIntel } 191de3cfa2cSIntel 192de3cfa2cSIntel int 19398a16481SDavid Marchand main(int argc, char **argv) 194de3cfa2cSIntel { 195de3cfa2cSIntel int ret; 196de3cfa2cSIntel 197de3cfa2cSIntel ret = app_parse_args(argc, argv); 198de3cfa2cSIntel if (ret < 0) 199de3cfa2cSIntel return -1; 200de3cfa2cSIntel 201de3cfa2cSIntel ret = app_init(); 202de3cfa2cSIntel if (ret < 0) 203de3cfa2cSIntel return -1; 204de3cfa2cSIntel 205de3cfa2cSIntel /* launch per-lcore init on every lcore */ 206de3cfa2cSIntel rte_eal_mp_remote_launch(app_main_loop, NULL, SKIP_MASTER); 207de3cfa2cSIntel 208cfd5c971SIntel if (interactive) { 209cfd5c971SIntel sleep(1); 210cfd5c971SIntel prompt(); 211cfd5c971SIntel } 212cfd5c971SIntel else { 213de3cfa2cSIntel /* print statistics every second */ 214de3cfa2cSIntel while(1) { 215de3cfa2cSIntel sleep(1); 216de3cfa2cSIntel app_stat(); 217de3cfa2cSIntel } 218de3cfa2cSIntel } 219de3cfa2cSIntel 220cfd5c971SIntel return 0; 221cfd5c971SIntel } 222