13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #include <stdint.h> 6de3cfa2cSIntel #include <memory.h> 7de3cfa2cSIntel 8de3cfa2cSIntel #include <rte_log.h> 9de3cfa2cSIntel #include <rte_mbuf.h> 10de3cfa2cSIntel #include <rte_debug.h> 11de3cfa2cSIntel #include <rte_ethdev.h> 12de3cfa2cSIntel #include <rte_mempool.h> 13de3cfa2cSIntel #include <rte_sched.h> 14de3cfa2cSIntel #include <rte_cycles.h> 15de3cfa2cSIntel #include <rte_string_fns.h> 16db935d01SMichal Jastrzebski #include <rte_cfgfile.h> 17de3cfa2cSIntel 18de3cfa2cSIntel #include "main.h" 19de3cfa2cSIntel #include "cfg_file.h" 20de3cfa2cSIntel 21de3cfa2cSIntel uint32_t app_numa_mask = 0; 22de3cfa2cSIntel static uint32_t app_inited_port_mask = 0; 23de3cfa2cSIntel 24de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 25de3cfa2cSIntel 26de3cfa2cSIntel #define MAX_NAME_LEN 32 27de3cfa2cSIntel 28de3cfa2cSIntel struct ring_conf ring_conf = { 29de3cfa2cSIntel .rx_size = APP_RX_DESC_DEFAULT, 30de3cfa2cSIntel .ring_size = APP_RING_SIZE, 31de3cfa2cSIntel .tx_size = APP_TX_DESC_DEFAULT, 32de3cfa2cSIntel }; 33de3cfa2cSIntel 34de3cfa2cSIntel struct burst_conf burst_conf = { 35de3cfa2cSIntel .rx_burst = MAX_PKT_RX_BURST, 36de3cfa2cSIntel .ring_burst = PKT_ENQUEUE, 37de3cfa2cSIntel .qos_dequeue = PKT_DEQUEUE, 38de3cfa2cSIntel .tx_burst = MAX_PKT_TX_BURST, 39de3cfa2cSIntel }; 40de3cfa2cSIntel 41de3cfa2cSIntel struct ring_thresh rx_thresh = { 42de3cfa2cSIntel .pthresh = RX_PTHRESH, 43de3cfa2cSIntel .hthresh = RX_HTHRESH, 44de3cfa2cSIntel .wthresh = RX_WTHRESH, 45de3cfa2cSIntel }; 46de3cfa2cSIntel 47de3cfa2cSIntel struct ring_thresh tx_thresh = { 48de3cfa2cSIntel .pthresh = TX_PTHRESH, 49de3cfa2cSIntel .hthresh = TX_HTHRESH, 50de3cfa2cSIntel .wthresh = TX_WTHRESH, 51de3cfa2cSIntel }; 52de3cfa2cSIntel 53de3cfa2cSIntel uint32_t nb_pfc; 54de3cfa2cSIntel const char *cfg_profile = NULL; 55e93b24a3SIntel int mp_size = NB_MBUF; 56de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS]; 57de3cfa2cSIntel 58e2ef4628SShahaf Shuler static struct rte_eth_conf port_conf = { 59de3cfa2cSIntel .rxmode = { 6035b2d13fSOlivier Matz .max_rx_pkt_len = RTE_ETHER_MAX_LEN, 61de3cfa2cSIntel .split_hdr_size = 0, 62de3cfa2cSIntel }, 63de3cfa2cSIntel .txmode = { 64de3cfa2cSIntel .mq_mode = ETH_DCB_NONE, 65de3cfa2cSIntel }, 66de3cfa2cSIntel }; 67de3cfa2cSIntel 68de3cfa2cSIntel static int 69f8244c63SZhiyong Yang app_init_port(uint16_t portid, struct rte_mempool *mp) 70de3cfa2cSIntel { 71de3cfa2cSIntel int ret; 72de3cfa2cSIntel struct rte_eth_link link; 73e2ef4628SShahaf Shuler struct rte_eth_dev_info dev_info; 74de3cfa2cSIntel struct rte_eth_rxconf rx_conf; 75de3cfa2cSIntel struct rte_eth_txconf tx_conf; 7660efb44fSRoman Zhukov uint16_t rx_size; 7760efb44fSRoman Zhukov uint16_t tx_size; 78e2ef4628SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf; 79de3cfa2cSIntel 80de3cfa2cSIntel /* check if port already initialized (multistream configuration) */ 81de3cfa2cSIntel if (app_inited_port_mask & (1u << portid)) 82de3cfa2cSIntel return 0; 83de3cfa2cSIntel 84de3cfa2cSIntel rx_conf.rx_thresh.pthresh = rx_thresh.pthresh; 85de3cfa2cSIntel rx_conf.rx_thresh.hthresh = rx_thresh.hthresh; 86de3cfa2cSIntel rx_conf.rx_thresh.wthresh = rx_thresh.wthresh; 87de3cfa2cSIntel rx_conf.rx_free_thresh = 32; 88de3cfa2cSIntel rx_conf.rx_drop_en = 0; 8996b5077cSJasvinder Singh rx_conf.rx_deferred_start = 0; 90de3cfa2cSIntel 91de3cfa2cSIntel tx_conf.tx_thresh.pthresh = tx_thresh.pthresh; 92de3cfa2cSIntel tx_conf.tx_thresh.hthresh = tx_thresh.hthresh; 93de3cfa2cSIntel tx_conf.tx_thresh.wthresh = tx_thresh.wthresh; 94de3cfa2cSIntel tx_conf.tx_free_thresh = 0; 95de3cfa2cSIntel tx_conf.tx_rs_thresh = 0; 9696b5077cSJasvinder Singh tx_conf.tx_deferred_start = 0; 97de3cfa2cSIntel 98de3cfa2cSIntel /* init port */ 99f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "Initializing port %"PRIu16"... ", portid); 100de3cfa2cSIntel fflush(stdout); 10145069992SIvan Ilchenko 10245069992SIvan Ilchenko ret = rte_eth_dev_info_get(portid, &dev_info); 10345069992SIvan Ilchenko if (ret != 0) 10445069992SIvan Ilchenko rte_exit(EXIT_FAILURE, 10545069992SIvan Ilchenko "Error during getting device (port %u) info: %s\n", 10645069992SIvan Ilchenko portid, strerror(-ret)); 10745069992SIvan Ilchenko 108e2ef4628SShahaf Shuler if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 109e2ef4628SShahaf Shuler local_port_conf.txmode.offloads |= 110e2ef4628SShahaf Shuler DEV_TX_OFFLOAD_MBUF_FAST_FREE; 111e2ef4628SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf); 112de3cfa2cSIntel if (ret < 0) 113f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 114f8244c63SZhiyong Yang "Cannot configure device: err=%d, port=%u\n", 115f8244c63SZhiyong Yang ret, portid); 116de3cfa2cSIntel 11760efb44fSRoman Zhukov rx_size = ring_conf.rx_size; 11860efb44fSRoman Zhukov tx_size = ring_conf.tx_size; 11960efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &rx_size, &tx_size); 12060efb44fSRoman Zhukov if (ret < 0) 121f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 122f8244c63SZhiyong Yang "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n", 123f8244c63SZhiyong Yang ret, portid); 12460efb44fSRoman Zhukov ring_conf.rx_size = rx_size; 12560efb44fSRoman Zhukov ring_conf.tx_size = tx_size; 12660efb44fSRoman Zhukov 127de3cfa2cSIntel /* init one RX queue */ 128de3cfa2cSIntel fflush(stdout); 129e2ef4628SShahaf Shuler rx_conf.offloads = local_port_conf.rxmode.offloads; 130de3cfa2cSIntel ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size, 131de3cfa2cSIntel rte_eth_dev_socket_id(portid), &rx_conf, mp); 132de3cfa2cSIntel if (ret < 0) 133f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 134f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u\n", 135f8244c63SZhiyong Yang ret, portid); 136de3cfa2cSIntel 137de3cfa2cSIntel /* init one TX queue */ 138de3cfa2cSIntel fflush(stdout); 139e2ef4628SShahaf Shuler tx_conf.offloads = local_port_conf.txmode.offloads; 140de3cfa2cSIntel ret = rte_eth_tx_queue_setup(portid, 0, 141de3cfa2cSIntel (uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf); 142de3cfa2cSIntel if (ret < 0) 143f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 144f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n", 145f8244c63SZhiyong Yang ret, portid, 0); 146de3cfa2cSIntel 147de3cfa2cSIntel /* Start device */ 148de3cfa2cSIntel ret = rte_eth_dev_start(portid); 149de3cfa2cSIntel if (ret < 0) 150f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 151f8244c63SZhiyong Yang "rte_pmd_port_start: err=%d, port=%u\n", 152f8244c63SZhiyong Yang ret, portid); 153de3cfa2cSIntel 154de3cfa2cSIntel printf("done: "); 155de3cfa2cSIntel 156de3cfa2cSIntel /* get link status */ 157de3cfa2cSIntel rte_eth_link_get(portid, &link); 158de3cfa2cSIntel if (link.link_status) { 159de3cfa2cSIntel printf(" Link Up - speed %u Mbps - %s\n", 160de3cfa2cSIntel (uint32_t) link.link_speed, 161de3cfa2cSIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 162de3cfa2cSIntel ("full-duplex") : ("half-duplex\n")); 163de3cfa2cSIntel } else { 164de3cfa2cSIntel printf(" Link Down\n"); 165de3cfa2cSIntel } 166*f430bbceSIvan Ilchenko ret = rte_eth_promiscuous_enable(portid); 167*f430bbceSIvan Ilchenko if (ret != 0) 168*f430bbceSIvan Ilchenko rte_exit(EXIT_FAILURE, 169*f430bbceSIvan Ilchenko "rte_eth_promiscuous_enable: err=%s, port=%u\n", 170*f430bbceSIvan Ilchenko rte_strerror(-ret), portid); 171de3cfa2cSIntel 172de3cfa2cSIntel /* mark port as initialized */ 173de3cfa2cSIntel app_inited_port_mask |= 1u << portid; 174de3cfa2cSIntel 175de3cfa2cSIntel return 0; 176de3cfa2cSIntel } 177de3cfa2cSIntel 178de3cfa2cSIntel static struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { 179de3cfa2cSIntel { 180de3cfa2cSIntel .tb_rate = 1250000000, 181de3cfa2cSIntel .tb_size = 1000000, 182de3cfa2cSIntel 183be1e5332SJasvinder Singh .tc_rate = {1250000000, 1250000000, 1250000000, 1250000000, 184be1e5332SJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000, 1250000000, 185be1e5332SJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000}, 186de3cfa2cSIntel .tc_period = 10, 187de3cfa2cSIntel }, 188de3cfa2cSIntel }; 189de3cfa2cSIntel 190be1e5332SJasvinder Singh static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = { 191de3cfa2cSIntel { /* Profile #0 */ 192de3cfa2cSIntel .tb_rate = 305175, 193de3cfa2cSIntel .tb_size = 1000000, 194de3cfa2cSIntel 195be1e5332SJasvinder Singh .tc_rate = {305175, 305175, 305175, 305175, 305175, 305175, 196be1e5332SJasvinder Singh 305175, 305175, 305175, 305175, 305175, 305175, 305175}, 197de3cfa2cSIntel .tc_period = 40, 198de3cfa2cSIntel #ifdef RTE_SCHED_SUBPORT_TC_OV 199835c5409SIntel .tc_ov_weight = 1, 200de3cfa2cSIntel #endif 201de3cfa2cSIntel 202e16b06daSJasvinder Singh .wrr_weights = {1, 1, 1, 1}, 203de3cfa2cSIntel }, 204de3cfa2cSIntel }; 205de3cfa2cSIntel 206de3cfa2cSIntel struct rte_sched_port_params port_params = { 207624148d2SIntel .name = "port_scheduler_0", 208de3cfa2cSIntel .socket = 0, /* computed */ 209de3cfa2cSIntel .rate = 0, /* computed */ 210a91c3cadSIntel .mtu = 6 + 6 + 4 + 4 + 2 + 1500, 211de3cfa2cSIntel .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT, 212de3cfa2cSIntel .n_subports_per_port = 1, 213de3cfa2cSIntel .n_pipes_per_subport = 4096, 214be1e5332SJasvinder Singh .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, 215de3cfa2cSIntel .pipe_profiles = pipe_profiles, 216624148d2SIntel .n_pipe_profiles = sizeof(pipe_profiles) / sizeof(struct rte_sched_pipe_params), 217be1e5332SJasvinder Singh .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, 218de3cfa2cSIntel 219de3cfa2cSIntel #ifdef RTE_SCHED_RED 220de3cfa2cSIntel .red_params = { 221de3cfa2cSIntel /* Traffic Class 0 Colors Green / Yellow / Red */ 222de3cfa2cSIntel [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 223de3cfa2cSIntel [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 224de3cfa2cSIntel [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 225de3cfa2cSIntel 226de3cfa2cSIntel /* Traffic Class 1 - Colors Green / Yellow / Red */ 227de3cfa2cSIntel [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 228de3cfa2cSIntel [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 229de3cfa2cSIntel [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 230de3cfa2cSIntel 231de3cfa2cSIntel /* Traffic Class 2 - Colors Green / Yellow / Red */ 232de3cfa2cSIntel [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 233de3cfa2cSIntel [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 234de3cfa2cSIntel [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 235de3cfa2cSIntel 236de3cfa2cSIntel /* Traffic Class 3 - Colors Green / Yellow / Red */ 237de3cfa2cSIntel [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 238de3cfa2cSIntel [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 239be1e5332SJasvinder Singh [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 240be1e5332SJasvinder Singh 241be1e5332SJasvinder Singh /* Traffic Class 4 - Colors Green / Yellow / Red */ 242be1e5332SJasvinder Singh [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 243be1e5332SJasvinder Singh [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 244be1e5332SJasvinder Singh [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 245be1e5332SJasvinder Singh 246be1e5332SJasvinder Singh /* Traffic Class 5 - Colors Green / Yellow / Red */ 247be1e5332SJasvinder Singh [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 248be1e5332SJasvinder Singh [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 249be1e5332SJasvinder Singh [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 250be1e5332SJasvinder Singh 251be1e5332SJasvinder Singh /* Traffic Class 6 - Colors Green / Yellow / Red */ 252be1e5332SJasvinder Singh [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 253be1e5332SJasvinder Singh [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 254be1e5332SJasvinder Singh [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 255be1e5332SJasvinder Singh 256be1e5332SJasvinder Singh /* Traffic Class 7 - Colors Green / Yellow / Red */ 257be1e5332SJasvinder Singh [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 258be1e5332SJasvinder Singh [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 259be1e5332SJasvinder Singh [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 260be1e5332SJasvinder Singh 261be1e5332SJasvinder Singh /* Traffic Class 8 - Colors Green / Yellow / Red */ 262be1e5332SJasvinder Singh [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 263be1e5332SJasvinder Singh [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 264be1e5332SJasvinder Singh [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 265be1e5332SJasvinder Singh 266be1e5332SJasvinder Singh /* Traffic Class 9 - Colors Green / Yellow / Red */ 267be1e5332SJasvinder Singh [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 268be1e5332SJasvinder Singh [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 269be1e5332SJasvinder Singh [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 270be1e5332SJasvinder Singh 271be1e5332SJasvinder Singh /* Traffic Class 10 - Colors Green / Yellow / Red */ 272be1e5332SJasvinder Singh [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 273be1e5332SJasvinder Singh [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 274be1e5332SJasvinder Singh [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 275be1e5332SJasvinder Singh 276be1e5332SJasvinder Singh /* Traffic Class 11 - Colors Green / Yellow / Red */ 277be1e5332SJasvinder Singh [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 278be1e5332SJasvinder Singh [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 279be1e5332SJasvinder Singh [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 280be1e5332SJasvinder Singh 281be1e5332SJasvinder Singh /* Traffic Class 12 - Colors Green / Yellow / Red */ 282be1e5332SJasvinder Singh [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 283be1e5332SJasvinder Singh [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 284be1e5332SJasvinder Singh [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 285be1e5332SJasvinder Singh }, 286de3cfa2cSIntel #endif /* RTE_SCHED_RED */ 287de3cfa2cSIntel }; 288de3cfa2cSIntel 289de3cfa2cSIntel static struct rte_sched_port * 290de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid) 291de3cfa2cSIntel { 292de3cfa2cSIntel static char port_name[32]; /* static as referenced from global port_params*/ 293de3cfa2cSIntel struct rte_eth_link link; 294de3cfa2cSIntel struct rte_sched_port *port = NULL; 295de3cfa2cSIntel uint32_t pipe, subport; 296de3cfa2cSIntel int err; 297de3cfa2cSIntel 298f8244c63SZhiyong Yang rte_eth_link_get(portid, &link); 299de3cfa2cSIntel 300de3cfa2cSIntel port_params.socket = socketid; 301de3cfa2cSIntel port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8; 3026f41fe75SStephen Hemminger snprintf(port_name, sizeof(port_name), "port_%d", portid); 303de3cfa2cSIntel port_params.name = port_name; 304de3cfa2cSIntel 305de3cfa2cSIntel port = rte_sched_port_config(&port_params); 306de3cfa2cSIntel if (port == NULL){ 307de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched port\n"); 308de3cfa2cSIntel } 309de3cfa2cSIntel 310de3cfa2cSIntel for (subport = 0; subport < port_params.n_subports_per_port; subport ++) { 311de3cfa2cSIntel err = rte_sched_subport_config(port, subport, &subport_params[subport]); 312de3cfa2cSIntel if (err) { 313de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched subport %u, err=%d\n", 314de3cfa2cSIntel subport, err); 315de3cfa2cSIntel } 316de3cfa2cSIntel 317de3cfa2cSIntel for (pipe = 0; pipe < port_params.n_pipes_per_subport; pipe++) { 318de3cfa2cSIntel if (app_pipe_to_profile[subport][pipe] != -1) { 319de3cfa2cSIntel err = rte_sched_pipe_config(port, subport, pipe, 320de3cfa2cSIntel app_pipe_to_profile[subport][pipe]); 321de3cfa2cSIntel if (err) { 322de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u " 323de3cfa2cSIntel "for profile %d, err=%d\n", pipe, 324de3cfa2cSIntel app_pipe_to_profile[subport][pipe], err); 325de3cfa2cSIntel } 326de3cfa2cSIntel } 327de3cfa2cSIntel } 328de3cfa2cSIntel } 329de3cfa2cSIntel 330de3cfa2cSIntel return port; 331de3cfa2cSIntel } 332de3cfa2cSIntel 333de3cfa2cSIntel static int 334de3cfa2cSIntel app_load_cfg_profile(const char *profile) 335de3cfa2cSIntel { 336de3cfa2cSIntel if (profile == NULL) 337de3cfa2cSIntel return 0; 338db935d01SMichal Jastrzebski struct rte_cfgfile *file = rte_cfgfile_load(profile, 0); 339db935d01SMichal Jastrzebski if (file == NULL) 340de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile); 341de3cfa2cSIntel 342db935d01SMichal Jastrzebski cfg_load_port(file, &port_params); 343db935d01SMichal Jastrzebski cfg_load_subport(file, subport_params); 344db935d01SMichal Jastrzebski cfg_load_pipe(file, pipe_profiles); 345de3cfa2cSIntel 346db935d01SMichal Jastrzebski rte_cfgfile_close(file); 347de3cfa2cSIntel 348de3cfa2cSIntel return 0; 349de3cfa2cSIntel } 350de3cfa2cSIntel 351de3cfa2cSIntel int app_init(void) 352de3cfa2cSIntel { 353de3cfa2cSIntel uint32_t i; 354de3cfa2cSIntel char ring_name[MAX_NAME_LEN]; 355de3cfa2cSIntel char pool_name[MAX_NAME_LEN]; 356de3cfa2cSIntel 357d9a42a69SThomas Monjalon if (rte_eth_dev_count_avail() == 0) 358de3cfa2cSIntel rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n"); 359de3cfa2cSIntel 360de3cfa2cSIntel /* load configuration profile */ 361de3cfa2cSIntel if (app_load_cfg_profile(cfg_profile) != 0) 362de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Invalid configuration profile\n"); 363de3cfa2cSIntel 364de3cfa2cSIntel /* Initialize each active flow */ 365de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 366de3cfa2cSIntel uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); 367de3cfa2cSIntel struct rte_ring *ring; 368de3cfa2cSIntel 3696f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); 370de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 371de3cfa2cSIntel if (ring == NULL) 372de3cfa2cSIntel qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 373de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 374de3cfa2cSIntel else 375de3cfa2cSIntel qos_conf[i].rx_ring = ring; 376de3cfa2cSIntel 3776f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core); 378de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 379de3cfa2cSIntel if (ring == NULL) 380de3cfa2cSIntel qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 381de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 382de3cfa2cSIntel else 383de3cfa2cSIntel qos_conf[i].tx_ring = ring; 384de3cfa2cSIntel 385de3cfa2cSIntel 386de3cfa2cSIntel /* create the mbuf pools for each RX Port */ 3876f41fe75SStephen Hemminger snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i); 388ea0c20eaSOlivier Matz qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name, 389824cb29cSKonstantin Ananyev mp_size, burst_conf.rx_burst * 4, 0, 390824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, 391ea0c20eaSOlivier Matz rte_eth_dev_socket_id(qos_conf[i].rx_port)); 392de3cfa2cSIntel if (qos_conf[i].mbuf_pool == NULL) 393de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i); 394de3cfa2cSIntel 395de3cfa2cSIntel app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); 396de3cfa2cSIntel app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); 397de3cfa2cSIntel 398cfd5c971SIntel qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket); 399de3cfa2cSIntel } 400de3cfa2cSIntel 401de3cfa2cSIntel RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n", 402de3cfa2cSIntel rte_get_timer_hz()); 403de3cfa2cSIntel 404de3cfa2cSIntel RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," 405e93b24a3SIntel "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size, 406de3cfa2cSIntel ring_conf.tx_size); 407de3cfa2cSIntel 408de3cfa2cSIntel RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n" 409de3cfa2cSIntel " Worker read/QoS enqueue = %hu,\n" 410de3cfa2cSIntel " QoS dequeue = %hu, Worker write = %hu\n", 411de3cfa2cSIntel burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst, 412de3cfa2cSIntel burst_conf.qos_dequeue, burst_conf.tx_burst); 413de3cfa2cSIntel 414de3cfa2cSIntel RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," 415de3cfa2cSIntel "TX (p = %hhu, h = %hhu, w = %hhu)\n", 416de3cfa2cSIntel rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh, 417de3cfa2cSIntel tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh); 418de3cfa2cSIntel 419de3cfa2cSIntel return 0; 420de3cfa2cSIntel } 421