xref: /dpdk/examples/qos_sched/init.c (revision ea0c20ea95fd5d71a10757e6598ac66233ea1495)
1de3cfa2cSIntel /*-
2de3cfa2cSIntel  *   BSD LICENSE
3de3cfa2cSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5de3cfa2cSIntel  *   All rights reserved.
6de3cfa2cSIntel  *
7de3cfa2cSIntel  *   Redistribution and use in source and binary forms, with or without
8de3cfa2cSIntel  *   modification, are permitted provided that the following conditions
9de3cfa2cSIntel  *   are met:
10de3cfa2cSIntel  *
11de3cfa2cSIntel  *     * Redistributions of source code must retain the above copyright
12de3cfa2cSIntel  *       notice, this list of conditions and the following disclaimer.
13de3cfa2cSIntel  *     * Redistributions in binary form must reproduce the above copyright
14de3cfa2cSIntel  *       notice, this list of conditions and the following disclaimer in
15de3cfa2cSIntel  *       the documentation and/or other materials provided with the
16de3cfa2cSIntel  *       distribution.
17de3cfa2cSIntel  *     * Neither the name of Intel Corporation nor the names of its
18de3cfa2cSIntel  *       contributors may be used to endorse or promote products derived
19de3cfa2cSIntel  *       from this software without specific prior written permission.
20de3cfa2cSIntel  *
21de3cfa2cSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22de3cfa2cSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23de3cfa2cSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24de3cfa2cSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25de3cfa2cSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26de3cfa2cSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27de3cfa2cSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28de3cfa2cSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29de3cfa2cSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30de3cfa2cSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31de3cfa2cSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32de3cfa2cSIntel  */
33de3cfa2cSIntel 
34de3cfa2cSIntel #include <stdint.h>
35de3cfa2cSIntel #include <memory.h>
36de3cfa2cSIntel 
37de3cfa2cSIntel #include <rte_log.h>
38de3cfa2cSIntel #include <rte_mbuf.h>
39de3cfa2cSIntel #include <rte_debug.h>
40de3cfa2cSIntel #include <rte_ethdev.h>
41de3cfa2cSIntel #include <rte_mempool.h>
42de3cfa2cSIntel #include <rte_sched.h>
43de3cfa2cSIntel #include <rte_cycles.h>
44de3cfa2cSIntel #include <rte_string_fns.h>
45de3cfa2cSIntel 
46de3cfa2cSIntel #include "main.h"
47de3cfa2cSIntel #include "cfg_file.h"
48de3cfa2cSIntel 
49de3cfa2cSIntel uint32_t app_numa_mask = 0;
50de3cfa2cSIntel static uint32_t app_inited_port_mask = 0;
51de3cfa2cSIntel 
52de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES];
53de3cfa2cSIntel 
54de3cfa2cSIntel #define MAX_NAME_LEN 32
55de3cfa2cSIntel 
56de3cfa2cSIntel struct ring_conf ring_conf = {
57de3cfa2cSIntel 	.rx_size   = APP_RX_DESC_DEFAULT,
58de3cfa2cSIntel 	.ring_size = APP_RING_SIZE,
59de3cfa2cSIntel 	.tx_size   = APP_TX_DESC_DEFAULT,
60de3cfa2cSIntel };
61de3cfa2cSIntel 
62de3cfa2cSIntel struct burst_conf burst_conf = {
63de3cfa2cSIntel 	.rx_burst    = MAX_PKT_RX_BURST,
64de3cfa2cSIntel 	.ring_burst  = PKT_ENQUEUE,
65de3cfa2cSIntel 	.qos_dequeue = PKT_DEQUEUE,
66de3cfa2cSIntel 	.tx_burst    = MAX_PKT_TX_BURST,
67de3cfa2cSIntel };
68de3cfa2cSIntel 
69de3cfa2cSIntel struct ring_thresh rx_thresh = {
70de3cfa2cSIntel 	.pthresh = RX_PTHRESH,
71de3cfa2cSIntel 	.hthresh = RX_HTHRESH,
72de3cfa2cSIntel 	.wthresh = RX_WTHRESH,
73de3cfa2cSIntel };
74de3cfa2cSIntel 
75de3cfa2cSIntel struct ring_thresh tx_thresh = {
76de3cfa2cSIntel 	.pthresh = TX_PTHRESH,
77de3cfa2cSIntel 	.hthresh = TX_HTHRESH,
78de3cfa2cSIntel 	.wthresh = TX_WTHRESH,
79de3cfa2cSIntel };
80de3cfa2cSIntel 
81de3cfa2cSIntel uint32_t nb_pfc;
82de3cfa2cSIntel const char *cfg_profile = NULL;
83e93b24a3SIntel int mp_size = NB_MBUF;
84de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS];
85de3cfa2cSIntel 
86de3cfa2cSIntel static const struct rte_eth_conf port_conf = {
87de3cfa2cSIntel 	.rxmode = {
88de3cfa2cSIntel 		.max_rx_pkt_len = ETHER_MAX_LEN,
89de3cfa2cSIntel 		.split_hdr_size = 0,
90de3cfa2cSIntel 		.header_split   = 0, /**< Header Split disabled */
91de3cfa2cSIntel 		.hw_ip_checksum = 0, /**< IP checksum offload disabled */
92de3cfa2cSIntel 		.hw_vlan_filter = 0, /**< VLAN filtering disabled */
93de3cfa2cSIntel 		.jumbo_frame    = 0, /**< Jumbo Frame Support disabled */
94de3cfa2cSIntel 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
95de3cfa2cSIntel 	},
96de3cfa2cSIntel 	.txmode = {
97de3cfa2cSIntel 		.mq_mode = ETH_DCB_NONE,
98de3cfa2cSIntel 	},
99de3cfa2cSIntel };
100de3cfa2cSIntel 
101de3cfa2cSIntel static int
102de3cfa2cSIntel app_init_port(uint8_t portid, struct rte_mempool *mp)
103de3cfa2cSIntel {
104de3cfa2cSIntel 	int ret;
105de3cfa2cSIntel 	struct rte_eth_link link;
106de3cfa2cSIntel 	struct rte_eth_rxconf rx_conf;
107de3cfa2cSIntel 	struct rte_eth_txconf tx_conf;
108de3cfa2cSIntel 
109de3cfa2cSIntel 	/* check if port already initialized (multistream configuration) */
110de3cfa2cSIntel 	if (app_inited_port_mask & (1u << portid))
111de3cfa2cSIntel 		return 0;
112de3cfa2cSIntel 
113de3cfa2cSIntel 	rx_conf.rx_thresh.pthresh = rx_thresh.pthresh;
114de3cfa2cSIntel 	rx_conf.rx_thresh.hthresh = rx_thresh.hthresh;
115de3cfa2cSIntel 	rx_conf.rx_thresh.wthresh = rx_thresh.wthresh;
116de3cfa2cSIntel 	rx_conf.rx_free_thresh = 32;
117de3cfa2cSIntel 	rx_conf.rx_drop_en = 0;
118de3cfa2cSIntel 
119de3cfa2cSIntel 	tx_conf.tx_thresh.pthresh = tx_thresh.pthresh;
120de3cfa2cSIntel 	tx_conf.tx_thresh.hthresh = tx_thresh.hthresh;
121de3cfa2cSIntel 	tx_conf.tx_thresh.wthresh = tx_thresh.wthresh;
122de3cfa2cSIntel 	tx_conf.tx_free_thresh = 0;
123de3cfa2cSIntel 	tx_conf.tx_rs_thresh = 0;
124de3cfa2cSIntel 	tx_conf.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS;
125de3cfa2cSIntel 
126de3cfa2cSIntel 	/* init port */
127e8ed6c78SBruce Richardson 	RTE_LOG(INFO, APP, "Initializing port %"PRIu8"... ", portid);
128de3cfa2cSIntel 	fflush(stdout);
129de3cfa2cSIntel 	ret = rte_eth_dev_configure(portid, 1, 1, &port_conf);
130de3cfa2cSIntel 	if (ret < 0)
131e8ed6c78SBruce Richardson 		rte_exit(EXIT_FAILURE, "Cannot configure device: "
132e8ed6c78SBruce Richardson 				"err=%d, port=%"PRIu8"\n", ret, portid);
133de3cfa2cSIntel 
134de3cfa2cSIntel 	/* init one RX queue */
135de3cfa2cSIntel 	fflush(stdout);
136de3cfa2cSIntel 	ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size,
137de3cfa2cSIntel 		rte_eth_dev_socket_id(portid), &rx_conf, mp);
138de3cfa2cSIntel 	if (ret < 0)
139e8ed6c78SBruce Richardson 		rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: "
140e8ed6c78SBruce Richardson 				"err=%d, port=%"PRIu8"\n", ret, portid);
141de3cfa2cSIntel 
142de3cfa2cSIntel 	/* init one TX queue */
143de3cfa2cSIntel 	fflush(stdout);
144de3cfa2cSIntel 	ret = rte_eth_tx_queue_setup(portid, 0,
145de3cfa2cSIntel 		(uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf);
146de3cfa2cSIntel 	if (ret < 0)
147de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, "
148e8ed6c78SBruce Richardson 				"port=%"PRIu8" queue=%d\n", ret, portid, 0);
149de3cfa2cSIntel 
150de3cfa2cSIntel 	/* Start device */
151de3cfa2cSIntel 	ret = rte_eth_dev_start(portid);
152de3cfa2cSIntel 	if (ret < 0)
153e8ed6c78SBruce Richardson 		rte_exit(EXIT_FAILURE, "rte_pmd_port_start: "
154e8ed6c78SBruce Richardson 				"err=%d, port=%"PRIu8"\n", ret, portid);
155de3cfa2cSIntel 
156de3cfa2cSIntel 	printf("done: ");
157de3cfa2cSIntel 
158de3cfa2cSIntel 	/* get link status */
159de3cfa2cSIntel 	rte_eth_link_get(portid, &link);
160de3cfa2cSIntel 	if (link.link_status) {
161de3cfa2cSIntel 		printf(" Link Up - speed %u Mbps - %s\n",
162de3cfa2cSIntel 			(uint32_t) link.link_speed,
163de3cfa2cSIntel 			(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
164de3cfa2cSIntel 			("full-duplex") : ("half-duplex\n"));
165de3cfa2cSIntel 	} else {
166de3cfa2cSIntel 		printf(" Link Down\n");
167de3cfa2cSIntel 	}
168de3cfa2cSIntel 	rte_eth_promiscuous_enable(portid);
169de3cfa2cSIntel 
170de3cfa2cSIntel 	/* mark port as initialized */
171de3cfa2cSIntel 	app_inited_port_mask |= 1u << portid;
172de3cfa2cSIntel 
173de3cfa2cSIntel 	return 0;
174de3cfa2cSIntel }
175de3cfa2cSIntel 
176de3cfa2cSIntel static struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
177de3cfa2cSIntel 	{
178de3cfa2cSIntel 		.tb_rate = 1250000000,
179de3cfa2cSIntel 		.tb_size = 1000000,
180de3cfa2cSIntel 
181de3cfa2cSIntel 		.tc_rate = {1250000000, 1250000000, 1250000000, 1250000000},
182de3cfa2cSIntel 		.tc_period = 10,
183de3cfa2cSIntel 	},
184de3cfa2cSIntel };
185de3cfa2cSIntel 
186de3cfa2cSIntel static struct rte_sched_pipe_params pipe_profiles[RTE_SCHED_PIPE_PROFILES_PER_PORT] = {
187de3cfa2cSIntel 	{ /* Profile #0 */
188de3cfa2cSIntel 		.tb_rate = 305175,
189de3cfa2cSIntel 		.tb_size = 1000000,
190de3cfa2cSIntel 
191de3cfa2cSIntel 		.tc_rate = {305175, 305175, 305175, 305175},
192de3cfa2cSIntel 		.tc_period = 40,
193de3cfa2cSIntel #ifdef RTE_SCHED_SUBPORT_TC_OV
194835c5409SIntel 		.tc_ov_weight = 1,
195de3cfa2cSIntel #endif
196de3cfa2cSIntel 
197de3cfa2cSIntel 		.wrr_weights = {1, 1, 1, 1,  1, 1, 1, 1,  1, 1, 1, 1,  1, 1, 1, 1},
198de3cfa2cSIntel 	},
199de3cfa2cSIntel };
200de3cfa2cSIntel 
201de3cfa2cSIntel struct rte_sched_port_params port_params = {
202624148d2SIntel 	.name = "port_scheduler_0",
203de3cfa2cSIntel 	.socket = 0, /* computed */
204de3cfa2cSIntel 	.rate = 0, /* computed */
205a91c3cadSIntel 	.mtu = 6 + 6 + 4 + 4 + 2 + 1500,
206de3cfa2cSIntel 	.frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT,
207de3cfa2cSIntel 	.n_subports_per_port = 1,
208de3cfa2cSIntel 	.n_pipes_per_subport = 4096,
209de3cfa2cSIntel 	.qsize = {64, 64, 64, 64},
210de3cfa2cSIntel 	.pipe_profiles = pipe_profiles,
211624148d2SIntel 	.n_pipe_profiles = sizeof(pipe_profiles) / sizeof(struct rte_sched_pipe_params),
212de3cfa2cSIntel 
213de3cfa2cSIntel #ifdef RTE_SCHED_RED
214de3cfa2cSIntel 	.red_params = {
215de3cfa2cSIntel 		/* Traffic Class 0 Colors Green / Yellow / Red */
216de3cfa2cSIntel 		[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
217de3cfa2cSIntel 		[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
218de3cfa2cSIntel 		[0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
219de3cfa2cSIntel 
220de3cfa2cSIntel 		/* Traffic Class 1 - Colors Green / Yellow / Red */
221de3cfa2cSIntel 		[1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
222de3cfa2cSIntel 		[1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
223de3cfa2cSIntel 		[1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
224de3cfa2cSIntel 
225de3cfa2cSIntel 		/* Traffic Class 2 - Colors Green / Yellow / Red */
226de3cfa2cSIntel 		[2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
227de3cfa2cSIntel 		[2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
228de3cfa2cSIntel 		[2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
229de3cfa2cSIntel 
230de3cfa2cSIntel 		/* Traffic Class 3 - Colors Green / Yellow / Red */
231de3cfa2cSIntel 		[3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
232de3cfa2cSIntel 		[3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
233de3cfa2cSIntel 		[3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}
234de3cfa2cSIntel 	}
235de3cfa2cSIntel #endif /* RTE_SCHED_RED */
236de3cfa2cSIntel };
237de3cfa2cSIntel 
238de3cfa2cSIntel static struct rte_sched_port *
239de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid)
240de3cfa2cSIntel {
241de3cfa2cSIntel 	static char port_name[32]; /* static as referenced from global port_params*/
242de3cfa2cSIntel 	struct rte_eth_link link;
243de3cfa2cSIntel 	struct rte_sched_port *port = NULL;
244de3cfa2cSIntel 	uint32_t pipe, subport;
245de3cfa2cSIntel 	int err;
246de3cfa2cSIntel 
247de3cfa2cSIntel 	rte_eth_link_get((uint8_t)portid, &link);
248de3cfa2cSIntel 
249de3cfa2cSIntel 	port_params.socket = socketid;
250de3cfa2cSIntel 	port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8;
2516f41fe75SStephen Hemminger 	snprintf(port_name, sizeof(port_name), "port_%d", portid);
252de3cfa2cSIntel 	port_params.name = port_name;
253de3cfa2cSIntel 
254de3cfa2cSIntel 	port = rte_sched_port_config(&port_params);
255de3cfa2cSIntel 	if (port == NULL){
256de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "Unable to config sched port\n");
257de3cfa2cSIntel 	}
258de3cfa2cSIntel 
259de3cfa2cSIntel 	for (subport = 0; subport < port_params.n_subports_per_port; subport ++) {
260de3cfa2cSIntel 		err = rte_sched_subport_config(port, subport, &subport_params[subport]);
261de3cfa2cSIntel 		if (err) {
262de3cfa2cSIntel 			rte_exit(EXIT_FAILURE, "Unable to config sched subport %u, err=%d\n",
263de3cfa2cSIntel 					subport, err);
264de3cfa2cSIntel 		}
265de3cfa2cSIntel 
266de3cfa2cSIntel 		for (pipe = 0; pipe < port_params.n_pipes_per_subport; pipe ++) {
267de3cfa2cSIntel 			if (app_pipe_to_profile[subport][pipe] != -1) {
268de3cfa2cSIntel 				err = rte_sched_pipe_config(port, subport, pipe,
269de3cfa2cSIntel 						app_pipe_to_profile[subport][pipe]);
270de3cfa2cSIntel 				if (err) {
271de3cfa2cSIntel 					rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u "
272de3cfa2cSIntel 							"for profile %d, err=%d\n", pipe,
273de3cfa2cSIntel 							app_pipe_to_profile[subport][pipe], err);
274de3cfa2cSIntel 				}
275de3cfa2cSIntel 			}
276de3cfa2cSIntel 		}
277de3cfa2cSIntel 	}
278de3cfa2cSIntel 
279de3cfa2cSIntel 	return port;
280de3cfa2cSIntel }
281de3cfa2cSIntel 
282de3cfa2cSIntel static int
283de3cfa2cSIntel app_load_cfg_profile(const char *profile)
284de3cfa2cSIntel {
285de3cfa2cSIntel 	if (profile == NULL)
286de3cfa2cSIntel 		return 0;
287de3cfa2cSIntel 
288de3cfa2cSIntel 	struct cfg_file *cfg_file = cfg_load(profile, 0);
289de3cfa2cSIntel 	if (cfg_file == NULL)
290de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile);
291de3cfa2cSIntel 
292de3cfa2cSIntel 	cfg_load_port(cfg_file, &port_params);
293de3cfa2cSIntel 	cfg_load_subport(cfg_file, subport_params);
294de3cfa2cSIntel 	cfg_load_pipe(cfg_file, pipe_profiles);
295de3cfa2cSIntel 
296de3cfa2cSIntel 	cfg_close(cfg_file);
297de3cfa2cSIntel 
298de3cfa2cSIntel 	return 0;
299de3cfa2cSIntel }
300de3cfa2cSIntel 
301de3cfa2cSIntel int app_init(void)
302de3cfa2cSIntel {
303de3cfa2cSIntel 	uint32_t i;
304de3cfa2cSIntel 	char ring_name[MAX_NAME_LEN];
305de3cfa2cSIntel 	char pool_name[MAX_NAME_LEN];
306de3cfa2cSIntel 
307de3cfa2cSIntel 	if (rte_eth_dev_count() == 0)
308de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n");
309de3cfa2cSIntel 
310de3cfa2cSIntel 	/* load configuration profile */
311de3cfa2cSIntel 	if (app_load_cfg_profile(cfg_profile) != 0)
312de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "Invalid configuration profile\n");
313de3cfa2cSIntel 
314de3cfa2cSIntel 	/* Initialize each active flow */
315de3cfa2cSIntel 	for(i = 0; i < nb_pfc; i++) {
316de3cfa2cSIntel 		uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core);
317de3cfa2cSIntel 		struct rte_ring *ring;
318de3cfa2cSIntel 
3196f41fe75SStephen Hemminger 		snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core);
320de3cfa2cSIntel 		ring = rte_ring_lookup(ring_name);
321de3cfa2cSIntel 		if (ring == NULL)
322de3cfa2cSIntel 			qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size,
323de3cfa2cSIntel 			 	socket, RING_F_SP_ENQ | RING_F_SC_DEQ);
324de3cfa2cSIntel 		else
325de3cfa2cSIntel 			qos_conf[i].rx_ring = ring;
326de3cfa2cSIntel 
3276f41fe75SStephen Hemminger 		snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core);
328de3cfa2cSIntel 		ring = rte_ring_lookup(ring_name);
329de3cfa2cSIntel 		if (ring == NULL)
330de3cfa2cSIntel 			qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size,
331de3cfa2cSIntel 				socket, RING_F_SP_ENQ | RING_F_SC_DEQ);
332de3cfa2cSIntel 		else
333de3cfa2cSIntel 			qos_conf[i].tx_ring = ring;
334de3cfa2cSIntel 
335de3cfa2cSIntel 
336de3cfa2cSIntel 		/* create the mbuf pools for each RX Port */
3376f41fe75SStephen Hemminger 		snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i);
338*ea0c20eaSOlivier Matz 		qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name,
339*ea0c20eaSOlivier Matz 			mp_size, burst_conf.rx_burst * 4, 0, MBUF_DATA_SIZE,
340*ea0c20eaSOlivier Matz 			rte_eth_dev_socket_id(qos_conf[i].rx_port));
341de3cfa2cSIntel 		if (qos_conf[i].mbuf_pool == NULL)
342de3cfa2cSIntel 			rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i);
343de3cfa2cSIntel 
344de3cfa2cSIntel 		app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool);
345de3cfa2cSIntel 		app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool);
346de3cfa2cSIntel 
347cfd5c971SIntel 		qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket);
348de3cfa2cSIntel 	}
349de3cfa2cSIntel 
350de3cfa2cSIntel 	RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n",
351de3cfa2cSIntel 			 rte_get_timer_hz());
352de3cfa2cSIntel 
353de3cfa2cSIntel 	RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u,"
354e93b24a3SIntel 			 "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size,
355de3cfa2cSIntel 			 ring_conf.tx_size);
356de3cfa2cSIntel 
357de3cfa2cSIntel 	RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n"
358de3cfa2cSIntel 						  "             Worker read/QoS enqueue = %hu,\n"
359de3cfa2cSIntel 						  "             QoS dequeue = %hu, Worker write = %hu\n",
360de3cfa2cSIntel 		burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst,
361de3cfa2cSIntel 		burst_conf.qos_dequeue, burst_conf.tx_burst);
362de3cfa2cSIntel 
363de3cfa2cSIntel 	RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu),"
364de3cfa2cSIntel 				 "TX (p = %hhu, h = %hhu, w = %hhu)\n",
365de3cfa2cSIntel 		rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh,
366de3cfa2cSIntel 		tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh);
367de3cfa2cSIntel 
368de3cfa2cSIntel 	return 0;
369de3cfa2cSIntel }
370