13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #include <stdint.h> 6de3cfa2cSIntel #include <memory.h> 7de3cfa2cSIntel 8de3cfa2cSIntel #include <rte_log.h> 9de3cfa2cSIntel #include <rte_mbuf.h> 10de3cfa2cSIntel #include <rte_debug.h> 11de3cfa2cSIntel #include <rte_ethdev.h> 12de3cfa2cSIntel #include <rte_mempool.h> 13de3cfa2cSIntel #include <rte_sched.h> 14de3cfa2cSIntel #include <rte_cycles.h> 15de3cfa2cSIntel #include <rte_string_fns.h> 16db935d01SMichal Jastrzebski #include <rte_cfgfile.h> 17de3cfa2cSIntel 18de3cfa2cSIntel #include "main.h" 19de3cfa2cSIntel #include "cfg_file.h" 20de3cfa2cSIntel 21de3cfa2cSIntel uint32_t app_numa_mask = 0; 22de3cfa2cSIntel static uint32_t app_inited_port_mask = 0; 23de3cfa2cSIntel 24de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 25de3cfa2cSIntel 26de3cfa2cSIntel #define MAX_NAME_LEN 32 27de3cfa2cSIntel 28de3cfa2cSIntel struct ring_conf ring_conf = { 29de3cfa2cSIntel .rx_size = APP_RX_DESC_DEFAULT, 30de3cfa2cSIntel .ring_size = APP_RING_SIZE, 31de3cfa2cSIntel .tx_size = APP_TX_DESC_DEFAULT, 32de3cfa2cSIntel }; 33de3cfa2cSIntel 34de3cfa2cSIntel struct burst_conf burst_conf = { 35de3cfa2cSIntel .rx_burst = MAX_PKT_RX_BURST, 36de3cfa2cSIntel .ring_burst = PKT_ENQUEUE, 37de3cfa2cSIntel .qos_dequeue = PKT_DEQUEUE, 38de3cfa2cSIntel .tx_burst = MAX_PKT_TX_BURST, 39de3cfa2cSIntel }; 40de3cfa2cSIntel 41de3cfa2cSIntel struct ring_thresh rx_thresh = { 42de3cfa2cSIntel .pthresh = RX_PTHRESH, 43de3cfa2cSIntel .hthresh = RX_HTHRESH, 44de3cfa2cSIntel .wthresh = RX_WTHRESH, 45de3cfa2cSIntel }; 46de3cfa2cSIntel 47de3cfa2cSIntel struct ring_thresh tx_thresh = { 48de3cfa2cSIntel .pthresh = TX_PTHRESH, 49de3cfa2cSIntel .hthresh = TX_HTHRESH, 50de3cfa2cSIntel .wthresh = TX_WTHRESH, 51de3cfa2cSIntel }; 52de3cfa2cSIntel 53de3cfa2cSIntel uint32_t nb_pfc; 54de3cfa2cSIntel const char *cfg_profile = NULL; 55e93b24a3SIntel int mp_size = NB_MBUF; 56de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS]; 57de3cfa2cSIntel 58e2ef4628SShahaf Shuler static struct rte_eth_conf port_conf = { 59de3cfa2cSIntel .rxmode = { 6035b2d13fSOlivier Matz .max_rx_pkt_len = RTE_ETHER_MAX_LEN, 61de3cfa2cSIntel .split_hdr_size = 0, 62de3cfa2cSIntel }, 63de3cfa2cSIntel .txmode = { 64de3cfa2cSIntel .mq_mode = ETH_DCB_NONE, 65de3cfa2cSIntel }, 66de3cfa2cSIntel }; 67de3cfa2cSIntel 68de3cfa2cSIntel static int 69f8244c63SZhiyong Yang app_init_port(uint16_t portid, struct rte_mempool *mp) 70de3cfa2cSIntel { 71de3cfa2cSIntel int ret; 72de3cfa2cSIntel struct rte_eth_link link; 73e2ef4628SShahaf Shuler struct rte_eth_dev_info dev_info; 74de3cfa2cSIntel struct rte_eth_rxconf rx_conf; 75de3cfa2cSIntel struct rte_eth_txconf tx_conf; 7660efb44fSRoman Zhukov uint16_t rx_size; 7760efb44fSRoman Zhukov uint16_t tx_size; 78e2ef4628SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf; 79*db4e8135SIvan Dyukov char link_status_text[RTE_ETH_LINK_MAX_STR_LEN]; 80de3cfa2cSIntel 81de3cfa2cSIntel /* check if port already initialized (multistream configuration) */ 82de3cfa2cSIntel if (app_inited_port_mask & (1u << portid)) 83de3cfa2cSIntel return 0; 84de3cfa2cSIntel 85de3cfa2cSIntel rx_conf.rx_thresh.pthresh = rx_thresh.pthresh; 86de3cfa2cSIntel rx_conf.rx_thresh.hthresh = rx_thresh.hthresh; 87de3cfa2cSIntel rx_conf.rx_thresh.wthresh = rx_thresh.wthresh; 88de3cfa2cSIntel rx_conf.rx_free_thresh = 32; 89de3cfa2cSIntel rx_conf.rx_drop_en = 0; 9096b5077cSJasvinder Singh rx_conf.rx_deferred_start = 0; 91de3cfa2cSIntel 92de3cfa2cSIntel tx_conf.tx_thresh.pthresh = tx_thresh.pthresh; 93de3cfa2cSIntel tx_conf.tx_thresh.hthresh = tx_thresh.hthresh; 94de3cfa2cSIntel tx_conf.tx_thresh.wthresh = tx_thresh.wthresh; 95de3cfa2cSIntel tx_conf.tx_free_thresh = 0; 96de3cfa2cSIntel tx_conf.tx_rs_thresh = 0; 9796b5077cSJasvinder Singh tx_conf.tx_deferred_start = 0; 98de3cfa2cSIntel 99de3cfa2cSIntel /* init port */ 100f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "Initializing port %"PRIu16"... ", portid); 101de3cfa2cSIntel fflush(stdout); 10245069992SIvan Ilchenko 10345069992SIvan Ilchenko ret = rte_eth_dev_info_get(portid, &dev_info); 10445069992SIvan Ilchenko if (ret != 0) 10545069992SIvan Ilchenko rte_exit(EXIT_FAILURE, 10645069992SIvan Ilchenko "Error during getting device (port %u) info: %s\n", 10745069992SIvan Ilchenko portid, strerror(-ret)); 10845069992SIvan Ilchenko 109e2ef4628SShahaf Shuler if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 110e2ef4628SShahaf Shuler local_port_conf.txmode.offloads |= 111e2ef4628SShahaf Shuler DEV_TX_OFFLOAD_MBUF_FAST_FREE; 112e2ef4628SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf); 113de3cfa2cSIntel if (ret < 0) 114f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 115f8244c63SZhiyong Yang "Cannot configure device: err=%d, port=%u\n", 116f8244c63SZhiyong Yang ret, portid); 117de3cfa2cSIntel 11860efb44fSRoman Zhukov rx_size = ring_conf.rx_size; 11960efb44fSRoman Zhukov tx_size = ring_conf.tx_size; 12060efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &rx_size, &tx_size); 12160efb44fSRoman Zhukov if (ret < 0) 122f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 123f8244c63SZhiyong Yang "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n", 124f8244c63SZhiyong Yang ret, portid); 12560efb44fSRoman Zhukov ring_conf.rx_size = rx_size; 12660efb44fSRoman Zhukov ring_conf.tx_size = tx_size; 12760efb44fSRoman Zhukov 128de3cfa2cSIntel /* init one RX queue */ 129de3cfa2cSIntel fflush(stdout); 130e2ef4628SShahaf Shuler rx_conf.offloads = local_port_conf.rxmode.offloads; 131de3cfa2cSIntel ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size, 132de3cfa2cSIntel rte_eth_dev_socket_id(portid), &rx_conf, mp); 133de3cfa2cSIntel if (ret < 0) 134f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 135f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u\n", 136f8244c63SZhiyong Yang ret, portid); 137de3cfa2cSIntel 138de3cfa2cSIntel /* init one TX queue */ 139de3cfa2cSIntel fflush(stdout); 140e2ef4628SShahaf Shuler tx_conf.offloads = local_port_conf.txmode.offloads; 141de3cfa2cSIntel ret = rte_eth_tx_queue_setup(portid, 0, 142de3cfa2cSIntel (uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf); 143de3cfa2cSIntel if (ret < 0) 144f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 145f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n", 146f8244c63SZhiyong Yang ret, portid, 0); 147de3cfa2cSIntel 148de3cfa2cSIntel /* Start device */ 149de3cfa2cSIntel ret = rte_eth_dev_start(portid); 150de3cfa2cSIntel if (ret < 0) 151f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 152f8244c63SZhiyong Yang "rte_pmd_port_start: err=%d, port=%u\n", 153f8244c63SZhiyong Yang ret, portid); 154de3cfa2cSIntel 155de3cfa2cSIntel printf("done: "); 156de3cfa2cSIntel 157de3cfa2cSIntel /* get link status */ 15822e5c73bSIgor Romanov ret = rte_eth_link_get(portid, &link); 15922e5c73bSIgor Romanov if (ret < 0) 16022e5c73bSIgor Romanov rte_exit(EXIT_FAILURE, 16122e5c73bSIgor Romanov "rte_eth_link_get: err=%d, port=%u: %s\n", 16222e5c73bSIgor Romanov ret, portid, rte_strerror(-ret)); 16322e5c73bSIgor Romanov 164*db4e8135SIvan Dyukov rte_eth_link_to_str(link_status_text, sizeof(link_status_text), &link); 165*db4e8135SIvan Dyukov printf("%s\n", link_status_text); 166*db4e8135SIvan Dyukov 167f430bbceSIvan Ilchenko ret = rte_eth_promiscuous_enable(portid); 168f430bbceSIvan Ilchenko if (ret != 0) 169f430bbceSIvan Ilchenko rte_exit(EXIT_FAILURE, 170f430bbceSIvan Ilchenko "rte_eth_promiscuous_enable: err=%s, port=%u\n", 171f430bbceSIvan Ilchenko rte_strerror(-ret), portid); 172de3cfa2cSIntel 173de3cfa2cSIntel /* mark port as initialized */ 174de3cfa2cSIntel app_inited_port_mask |= 1u << portid; 175de3cfa2cSIntel 176de3cfa2cSIntel return 0; 177de3cfa2cSIntel } 178de3cfa2cSIntel 179be1e5332SJasvinder Singh static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = { 180de3cfa2cSIntel { /* Profile #0 */ 181de3cfa2cSIntel .tb_rate = 305175, 182de3cfa2cSIntel .tb_size = 1000000, 183de3cfa2cSIntel 184be1e5332SJasvinder Singh .tc_rate = {305175, 305175, 305175, 305175, 305175, 305175, 185be1e5332SJasvinder Singh 305175, 305175, 305175, 305175, 305175, 305175, 305175}, 186de3cfa2cSIntel .tc_period = 40, 187de3cfa2cSIntel #ifdef RTE_SCHED_SUBPORT_TC_OV 188835c5409SIntel .tc_ov_weight = 1, 189de3cfa2cSIntel #endif 190de3cfa2cSIntel 191e16b06daSJasvinder Singh .wrr_weights = {1, 1, 1, 1}, 192de3cfa2cSIntel }, 193de3cfa2cSIntel }; 194de3cfa2cSIntel 195b0c1628bSJasvinder Singh struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { 196b0c1628bSJasvinder Singh { 197b0c1628bSJasvinder Singh .tb_rate = 1250000000, 198b0c1628bSJasvinder Singh .tb_size = 1000000, 199b0c1628bSJasvinder Singh 200b0c1628bSJasvinder Singh .tc_rate = {1250000000, 1250000000, 1250000000, 1250000000, 201b0c1628bSJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000, 1250000000, 202b0c1628bSJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000}, 203b0c1628bSJasvinder Singh .tc_period = 10, 204b0c1628bSJasvinder Singh .n_pipes_per_subport_enabled = 4096, 205be1e5332SJasvinder Singh .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, 206de3cfa2cSIntel .pipe_profiles = pipe_profiles, 207b0c1628bSJasvinder Singh .n_pipe_profiles = sizeof(pipe_profiles) / 208b0c1628bSJasvinder Singh sizeof(struct rte_sched_pipe_params), 209be1e5332SJasvinder Singh .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, 210de3cfa2cSIntel #ifdef RTE_SCHED_RED 211de3cfa2cSIntel .red_params = { 212de3cfa2cSIntel /* Traffic Class 0 Colors Green / Yellow / Red */ 213de3cfa2cSIntel [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 214de3cfa2cSIntel [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 215de3cfa2cSIntel [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 216de3cfa2cSIntel 217de3cfa2cSIntel /* Traffic Class 1 - Colors Green / Yellow / Red */ 218de3cfa2cSIntel [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 219de3cfa2cSIntel [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 220de3cfa2cSIntel [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 221de3cfa2cSIntel 222de3cfa2cSIntel /* Traffic Class 2 - Colors Green / Yellow / Red */ 223de3cfa2cSIntel [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 224de3cfa2cSIntel [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 225de3cfa2cSIntel [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 226de3cfa2cSIntel 227de3cfa2cSIntel /* Traffic Class 3 - Colors Green / Yellow / Red */ 228de3cfa2cSIntel [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 229de3cfa2cSIntel [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 230be1e5332SJasvinder Singh [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 231be1e5332SJasvinder Singh 232be1e5332SJasvinder Singh /* Traffic Class 4 - Colors Green / Yellow / Red */ 233be1e5332SJasvinder Singh [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 234be1e5332SJasvinder Singh [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 235be1e5332SJasvinder Singh [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 236be1e5332SJasvinder Singh 237be1e5332SJasvinder Singh /* Traffic Class 5 - Colors Green / Yellow / Red */ 238be1e5332SJasvinder Singh [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 239be1e5332SJasvinder Singh [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 240be1e5332SJasvinder Singh [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 241be1e5332SJasvinder Singh 242be1e5332SJasvinder Singh /* Traffic Class 6 - Colors Green / Yellow / Red */ 243be1e5332SJasvinder Singh [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 244be1e5332SJasvinder Singh [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 245be1e5332SJasvinder Singh [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 246be1e5332SJasvinder Singh 247be1e5332SJasvinder Singh /* Traffic Class 7 - Colors Green / Yellow / Red */ 248be1e5332SJasvinder Singh [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 249be1e5332SJasvinder Singh [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 250be1e5332SJasvinder Singh [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 251be1e5332SJasvinder Singh 252be1e5332SJasvinder Singh /* Traffic Class 8 - Colors Green / Yellow / Red */ 253be1e5332SJasvinder Singh [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 254be1e5332SJasvinder Singh [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 255be1e5332SJasvinder Singh [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 256be1e5332SJasvinder Singh 257be1e5332SJasvinder Singh /* Traffic Class 9 - Colors Green / Yellow / Red */ 258be1e5332SJasvinder Singh [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 259be1e5332SJasvinder Singh [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 260be1e5332SJasvinder Singh [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 261be1e5332SJasvinder Singh 262be1e5332SJasvinder Singh /* Traffic Class 10 - Colors Green / Yellow / Red */ 263be1e5332SJasvinder Singh [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 264be1e5332SJasvinder Singh [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 265be1e5332SJasvinder Singh [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 266be1e5332SJasvinder Singh 267be1e5332SJasvinder Singh /* Traffic Class 11 - Colors Green / Yellow / Red */ 268be1e5332SJasvinder Singh [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 269be1e5332SJasvinder Singh [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 270be1e5332SJasvinder Singh [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 271be1e5332SJasvinder Singh 272be1e5332SJasvinder Singh /* Traffic Class 12 - Colors Green / Yellow / Red */ 273be1e5332SJasvinder Singh [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 274be1e5332SJasvinder Singh [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 275be1e5332SJasvinder Singh [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 276be1e5332SJasvinder Singh }, 277de3cfa2cSIntel #endif /* RTE_SCHED_RED */ 278b0c1628bSJasvinder Singh }, 279b0c1628bSJasvinder Singh }; 280b0c1628bSJasvinder Singh 281b0c1628bSJasvinder Singh struct rte_sched_port_params port_params = { 282b0c1628bSJasvinder Singh .name = "port_scheduler_0", 283b0c1628bSJasvinder Singh .socket = 0, /* computed */ 284b0c1628bSJasvinder Singh .rate = 0, /* computed */ 285b0c1628bSJasvinder Singh .mtu = 6 + 6 + 4 + 4 + 2 + 1500, 286b0c1628bSJasvinder Singh .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT, 287b0c1628bSJasvinder Singh .n_subports_per_port = 1, 288b0c1628bSJasvinder Singh .n_pipes_per_subport = MAX_SCHED_PIPES, 289de3cfa2cSIntel }; 290de3cfa2cSIntel 291de3cfa2cSIntel static struct rte_sched_port * 292de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid) 293de3cfa2cSIntel { 294de3cfa2cSIntel static char port_name[32]; /* static as referenced from global port_params*/ 295de3cfa2cSIntel struct rte_eth_link link; 296de3cfa2cSIntel struct rte_sched_port *port = NULL; 297de3cfa2cSIntel uint32_t pipe, subport; 298de3cfa2cSIntel int err; 299de3cfa2cSIntel 30022e5c73bSIgor Romanov err = rte_eth_link_get(portid, &link); 30122e5c73bSIgor Romanov if (err < 0) 30222e5c73bSIgor Romanov rte_exit(EXIT_FAILURE, 30322e5c73bSIgor Romanov "rte_eth_link_get: err=%d, port=%u: %s\n", 30422e5c73bSIgor Romanov err, portid, rte_strerror(-err)); 305de3cfa2cSIntel 306de3cfa2cSIntel port_params.socket = socketid; 307de3cfa2cSIntel port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8; 3086f41fe75SStephen Hemminger snprintf(port_name, sizeof(port_name), "port_%d", portid); 309de3cfa2cSIntel port_params.name = port_name; 310de3cfa2cSIntel 311de3cfa2cSIntel port = rte_sched_port_config(&port_params); 312de3cfa2cSIntel if (port == NULL){ 313de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched port\n"); 314de3cfa2cSIntel } 315de3cfa2cSIntel 316de3cfa2cSIntel for (subport = 0; subport < port_params.n_subports_per_port; subport ++) { 317de3cfa2cSIntel err = rte_sched_subport_config(port, subport, &subport_params[subport]); 318de3cfa2cSIntel if (err) { 319de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched subport %u, err=%d\n", 320de3cfa2cSIntel subport, err); 321de3cfa2cSIntel } 322de3cfa2cSIntel 323b0c1628bSJasvinder Singh uint32_t n_pipes_per_subport = 324b0c1628bSJasvinder Singh subport_params[subport].n_pipes_per_subport_enabled; 325b0c1628bSJasvinder Singh 326b0c1628bSJasvinder Singh for (pipe = 0; pipe < n_pipes_per_subport; pipe++) { 327de3cfa2cSIntel if (app_pipe_to_profile[subport][pipe] != -1) { 328de3cfa2cSIntel err = rte_sched_pipe_config(port, subport, pipe, 329de3cfa2cSIntel app_pipe_to_profile[subport][pipe]); 330de3cfa2cSIntel if (err) { 331de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u " 332de3cfa2cSIntel "for profile %d, err=%d\n", pipe, 333de3cfa2cSIntel app_pipe_to_profile[subport][pipe], err); 334de3cfa2cSIntel } 335de3cfa2cSIntel } 336de3cfa2cSIntel } 337de3cfa2cSIntel } 338de3cfa2cSIntel 339de3cfa2cSIntel return port; 340de3cfa2cSIntel } 341de3cfa2cSIntel 342de3cfa2cSIntel static int 343de3cfa2cSIntel app_load_cfg_profile(const char *profile) 344de3cfa2cSIntel { 345de3cfa2cSIntel if (profile == NULL) 346de3cfa2cSIntel return 0; 347db935d01SMichal Jastrzebski struct rte_cfgfile *file = rte_cfgfile_load(profile, 0); 348db935d01SMichal Jastrzebski if (file == NULL) 349de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile); 350de3cfa2cSIntel 351db935d01SMichal Jastrzebski cfg_load_port(file, &port_params); 352db935d01SMichal Jastrzebski cfg_load_subport(file, subport_params); 353db935d01SMichal Jastrzebski cfg_load_pipe(file, pipe_profiles); 354de3cfa2cSIntel 355db935d01SMichal Jastrzebski rte_cfgfile_close(file); 356de3cfa2cSIntel 357de3cfa2cSIntel return 0; 358de3cfa2cSIntel } 359de3cfa2cSIntel 360de3cfa2cSIntel int app_init(void) 361de3cfa2cSIntel { 362de3cfa2cSIntel uint32_t i; 363de3cfa2cSIntel char ring_name[MAX_NAME_LEN]; 364de3cfa2cSIntel char pool_name[MAX_NAME_LEN]; 365de3cfa2cSIntel 366d9a42a69SThomas Monjalon if (rte_eth_dev_count_avail() == 0) 367de3cfa2cSIntel rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n"); 368de3cfa2cSIntel 369de3cfa2cSIntel /* load configuration profile */ 370de3cfa2cSIntel if (app_load_cfg_profile(cfg_profile) != 0) 371de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Invalid configuration profile\n"); 372de3cfa2cSIntel 373de3cfa2cSIntel /* Initialize each active flow */ 374de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 375de3cfa2cSIntel uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); 376de3cfa2cSIntel struct rte_ring *ring; 377de3cfa2cSIntel 3786f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); 379de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 380de3cfa2cSIntel if (ring == NULL) 381de3cfa2cSIntel qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 382de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 383de3cfa2cSIntel else 384de3cfa2cSIntel qos_conf[i].rx_ring = ring; 385de3cfa2cSIntel 3866f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core); 387de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 388de3cfa2cSIntel if (ring == NULL) 389de3cfa2cSIntel qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 390de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 391de3cfa2cSIntel else 392de3cfa2cSIntel qos_conf[i].tx_ring = ring; 393de3cfa2cSIntel 394de3cfa2cSIntel 395de3cfa2cSIntel /* create the mbuf pools for each RX Port */ 3966f41fe75SStephen Hemminger snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i); 397ea0c20eaSOlivier Matz qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name, 398824cb29cSKonstantin Ananyev mp_size, burst_conf.rx_burst * 4, 0, 399824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, 400ea0c20eaSOlivier Matz rte_eth_dev_socket_id(qos_conf[i].rx_port)); 401de3cfa2cSIntel if (qos_conf[i].mbuf_pool == NULL) 402de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i); 403de3cfa2cSIntel 404de3cfa2cSIntel app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); 405de3cfa2cSIntel app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); 406de3cfa2cSIntel 407cfd5c971SIntel qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket); 408de3cfa2cSIntel } 409de3cfa2cSIntel 410de3cfa2cSIntel RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n", 411de3cfa2cSIntel rte_get_timer_hz()); 412de3cfa2cSIntel 413de3cfa2cSIntel RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," 414e93b24a3SIntel "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size, 415de3cfa2cSIntel ring_conf.tx_size); 416de3cfa2cSIntel 417de3cfa2cSIntel RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n" 418de3cfa2cSIntel " Worker read/QoS enqueue = %hu,\n" 419de3cfa2cSIntel " QoS dequeue = %hu, Worker write = %hu\n", 420de3cfa2cSIntel burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst, 421de3cfa2cSIntel burst_conf.qos_dequeue, burst_conf.tx_burst); 422de3cfa2cSIntel 423de3cfa2cSIntel RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," 424de3cfa2cSIntel "TX (p = %hhu, h = %hhu, w = %hhu)\n", 425de3cfa2cSIntel rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh, 426de3cfa2cSIntel tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh); 427de3cfa2cSIntel 428de3cfa2cSIntel return 0; 429de3cfa2cSIntel } 430