13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #include <stdint.h> 6de3cfa2cSIntel #include <memory.h> 7de3cfa2cSIntel 8de3cfa2cSIntel #include <rte_log.h> 9de3cfa2cSIntel #include <rte_mbuf.h> 10de3cfa2cSIntel #include <rte_debug.h> 11de3cfa2cSIntel #include <rte_ethdev.h> 12de3cfa2cSIntel #include <rte_mempool.h> 13de3cfa2cSIntel #include <rte_sched.h> 14de3cfa2cSIntel #include <rte_cycles.h> 15de3cfa2cSIntel #include <rte_string_fns.h> 16db935d01SMichal Jastrzebski #include <rte_cfgfile.h> 17de3cfa2cSIntel 18de3cfa2cSIntel #include "main.h" 19de3cfa2cSIntel #include "cfg_file.h" 20de3cfa2cSIntel 21de3cfa2cSIntel uint32_t app_numa_mask = 0; 22de3cfa2cSIntel static uint32_t app_inited_port_mask = 0; 23de3cfa2cSIntel 24de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 25de3cfa2cSIntel 26de3cfa2cSIntel #define MAX_NAME_LEN 32 27de3cfa2cSIntel 28de3cfa2cSIntel struct ring_conf ring_conf = { 29de3cfa2cSIntel .rx_size = APP_RX_DESC_DEFAULT, 30de3cfa2cSIntel .ring_size = APP_RING_SIZE, 31de3cfa2cSIntel .tx_size = APP_TX_DESC_DEFAULT, 32de3cfa2cSIntel }; 33de3cfa2cSIntel 34de3cfa2cSIntel struct burst_conf burst_conf = { 35de3cfa2cSIntel .rx_burst = MAX_PKT_RX_BURST, 36de3cfa2cSIntel .ring_burst = PKT_ENQUEUE, 37de3cfa2cSIntel .qos_dequeue = PKT_DEQUEUE, 38de3cfa2cSIntel .tx_burst = MAX_PKT_TX_BURST, 39de3cfa2cSIntel }; 40de3cfa2cSIntel 41de3cfa2cSIntel struct ring_thresh rx_thresh = { 42de3cfa2cSIntel .pthresh = RX_PTHRESH, 43de3cfa2cSIntel .hthresh = RX_HTHRESH, 44de3cfa2cSIntel .wthresh = RX_WTHRESH, 45de3cfa2cSIntel }; 46de3cfa2cSIntel 47de3cfa2cSIntel struct ring_thresh tx_thresh = { 48de3cfa2cSIntel .pthresh = TX_PTHRESH, 49de3cfa2cSIntel .hthresh = TX_HTHRESH, 50de3cfa2cSIntel .wthresh = TX_WTHRESH, 51de3cfa2cSIntel }; 52de3cfa2cSIntel 53de3cfa2cSIntel uint32_t nb_pfc; 54de3cfa2cSIntel const char *cfg_profile = NULL; 55e93b24a3SIntel int mp_size = NB_MBUF; 56de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS]; 57de3cfa2cSIntel 58e2ef4628SShahaf Shuler static struct rte_eth_conf port_conf = { 59de3cfa2cSIntel .rxmode = { 60de3cfa2cSIntel .max_rx_pkt_len = ETHER_MAX_LEN, 61de3cfa2cSIntel .split_hdr_size = 0, 62e2ef4628SShahaf Shuler .ignore_offload_bitfield = 1, 63e2ef4628SShahaf Shuler .offloads = DEV_RX_OFFLOAD_CRC_STRIP, 64de3cfa2cSIntel }, 65de3cfa2cSIntel .txmode = { 66de3cfa2cSIntel .mq_mode = ETH_DCB_NONE, 67de3cfa2cSIntel }, 68de3cfa2cSIntel }; 69de3cfa2cSIntel 70de3cfa2cSIntel static int 71f8244c63SZhiyong Yang app_init_port(uint16_t portid, struct rte_mempool *mp) 72de3cfa2cSIntel { 73de3cfa2cSIntel int ret; 74de3cfa2cSIntel struct rte_eth_link link; 75e2ef4628SShahaf Shuler struct rte_eth_dev_info dev_info; 76de3cfa2cSIntel struct rte_eth_rxconf rx_conf; 77de3cfa2cSIntel struct rte_eth_txconf tx_conf; 7860efb44fSRoman Zhukov uint16_t rx_size; 7960efb44fSRoman Zhukov uint16_t tx_size; 80e2ef4628SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf; 81de3cfa2cSIntel 82de3cfa2cSIntel /* check if port already initialized (multistream configuration) */ 83de3cfa2cSIntel if (app_inited_port_mask & (1u << portid)) 84de3cfa2cSIntel return 0; 85de3cfa2cSIntel 86de3cfa2cSIntel rx_conf.rx_thresh.pthresh = rx_thresh.pthresh; 87de3cfa2cSIntel rx_conf.rx_thresh.hthresh = rx_thresh.hthresh; 88de3cfa2cSIntel rx_conf.rx_thresh.wthresh = rx_thresh.wthresh; 89de3cfa2cSIntel rx_conf.rx_free_thresh = 32; 90de3cfa2cSIntel rx_conf.rx_drop_en = 0; 9196b5077cSJasvinder Singh rx_conf.rx_deferred_start = 0; 92de3cfa2cSIntel 93de3cfa2cSIntel tx_conf.tx_thresh.pthresh = tx_thresh.pthresh; 94de3cfa2cSIntel tx_conf.tx_thresh.hthresh = tx_thresh.hthresh; 95de3cfa2cSIntel tx_conf.tx_thresh.wthresh = tx_thresh.wthresh; 96de3cfa2cSIntel tx_conf.tx_free_thresh = 0; 97de3cfa2cSIntel tx_conf.tx_rs_thresh = 0; 9896b5077cSJasvinder Singh tx_conf.tx_deferred_start = 0; 99e2ef4628SShahaf Shuler tx_conf.txq_flags = ETH_TXQ_FLAGS_IGNORE; 100de3cfa2cSIntel 101de3cfa2cSIntel /* init port */ 102f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "Initializing port %"PRIu16"... ", portid); 103de3cfa2cSIntel fflush(stdout); 104e2ef4628SShahaf Shuler rte_eth_dev_info_get(portid, &dev_info); 105e2ef4628SShahaf Shuler if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 106e2ef4628SShahaf Shuler local_port_conf.txmode.offloads |= 107e2ef4628SShahaf Shuler DEV_TX_OFFLOAD_MBUF_FAST_FREE; 108e2ef4628SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf); 109de3cfa2cSIntel if (ret < 0) 110f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 111f8244c63SZhiyong Yang "Cannot configure device: err=%d, port=%u\n", 112f8244c63SZhiyong Yang ret, portid); 113de3cfa2cSIntel 11460efb44fSRoman Zhukov rx_size = ring_conf.rx_size; 11560efb44fSRoman Zhukov tx_size = ring_conf.tx_size; 11660efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &rx_size, &tx_size); 11760efb44fSRoman Zhukov if (ret < 0) 118f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 119f8244c63SZhiyong Yang "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n", 120f8244c63SZhiyong Yang ret, portid); 12160efb44fSRoman Zhukov ring_conf.rx_size = rx_size; 12260efb44fSRoman Zhukov ring_conf.tx_size = tx_size; 12360efb44fSRoman Zhukov 124de3cfa2cSIntel /* init one RX queue */ 125de3cfa2cSIntel fflush(stdout); 126e2ef4628SShahaf Shuler rx_conf.offloads = local_port_conf.rxmode.offloads; 127de3cfa2cSIntel ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size, 128de3cfa2cSIntel rte_eth_dev_socket_id(portid), &rx_conf, mp); 129de3cfa2cSIntel if (ret < 0) 130f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 131f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u\n", 132f8244c63SZhiyong Yang ret, portid); 133de3cfa2cSIntel 134de3cfa2cSIntel /* init one TX queue */ 135de3cfa2cSIntel fflush(stdout); 136e2ef4628SShahaf Shuler tx_conf.offloads = local_port_conf.txmode.offloads; 137de3cfa2cSIntel ret = rte_eth_tx_queue_setup(portid, 0, 138de3cfa2cSIntel (uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf); 139de3cfa2cSIntel if (ret < 0) 140f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 141f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n", 142f8244c63SZhiyong Yang ret, portid, 0); 143de3cfa2cSIntel 144de3cfa2cSIntel /* Start device */ 145de3cfa2cSIntel ret = rte_eth_dev_start(portid); 146de3cfa2cSIntel if (ret < 0) 147f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 148f8244c63SZhiyong Yang "rte_pmd_port_start: err=%d, port=%u\n", 149f8244c63SZhiyong Yang ret, portid); 150de3cfa2cSIntel 151de3cfa2cSIntel printf("done: "); 152de3cfa2cSIntel 153de3cfa2cSIntel /* get link status */ 154de3cfa2cSIntel rte_eth_link_get(portid, &link); 155de3cfa2cSIntel if (link.link_status) { 156de3cfa2cSIntel printf(" Link Up - speed %u Mbps - %s\n", 157de3cfa2cSIntel (uint32_t) link.link_speed, 158de3cfa2cSIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 159de3cfa2cSIntel ("full-duplex") : ("half-duplex\n")); 160de3cfa2cSIntel } else { 161de3cfa2cSIntel printf(" Link Down\n"); 162de3cfa2cSIntel } 163de3cfa2cSIntel rte_eth_promiscuous_enable(portid); 164de3cfa2cSIntel 165de3cfa2cSIntel /* mark port as initialized */ 166de3cfa2cSIntel app_inited_port_mask |= 1u << portid; 167de3cfa2cSIntel 168de3cfa2cSIntel return 0; 169de3cfa2cSIntel } 170de3cfa2cSIntel 171de3cfa2cSIntel static struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { 172de3cfa2cSIntel { 173de3cfa2cSIntel .tb_rate = 1250000000, 174de3cfa2cSIntel .tb_size = 1000000, 175de3cfa2cSIntel 176de3cfa2cSIntel .tc_rate = {1250000000, 1250000000, 1250000000, 1250000000}, 177de3cfa2cSIntel .tc_period = 10, 178de3cfa2cSIntel }, 179de3cfa2cSIntel }; 180de3cfa2cSIntel 181de3cfa2cSIntel static struct rte_sched_pipe_params pipe_profiles[RTE_SCHED_PIPE_PROFILES_PER_PORT] = { 182de3cfa2cSIntel { /* Profile #0 */ 183de3cfa2cSIntel .tb_rate = 305175, 184de3cfa2cSIntel .tb_size = 1000000, 185de3cfa2cSIntel 186de3cfa2cSIntel .tc_rate = {305175, 305175, 305175, 305175}, 187de3cfa2cSIntel .tc_period = 40, 188de3cfa2cSIntel #ifdef RTE_SCHED_SUBPORT_TC_OV 189835c5409SIntel .tc_ov_weight = 1, 190de3cfa2cSIntel #endif 191de3cfa2cSIntel 192de3cfa2cSIntel .wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 193de3cfa2cSIntel }, 194de3cfa2cSIntel }; 195de3cfa2cSIntel 196de3cfa2cSIntel struct rte_sched_port_params port_params = { 197624148d2SIntel .name = "port_scheduler_0", 198de3cfa2cSIntel .socket = 0, /* computed */ 199de3cfa2cSIntel .rate = 0, /* computed */ 200a91c3cadSIntel .mtu = 6 + 6 + 4 + 4 + 2 + 1500, 201de3cfa2cSIntel .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT, 202de3cfa2cSIntel .n_subports_per_port = 1, 203de3cfa2cSIntel .n_pipes_per_subport = 4096, 204de3cfa2cSIntel .qsize = {64, 64, 64, 64}, 205de3cfa2cSIntel .pipe_profiles = pipe_profiles, 206624148d2SIntel .n_pipe_profiles = sizeof(pipe_profiles) / sizeof(struct rte_sched_pipe_params), 207de3cfa2cSIntel 208de3cfa2cSIntel #ifdef RTE_SCHED_RED 209de3cfa2cSIntel .red_params = { 210de3cfa2cSIntel /* Traffic Class 0 Colors Green / Yellow / Red */ 211de3cfa2cSIntel [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 212de3cfa2cSIntel [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 213de3cfa2cSIntel [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 214de3cfa2cSIntel 215de3cfa2cSIntel /* Traffic Class 1 - Colors Green / Yellow / Red */ 216de3cfa2cSIntel [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 217de3cfa2cSIntel [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 218de3cfa2cSIntel [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 219de3cfa2cSIntel 220de3cfa2cSIntel /* Traffic Class 2 - Colors Green / Yellow / Red */ 221de3cfa2cSIntel [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 222de3cfa2cSIntel [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 223de3cfa2cSIntel [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 224de3cfa2cSIntel 225de3cfa2cSIntel /* Traffic Class 3 - Colors Green / Yellow / Red */ 226de3cfa2cSIntel [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 227de3cfa2cSIntel [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 228de3cfa2cSIntel [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9} 229de3cfa2cSIntel } 230de3cfa2cSIntel #endif /* RTE_SCHED_RED */ 231de3cfa2cSIntel }; 232de3cfa2cSIntel 233de3cfa2cSIntel static struct rte_sched_port * 234de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid) 235de3cfa2cSIntel { 236de3cfa2cSIntel static char port_name[32]; /* static as referenced from global port_params*/ 237de3cfa2cSIntel struct rte_eth_link link; 238de3cfa2cSIntel struct rte_sched_port *port = NULL; 239de3cfa2cSIntel uint32_t pipe, subport; 240de3cfa2cSIntel int err; 241de3cfa2cSIntel 242f8244c63SZhiyong Yang rte_eth_link_get(portid, &link); 243de3cfa2cSIntel 244de3cfa2cSIntel port_params.socket = socketid; 245de3cfa2cSIntel port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8; 2466f41fe75SStephen Hemminger snprintf(port_name, sizeof(port_name), "port_%d", portid); 247de3cfa2cSIntel port_params.name = port_name; 248de3cfa2cSIntel 249de3cfa2cSIntel port = rte_sched_port_config(&port_params); 250de3cfa2cSIntel if (port == NULL){ 251de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched port\n"); 252de3cfa2cSIntel } 253de3cfa2cSIntel 254de3cfa2cSIntel for (subport = 0; subport < port_params.n_subports_per_port; subport ++) { 255de3cfa2cSIntel err = rte_sched_subport_config(port, subport, &subport_params[subport]); 256de3cfa2cSIntel if (err) { 257de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched subport %u, err=%d\n", 258de3cfa2cSIntel subport, err); 259de3cfa2cSIntel } 260de3cfa2cSIntel 261de3cfa2cSIntel for (pipe = 0; pipe < port_params.n_pipes_per_subport; pipe ++) { 262de3cfa2cSIntel if (app_pipe_to_profile[subport][pipe] != -1) { 263de3cfa2cSIntel err = rte_sched_pipe_config(port, subport, pipe, 264de3cfa2cSIntel app_pipe_to_profile[subport][pipe]); 265de3cfa2cSIntel if (err) { 266de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u " 267de3cfa2cSIntel "for profile %d, err=%d\n", pipe, 268de3cfa2cSIntel app_pipe_to_profile[subport][pipe], err); 269de3cfa2cSIntel } 270de3cfa2cSIntel } 271de3cfa2cSIntel } 272de3cfa2cSIntel } 273de3cfa2cSIntel 274de3cfa2cSIntel return port; 275de3cfa2cSIntel } 276de3cfa2cSIntel 277de3cfa2cSIntel static int 278de3cfa2cSIntel app_load_cfg_profile(const char *profile) 279de3cfa2cSIntel { 280de3cfa2cSIntel if (profile == NULL) 281de3cfa2cSIntel return 0; 282db935d01SMichal Jastrzebski struct rte_cfgfile *file = rte_cfgfile_load(profile, 0); 283db935d01SMichal Jastrzebski if (file == NULL) 284de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile); 285de3cfa2cSIntel 286db935d01SMichal Jastrzebski cfg_load_port(file, &port_params); 287db935d01SMichal Jastrzebski cfg_load_subport(file, subport_params); 288db935d01SMichal Jastrzebski cfg_load_pipe(file, pipe_profiles); 289de3cfa2cSIntel 290db935d01SMichal Jastrzebski rte_cfgfile_close(file); 291de3cfa2cSIntel 292de3cfa2cSIntel return 0; 293de3cfa2cSIntel } 294de3cfa2cSIntel 295de3cfa2cSIntel int app_init(void) 296de3cfa2cSIntel { 297de3cfa2cSIntel uint32_t i; 298de3cfa2cSIntel char ring_name[MAX_NAME_LEN]; 299de3cfa2cSIntel char pool_name[MAX_NAME_LEN]; 300de3cfa2cSIntel 301*d9a42a69SThomas Monjalon if (rte_eth_dev_count_avail() == 0) 302de3cfa2cSIntel rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n"); 303de3cfa2cSIntel 304de3cfa2cSIntel /* load configuration profile */ 305de3cfa2cSIntel if (app_load_cfg_profile(cfg_profile) != 0) 306de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Invalid configuration profile\n"); 307de3cfa2cSIntel 308de3cfa2cSIntel /* Initialize each active flow */ 309de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 310de3cfa2cSIntel uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); 311de3cfa2cSIntel struct rte_ring *ring; 312de3cfa2cSIntel 3136f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); 314de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 315de3cfa2cSIntel if (ring == NULL) 316de3cfa2cSIntel qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 317de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 318de3cfa2cSIntel else 319de3cfa2cSIntel qos_conf[i].rx_ring = ring; 320de3cfa2cSIntel 3216f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core); 322de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 323de3cfa2cSIntel if (ring == NULL) 324de3cfa2cSIntel qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 325de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 326de3cfa2cSIntel else 327de3cfa2cSIntel qos_conf[i].tx_ring = ring; 328de3cfa2cSIntel 329de3cfa2cSIntel 330de3cfa2cSIntel /* create the mbuf pools for each RX Port */ 3316f41fe75SStephen Hemminger snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i); 332ea0c20eaSOlivier Matz qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name, 333824cb29cSKonstantin Ananyev mp_size, burst_conf.rx_burst * 4, 0, 334824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, 335ea0c20eaSOlivier Matz rte_eth_dev_socket_id(qos_conf[i].rx_port)); 336de3cfa2cSIntel if (qos_conf[i].mbuf_pool == NULL) 337de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i); 338de3cfa2cSIntel 339de3cfa2cSIntel app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); 340de3cfa2cSIntel app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); 341de3cfa2cSIntel 342cfd5c971SIntel qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket); 343de3cfa2cSIntel } 344de3cfa2cSIntel 345de3cfa2cSIntel RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n", 346de3cfa2cSIntel rte_get_timer_hz()); 347de3cfa2cSIntel 348de3cfa2cSIntel RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," 349e93b24a3SIntel "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size, 350de3cfa2cSIntel ring_conf.tx_size); 351de3cfa2cSIntel 352de3cfa2cSIntel RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n" 353de3cfa2cSIntel " Worker read/QoS enqueue = %hu,\n" 354de3cfa2cSIntel " QoS dequeue = %hu, Worker write = %hu\n", 355de3cfa2cSIntel burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst, 356de3cfa2cSIntel burst_conf.qos_dequeue, burst_conf.tx_burst); 357de3cfa2cSIntel 358de3cfa2cSIntel RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," 359de3cfa2cSIntel "TX (p = %hhu, h = %hhu, w = %hhu)\n", 360de3cfa2cSIntel rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh, 361de3cfa2cSIntel tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh); 362de3cfa2cSIntel 363de3cfa2cSIntel return 0; 364de3cfa2cSIntel } 365