1de3cfa2cSIntel /*- 2de3cfa2cSIntel * BSD LICENSE 3de3cfa2cSIntel * 4de3cfa2cSIntel * Copyright(c) 2010-2013 Intel Corporation. All rights reserved. 5de3cfa2cSIntel * All rights reserved. 6de3cfa2cSIntel * 7de3cfa2cSIntel * Redistribution and use in source and binary forms, with or without 8de3cfa2cSIntel * modification, are permitted provided that the following conditions 9de3cfa2cSIntel * are met: 10de3cfa2cSIntel * 11de3cfa2cSIntel * * Redistributions of source code must retain the above copyright 12de3cfa2cSIntel * notice, this list of conditions and the following disclaimer. 13de3cfa2cSIntel * * Redistributions in binary form must reproduce the above copyright 14de3cfa2cSIntel * notice, this list of conditions and the following disclaimer in 15de3cfa2cSIntel * the documentation and/or other materials provided with the 16de3cfa2cSIntel * distribution. 17de3cfa2cSIntel * * Neither the name of Intel Corporation nor the names of its 18de3cfa2cSIntel * contributors may be used to endorse or promote products derived 19de3cfa2cSIntel * from this software without specific prior written permission. 20de3cfa2cSIntel * 21de3cfa2cSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22de3cfa2cSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23de3cfa2cSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24de3cfa2cSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25de3cfa2cSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26de3cfa2cSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27de3cfa2cSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28de3cfa2cSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29de3cfa2cSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30de3cfa2cSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31de3cfa2cSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32de3cfa2cSIntel * 33de3cfa2cSIntel */ 34de3cfa2cSIntel 35de3cfa2cSIntel #include <stdint.h> 36de3cfa2cSIntel #include <memory.h> 37de3cfa2cSIntel 38de3cfa2cSIntel #include <rte_log.h> 39de3cfa2cSIntel #include <rte_mbuf.h> 40de3cfa2cSIntel #include <rte_debug.h> 41de3cfa2cSIntel #include <rte_ethdev.h> 42de3cfa2cSIntel #include <rte_mempool.h> 43de3cfa2cSIntel #include <rte_sched.h> 44de3cfa2cSIntel #include <rte_cycles.h> 45de3cfa2cSIntel #include <rte_string_fns.h> 46de3cfa2cSIntel 47de3cfa2cSIntel #include "main.h" 48de3cfa2cSIntel #include "cfg_file.h" 49de3cfa2cSIntel 50de3cfa2cSIntel uint32_t app_numa_mask = 0; 51de3cfa2cSIntel static uint32_t app_inited_port_mask = 0; 52de3cfa2cSIntel 53de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 54de3cfa2cSIntel 55de3cfa2cSIntel #define MAX_NAME_LEN 32 56de3cfa2cSIntel 57de3cfa2cSIntel struct ring_conf ring_conf = { 58de3cfa2cSIntel .rx_size = APP_RX_DESC_DEFAULT, 59de3cfa2cSIntel .ring_size = APP_RING_SIZE, 60de3cfa2cSIntel .tx_size = APP_TX_DESC_DEFAULT, 61de3cfa2cSIntel }; 62de3cfa2cSIntel 63de3cfa2cSIntel struct burst_conf burst_conf = { 64de3cfa2cSIntel .rx_burst = MAX_PKT_RX_BURST, 65de3cfa2cSIntel .ring_burst = PKT_ENQUEUE, 66de3cfa2cSIntel .qos_dequeue = PKT_DEQUEUE, 67de3cfa2cSIntel .tx_burst = MAX_PKT_TX_BURST, 68de3cfa2cSIntel }; 69de3cfa2cSIntel 70de3cfa2cSIntel struct ring_thresh rx_thresh = { 71de3cfa2cSIntel .pthresh = RX_PTHRESH, 72de3cfa2cSIntel .hthresh = RX_HTHRESH, 73de3cfa2cSIntel .wthresh = RX_WTHRESH, 74de3cfa2cSIntel }; 75de3cfa2cSIntel 76de3cfa2cSIntel struct ring_thresh tx_thresh = { 77de3cfa2cSIntel .pthresh = TX_PTHRESH, 78de3cfa2cSIntel .hthresh = TX_HTHRESH, 79de3cfa2cSIntel .wthresh = TX_WTHRESH, 80de3cfa2cSIntel }; 81de3cfa2cSIntel 82de3cfa2cSIntel uint32_t nb_pfc; 83de3cfa2cSIntel const char *cfg_profile = NULL; 84de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS]; 85de3cfa2cSIntel 86de3cfa2cSIntel static const struct rte_eth_conf port_conf = { 87de3cfa2cSIntel .rxmode = { 88de3cfa2cSIntel .max_rx_pkt_len = ETHER_MAX_LEN, 89de3cfa2cSIntel .split_hdr_size = 0, 90de3cfa2cSIntel .header_split = 0, /**< Header Split disabled */ 91de3cfa2cSIntel .hw_ip_checksum = 0, /**< IP checksum offload disabled */ 92de3cfa2cSIntel .hw_vlan_filter = 0, /**< VLAN filtering disabled */ 93de3cfa2cSIntel .jumbo_frame = 0, /**< Jumbo Frame Support disabled */ 94de3cfa2cSIntel .hw_strip_crc = 0, /**< CRC stripped by hardware */ 95de3cfa2cSIntel }, 96de3cfa2cSIntel .txmode = { 97de3cfa2cSIntel .mq_mode = ETH_DCB_NONE, 98de3cfa2cSIntel }, 99de3cfa2cSIntel }; 100de3cfa2cSIntel 101de3cfa2cSIntel static int 102de3cfa2cSIntel app_init_port(uint8_t portid, struct rte_mempool *mp) 103de3cfa2cSIntel { 104de3cfa2cSIntel int ret; 105de3cfa2cSIntel struct rte_eth_link link; 106de3cfa2cSIntel struct rte_eth_rxconf rx_conf; 107de3cfa2cSIntel struct rte_eth_txconf tx_conf; 108de3cfa2cSIntel 109de3cfa2cSIntel /* check if port already initialized (multistream configuration) */ 110de3cfa2cSIntel if (app_inited_port_mask & (1u << portid)) 111de3cfa2cSIntel return 0; 112de3cfa2cSIntel 113de3cfa2cSIntel rx_conf.rx_thresh.pthresh = rx_thresh.pthresh; 114de3cfa2cSIntel rx_conf.rx_thresh.hthresh = rx_thresh.hthresh; 115de3cfa2cSIntel rx_conf.rx_thresh.wthresh = rx_thresh.wthresh; 116de3cfa2cSIntel rx_conf.rx_free_thresh = 32; 117de3cfa2cSIntel rx_conf.rx_drop_en = 0; 118de3cfa2cSIntel 119de3cfa2cSIntel tx_conf.tx_thresh.pthresh = tx_thresh.pthresh; 120de3cfa2cSIntel tx_conf.tx_thresh.hthresh = tx_thresh.hthresh; 121de3cfa2cSIntel tx_conf.tx_thresh.wthresh = tx_thresh.wthresh; 122de3cfa2cSIntel tx_conf.tx_free_thresh = 0; 123de3cfa2cSIntel tx_conf.tx_rs_thresh = 0; 124de3cfa2cSIntel tx_conf.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS; 125de3cfa2cSIntel 126de3cfa2cSIntel /* init port */ 127de3cfa2cSIntel RTE_LOG(INFO, APP, "Initializing port %hu... ", portid); 128de3cfa2cSIntel fflush(stdout); 129de3cfa2cSIntel ret = rte_eth_dev_configure(portid, 1, 1, &port_conf); 130de3cfa2cSIntel if (ret < 0) 131de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%hu\n", 132de3cfa2cSIntel ret, portid); 133de3cfa2cSIntel 134de3cfa2cSIntel /* init one RX queue */ 135de3cfa2cSIntel fflush(stdout); 136de3cfa2cSIntel ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size, 137de3cfa2cSIntel rte_eth_dev_socket_id(portid), &rx_conf, mp); 138de3cfa2cSIntel if (ret < 0) 139de3cfa2cSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, port=%hu\n", 140de3cfa2cSIntel ret, portid); 141de3cfa2cSIntel 142de3cfa2cSIntel /* init one TX queue */ 143de3cfa2cSIntel fflush(stdout); 144de3cfa2cSIntel ret = rte_eth_tx_queue_setup(portid, 0, 145de3cfa2cSIntel (uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf); 146de3cfa2cSIntel if (ret < 0) 147de3cfa2cSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, " 148de3cfa2cSIntel "port=%hu queue=%d\n", 149de3cfa2cSIntel ret, portid, 0); 150de3cfa2cSIntel 151de3cfa2cSIntel /* Start device */ 152de3cfa2cSIntel ret = rte_eth_dev_start(portid); 153de3cfa2cSIntel if (ret < 0) 154de3cfa2cSIntel rte_exit(EXIT_FAILURE, "rte_pmd_port_start: err=%d, port=%hu\n", 155de3cfa2cSIntel ret, portid); 156de3cfa2cSIntel 157de3cfa2cSIntel printf("done: "); 158de3cfa2cSIntel 159de3cfa2cSIntel /* get link status */ 160de3cfa2cSIntel rte_eth_link_get(portid, &link); 161de3cfa2cSIntel if (link.link_status) { 162de3cfa2cSIntel printf(" Link Up - speed %u Mbps - %s\n", 163de3cfa2cSIntel (uint32_t) link.link_speed, 164de3cfa2cSIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 165de3cfa2cSIntel ("full-duplex") : ("half-duplex\n")); 166de3cfa2cSIntel } else { 167de3cfa2cSIntel printf(" Link Down\n"); 168de3cfa2cSIntel } 169de3cfa2cSIntel rte_eth_promiscuous_enable(portid); 170de3cfa2cSIntel 171de3cfa2cSIntel /* mark port as initialized */ 172de3cfa2cSIntel app_inited_port_mask |= 1u << portid; 173de3cfa2cSIntel 174de3cfa2cSIntel return 0; 175de3cfa2cSIntel } 176de3cfa2cSIntel 177de3cfa2cSIntel static struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { 178de3cfa2cSIntel { 179de3cfa2cSIntel .tb_rate = 1250000000, 180de3cfa2cSIntel .tb_size = 1000000, 181de3cfa2cSIntel 182de3cfa2cSIntel .tc_rate = {1250000000, 1250000000, 1250000000, 1250000000}, 183de3cfa2cSIntel .tc_period = 10, 184de3cfa2cSIntel #ifdef RTE_SCHED_SUBPORT_TC_OV 185de3cfa2cSIntel .tc_ov_period = 10, 186de3cfa2cSIntel #endif 187de3cfa2cSIntel }, 188de3cfa2cSIntel }; 189de3cfa2cSIntel 190de3cfa2cSIntel static struct rte_sched_pipe_params pipe_profiles[RTE_SCHED_PIPE_PROFILES_PER_PORT] = { 191de3cfa2cSIntel { /* Profile #0 */ 192de3cfa2cSIntel .tb_rate = 305175, 193de3cfa2cSIntel .tb_size = 1000000, 194de3cfa2cSIntel 195de3cfa2cSIntel .tc_rate = {305175, 305175, 305175, 305175}, 196de3cfa2cSIntel .tc_period = 40, 197de3cfa2cSIntel #ifdef RTE_SCHED_SUBPORT_TC_OV 198de3cfa2cSIntel .tc_ov_weight = {1, 1, 1, 1}, 199de3cfa2cSIntel #endif 200de3cfa2cSIntel 201de3cfa2cSIntel .wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 202de3cfa2cSIntel }, 203de3cfa2cSIntel }; 204de3cfa2cSIntel 205de3cfa2cSIntel struct rte_sched_port_params port_params = { 206de3cfa2cSIntel .name = "port_0", 207de3cfa2cSIntel .socket = 0, /* computed */ 208de3cfa2cSIntel .rate = 0, /* computed */ 209*a91c3cadSIntel .mtu = 6 + 6 + 4 + 4 + 2 + 1500, 210de3cfa2cSIntel .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT, 211de3cfa2cSIntel .n_subports_per_port = 1, 212de3cfa2cSIntel .n_pipes_per_subport = 4096, 213de3cfa2cSIntel .qsize = {64, 64, 64, 64}, 214de3cfa2cSIntel .pipe_profiles = pipe_profiles, 215de3cfa2cSIntel .n_pipe_profiles = 1, 216de3cfa2cSIntel 217de3cfa2cSIntel #ifdef RTE_SCHED_RED 218de3cfa2cSIntel .red_params = { 219de3cfa2cSIntel /* Traffic Class 0 Colors Green / Yellow / Red */ 220de3cfa2cSIntel [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 221de3cfa2cSIntel [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 222de3cfa2cSIntel [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 223de3cfa2cSIntel 224de3cfa2cSIntel /* Traffic Class 1 - Colors Green / Yellow / Red */ 225de3cfa2cSIntel [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 226de3cfa2cSIntel [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 227de3cfa2cSIntel [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 228de3cfa2cSIntel 229de3cfa2cSIntel /* Traffic Class 2 - Colors Green / Yellow / Red */ 230de3cfa2cSIntel [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 231de3cfa2cSIntel [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 232de3cfa2cSIntel [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 233de3cfa2cSIntel 234de3cfa2cSIntel /* Traffic Class 3 - Colors Green / Yellow / Red */ 235de3cfa2cSIntel [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 236de3cfa2cSIntel [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, 237de3cfa2cSIntel [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9} 238de3cfa2cSIntel } 239de3cfa2cSIntel #endif /* RTE_SCHED_RED */ 240de3cfa2cSIntel }; 241de3cfa2cSIntel 242de3cfa2cSIntel static struct rte_sched_port * 243de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid) 244de3cfa2cSIntel { 245de3cfa2cSIntel static char port_name[32]; /* static as referenced from global port_params*/ 246de3cfa2cSIntel struct rte_eth_link link; 247de3cfa2cSIntel struct rte_sched_port *port = NULL; 248de3cfa2cSIntel uint32_t pipe, subport; 249de3cfa2cSIntel int err; 250de3cfa2cSIntel 251de3cfa2cSIntel rte_eth_link_get((uint8_t)portid, &link); 252de3cfa2cSIntel 253de3cfa2cSIntel port_params.socket = socketid; 254de3cfa2cSIntel port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8; 255de3cfa2cSIntel rte_snprintf(port_name, sizeof(port_name), "port_%d", portid); 256de3cfa2cSIntel port_params.name = port_name; 257de3cfa2cSIntel 258de3cfa2cSIntel port = rte_sched_port_config(&port_params); 259de3cfa2cSIntel if (port == NULL){ 260de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched port\n"); 261de3cfa2cSIntel } 262de3cfa2cSIntel 263de3cfa2cSIntel for (subport = 0; subport < port_params.n_subports_per_port; subport ++) { 264de3cfa2cSIntel err = rte_sched_subport_config(port, subport, &subport_params[subport]); 265de3cfa2cSIntel if (err) { 266de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched subport %u, err=%d\n", 267de3cfa2cSIntel subport, err); 268de3cfa2cSIntel } 269de3cfa2cSIntel 270de3cfa2cSIntel for (pipe = 0; pipe < port_params.n_pipes_per_subport; pipe ++) { 271de3cfa2cSIntel if (app_pipe_to_profile[subport][pipe] != -1) { 272de3cfa2cSIntel err = rte_sched_pipe_config(port, subport, pipe, 273de3cfa2cSIntel app_pipe_to_profile[subport][pipe]); 274de3cfa2cSIntel if (err) { 275de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u " 276de3cfa2cSIntel "for profile %d, err=%d\n", pipe, 277de3cfa2cSIntel app_pipe_to_profile[subport][pipe], err); 278de3cfa2cSIntel } 279de3cfa2cSIntel } 280de3cfa2cSIntel } 281de3cfa2cSIntel } 282de3cfa2cSIntel 283de3cfa2cSIntel return port; 284de3cfa2cSIntel } 285de3cfa2cSIntel 286de3cfa2cSIntel static int 287de3cfa2cSIntel app_load_cfg_profile(const char *profile) 288de3cfa2cSIntel { 289de3cfa2cSIntel if (profile == NULL) 290de3cfa2cSIntel return 0; 291de3cfa2cSIntel 292de3cfa2cSIntel struct cfg_file *cfg_file = cfg_load(profile, 0); 293de3cfa2cSIntel if (cfg_file == NULL) 294de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile); 295de3cfa2cSIntel 296de3cfa2cSIntel cfg_load_port(cfg_file, &port_params); 297de3cfa2cSIntel cfg_load_subport(cfg_file, subport_params); 298de3cfa2cSIntel cfg_load_pipe(cfg_file, pipe_profiles); 299de3cfa2cSIntel 300de3cfa2cSIntel cfg_close(cfg_file); 301de3cfa2cSIntel 302de3cfa2cSIntel return 0; 303de3cfa2cSIntel } 304de3cfa2cSIntel 305de3cfa2cSIntel int app_init(void) 306de3cfa2cSIntel { 307de3cfa2cSIntel uint32_t i; 308de3cfa2cSIntel char ring_name[MAX_NAME_LEN]; 309de3cfa2cSIntel char pool_name[MAX_NAME_LEN]; 310de3cfa2cSIntel 311de3cfa2cSIntel /* init driver(s) */ 312de3cfa2cSIntel if (rte_pmd_init_all() < 0) 313de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init PMD\n"); 314de3cfa2cSIntel 315de3cfa2cSIntel if (rte_eal_pci_probe() < 0) 316de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot probe PCI\n"); 317de3cfa2cSIntel 318de3cfa2cSIntel if (rte_eth_dev_count() == 0) 319de3cfa2cSIntel rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n"); 320de3cfa2cSIntel 321de3cfa2cSIntel /* load configuration profile */ 322de3cfa2cSIntel if (app_load_cfg_profile(cfg_profile) != 0) 323de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Invalid configuration profile\n"); 324de3cfa2cSIntel 325de3cfa2cSIntel /* Initialize each active flow */ 326de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 327de3cfa2cSIntel uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); 328de3cfa2cSIntel struct rte_ring *ring; 329de3cfa2cSIntel 330de3cfa2cSIntel rte_snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); 331de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 332de3cfa2cSIntel if (ring == NULL) 333de3cfa2cSIntel qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 334de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 335de3cfa2cSIntel else 336de3cfa2cSIntel qos_conf[i].rx_ring = ring; 337de3cfa2cSIntel 338de3cfa2cSIntel rte_snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core); 339de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 340de3cfa2cSIntel if (ring == NULL) 341de3cfa2cSIntel qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 342de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 343de3cfa2cSIntel else 344de3cfa2cSIntel qos_conf[i].tx_ring = ring; 345de3cfa2cSIntel 346de3cfa2cSIntel 347de3cfa2cSIntel /* create the mbuf pools for each RX Port */ 348de3cfa2cSIntel rte_snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i); 349de3cfa2cSIntel qos_conf[i].mbuf_pool = rte_mempool_create(pool_name, NB_MBUF, MBUF_SIZE, 350de3cfa2cSIntel burst_conf.rx_burst * 4, 351de3cfa2cSIntel sizeof(struct rte_pktmbuf_pool_private), 352de3cfa2cSIntel rte_pktmbuf_pool_init, NULL, 353de3cfa2cSIntel rte_pktmbuf_init, NULL, 354de3cfa2cSIntel rte_eth_dev_socket_id(qos_conf[i].rx_port), 355de3cfa2cSIntel 0); 356de3cfa2cSIntel if (qos_conf[i].mbuf_pool == NULL) 357de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i); 358de3cfa2cSIntel 359de3cfa2cSIntel //printf("MP = %d\n", rte_mempool_count(qos_conf[i].app_pktmbuf_pool)); 360de3cfa2cSIntel 361de3cfa2cSIntel app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); 362de3cfa2cSIntel app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); 363de3cfa2cSIntel 364de3cfa2cSIntel qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].rx_port, socket); 365de3cfa2cSIntel } 366de3cfa2cSIntel 367de3cfa2cSIntel RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n", 368de3cfa2cSIntel rte_get_timer_hz()); 369de3cfa2cSIntel 370de3cfa2cSIntel RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," 371de3cfa2cSIntel "NIC TX = %u\n", ring_conf.rx_size, NB_MBUF, ring_conf.ring_size, 372de3cfa2cSIntel ring_conf.tx_size); 373de3cfa2cSIntel 374de3cfa2cSIntel RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n" 375de3cfa2cSIntel " Worker read/QoS enqueue = %hu,\n" 376de3cfa2cSIntel " QoS dequeue = %hu, Worker write = %hu\n", 377de3cfa2cSIntel burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst, 378de3cfa2cSIntel burst_conf.qos_dequeue, burst_conf.tx_burst); 379de3cfa2cSIntel 380de3cfa2cSIntel RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," 381de3cfa2cSIntel "TX (p = %hhu, h = %hhu, w = %hhu)\n", 382de3cfa2cSIntel rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh, 383de3cfa2cSIntel tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh); 384de3cfa2cSIntel 385de3cfa2cSIntel return 0; 386de3cfa2cSIntel } 387