13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #include <stdint.h> 672b452c5SDmitry Kozlyuk #include <stdlib.h> 7de3cfa2cSIntel #include <memory.h> 8de3cfa2cSIntel 9de3cfa2cSIntel #include <rte_log.h> 10de3cfa2cSIntel #include <rte_mbuf.h> 11de3cfa2cSIntel #include <rte_debug.h> 12de3cfa2cSIntel #include <rte_ethdev.h> 13de3cfa2cSIntel #include <rte_mempool.h> 14de3cfa2cSIntel #include <rte_sched.h> 15de3cfa2cSIntel #include <rte_cycles.h> 16de3cfa2cSIntel #include <rte_string_fns.h> 17db935d01SMichal Jastrzebski #include <rte_cfgfile.h> 18de3cfa2cSIntel 19de3cfa2cSIntel #include "main.h" 20de3cfa2cSIntel #include "cfg_file.h" 21de3cfa2cSIntel 22de3cfa2cSIntel uint32_t app_numa_mask = 0; 23de3cfa2cSIntel static uint32_t app_inited_port_mask = 0; 24de3cfa2cSIntel 25de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 26de3cfa2cSIntel 27de3cfa2cSIntel #define MAX_NAME_LEN 32 28de3cfa2cSIntel 29de3cfa2cSIntel struct ring_conf ring_conf = { 30de3cfa2cSIntel .rx_size = APP_RX_DESC_DEFAULT, 31de3cfa2cSIntel .ring_size = APP_RING_SIZE, 32de3cfa2cSIntel .tx_size = APP_TX_DESC_DEFAULT, 33de3cfa2cSIntel }; 34de3cfa2cSIntel 35de3cfa2cSIntel struct burst_conf burst_conf = { 36de3cfa2cSIntel .rx_burst = MAX_PKT_RX_BURST, 37de3cfa2cSIntel .ring_burst = PKT_ENQUEUE, 38de3cfa2cSIntel .qos_dequeue = PKT_DEQUEUE, 39de3cfa2cSIntel .tx_burst = MAX_PKT_TX_BURST, 40de3cfa2cSIntel }; 41de3cfa2cSIntel 42de3cfa2cSIntel struct ring_thresh rx_thresh = { 43de3cfa2cSIntel .pthresh = RX_PTHRESH, 44de3cfa2cSIntel .hthresh = RX_HTHRESH, 45de3cfa2cSIntel .wthresh = RX_WTHRESH, 46de3cfa2cSIntel }; 47de3cfa2cSIntel 48de3cfa2cSIntel struct ring_thresh tx_thresh = { 49de3cfa2cSIntel .pthresh = TX_PTHRESH, 50de3cfa2cSIntel .hthresh = TX_HTHRESH, 51de3cfa2cSIntel .wthresh = TX_WTHRESH, 52de3cfa2cSIntel }; 53de3cfa2cSIntel 54de3cfa2cSIntel uint32_t nb_pfc; 55de3cfa2cSIntel const char *cfg_profile = NULL; 56e93b24a3SIntel int mp_size = NB_MBUF; 57de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS]; 58de3cfa2cSIntel 59e2ef4628SShahaf Shuler static struct rte_eth_conf port_conf = { 60de3cfa2cSIntel .txmode = { 61295968d1SFerruh Yigit .mq_mode = RTE_ETH_MQ_TX_NONE, 62de3cfa2cSIntel }, 63de3cfa2cSIntel }; 64de3cfa2cSIntel 65de3cfa2cSIntel static int 66f8244c63SZhiyong Yang app_init_port(uint16_t portid, struct rte_mempool *mp) 67de3cfa2cSIntel { 68de3cfa2cSIntel int ret; 69de3cfa2cSIntel struct rte_eth_link link; 70e2ef4628SShahaf Shuler struct rte_eth_dev_info dev_info; 71de3cfa2cSIntel struct rte_eth_rxconf rx_conf; 72de3cfa2cSIntel struct rte_eth_txconf tx_conf; 7360efb44fSRoman Zhukov uint16_t rx_size; 7460efb44fSRoman Zhukov uint16_t tx_size; 75e2ef4628SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf; 76db4e8135SIvan Dyukov char link_status_text[RTE_ETH_LINK_MAX_STR_LEN]; 77de3cfa2cSIntel 78de3cfa2cSIntel /* check if port already initialized (multistream configuration) */ 79de3cfa2cSIntel if (app_inited_port_mask & (1u << portid)) 80de3cfa2cSIntel return 0; 81de3cfa2cSIntel 82de3cfa2cSIntel rx_conf.rx_thresh.pthresh = rx_thresh.pthresh; 83de3cfa2cSIntel rx_conf.rx_thresh.hthresh = rx_thresh.hthresh; 84de3cfa2cSIntel rx_conf.rx_thresh.wthresh = rx_thresh.wthresh; 85de3cfa2cSIntel rx_conf.rx_free_thresh = 32; 86de3cfa2cSIntel rx_conf.rx_drop_en = 0; 8796b5077cSJasvinder Singh rx_conf.rx_deferred_start = 0; 88de3cfa2cSIntel 89de3cfa2cSIntel tx_conf.tx_thresh.pthresh = tx_thresh.pthresh; 90de3cfa2cSIntel tx_conf.tx_thresh.hthresh = tx_thresh.hthresh; 91de3cfa2cSIntel tx_conf.tx_thresh.wthresh = tx_thresh.wthresh; 92de3cfa2cSIntel tx_conf.tx_free_thresh = 0; 93de3cfa2cSIntel tx_conf.tx_rs_thresh = 0; 9496b5077cSJasvinder Singh tx_conf.tx_deferred_start = 0; 95de3cfa2cSIntel 96de3cfa2cSIntel /* init port */ 97f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "Initializing port %"PRIu16"... ", portid); 98de3cfa2cSIntel fflush(stdout); 9945069992SIvan Ilchenko 10045069992SIvan Ilchenko ret = rte_eth_dev_info_get(portid, &dev_info); 10145069992SIvan Ilchenko if (ret != 0) 10245069992SIvan Ilchenko rte_exit(EXIT_FAILURE, 10345069992SIvan Ilchenko "Error during getting device (port %u) info: %s\n", 10445069992SIvan Ilchenko portid, strerror(-ret)); 10545069992SIvan Ilchenko 106295968d1SFerruh Yigit if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) 107e2ef4628SShahaf Shuler local_port_conf.txmode.offloads |= 108295968d1SFerruh Yigit RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 109e2ef4628SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf); 110de3cfa2cSIntel if (ret < 0) 111f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 112f8244c63SZhiyong Yang "Cannot configure device: err=%d, port=%u\n", 113f8244c63SZhiyong Yang ret, portid); 114de3cfa2cSIntel 11560efb44fSRoman Zhukov rx_size = ring_conf.rx_size; 11660efb44fSRoman Zhukov tx_size = ring_conf.tx_size; 11760efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &rx_size, &tx_size); 11860efb44fSRoman Zhukov if (ret < 0) 119f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 120f8244c63SZhiyong Yang "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n", 121f8244c63SZhiyong Yang ret, portid); 12260efb44fSRoman Zhukov ring_conf.rx_size = rx_size; 12360efb44fSRoman Zhukov ring_conf.tx_size = tx_size; 12460efb44fSRoman Zhukov 125de3cfa2cSIntel /* init one RX queue */ 126de3cfa2cSIntel fflush(stdout); 127e2ef4628SShahaf Shuler rx_conf.offloads = local_port_conf.rxmode.offloads; 128de3cfa2cSIntel ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size, 129de3cfa2cSIntel rte_eth_dev_socket_id(portid), &rx_conf, mp); 130de3cfa2cSIntel if (ret < 0) 131f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 132f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u\n", 133f8244c63SZhiyong Yang ret, portid); 134de3cfa2cSIntel 135de3cfa2cSIntel /* init one TX queue */ 136de3cfa2cSIntel fflush(stdout); 137e2ef4628SShahaf Shuler tx_conf.offloads = local_port_conf.txmode.offloads; 138de3cfa2cSIntel ret = rte_eth_tx_queue_setup(portid, 0, 139de3cfa2cSIntel (uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf); 140de3cfa2cSIntel if (ret < 0) 141f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 142f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n", 143f8244c63SZhiyong Yang ret, portid, 0); 144de3cfa2cSIntel 145de3cfa2cSIntel /* Start device */ 146de3cfa2cSIntel ret = rte_eth_dev_start(portid); 147de3cfa2cSIntel if (ret < 0) 148f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 149f8244c63SZhiyong Yang "rte_pmd_port_start: err=%d, port=%u\n", 150f8244c63SZhiyong Yang ret, portid); 151de3cfa2cSIntel 152de3cfa2cSIntel printf("done: "); 153de3cfa2cSIntel 154de3cfa2cSIntel /* get link status */ 15522e5c73bSIgor Romanov ret = rte_eth_link_get(portid, &link); 15622e5c73bSIgor Romanov if (ret < 0) 15722e5c73bSIgor Romanov rte_exit(EXIT_FAILURE, 15822e5c73bSIgor Romanov "rte_eth_link_get: err=%d, port=%u: %s\n", 15922e5c73bSIgor Romanov ret, portid, rte_strerror(-ret)); 16022e5c73bSIgor Romanov 161db4e8135SIvan Dyukov rte_eth_link_to_str(link_status_text, sizeof(link_status_text), &link); 162db4e8135SIvan Dyukov printf("%s\n", link_status_text); 163db4e8135SIvan Dyukov 164f430bbceSIvan Ilchenko ret = rte_eth_promiscuous_enable(portid); 165f430bbceSIvan Ilchenko if (ret != 0) 166f430bbceSIvan Ilchenko rte_exit(EXIT_FAILURE, 167f430bbceSIvan Ilchenko "rte_eth_promiscuous_enable: err=%s, port=%u\n", 168f430bbceSIvan Ilchenko rte_strerror(-ret), portid); 169de3cfa2cSIntel 170de3cfa2cSIntel /* mark port as initialized */ 171de3cfa2cSIntel app_inited_port_mask |= 1u << portid; 172de3cfa2cSIntel 173de3cfa2cSIntel return 0; 174de3cfa2cSIntel } 175de3cfa2cSIntel 176be1e5332SJasvinder Singh static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = { 177de3cfa2cSIntel { /* Profile #0 */ 178de3cfa2cSIntel .tb_rate = 305175, 179de3cfa2cSIntel .tb_size = 1000000, 180de3cfa2cSIntel 181be1e5332SJasvinder Singh .tc_rate = {305175, 305175, 305175, 305175, 305175, 305175, 182be1e5332SJasvinder Singh 305175, 305175, 305175, 305175, 305175, 305175, 305175}, 183de3cfa2cSIntel .tc_period = 40, 184835c5409SIntel .tc_ov_weight = 1, 185de3cfa2cSIntel 186e16b06daSJasvinder Singh .wrr_weights = {1, 1, 1, 1}, 187de3cfa2cSIntel }, 188de3cfa2cSIntel }; 189de3cfa2cSIntel 190802d214dSSavinay Dharmappa static struct rte_sched_subport_profile_params 191802d214dSSavinay Dharmappa subport_profile[MAX_SCHED_SUBPORT_PROFILES] = { 192b0c1628bSJasvinder Singh { 193b0c1628bSJasvinder Singh .tb_rate = 1250000000, 194b0c1628bSJasvinder Singh .tb_size = 1000000, 195b0c1628bSJasvinder Singh .tc_rate = {1250000000, 1250000000, 1250000000, 1250000000, 196b0c1628bSJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000, 1250000000, 197b0c1628bSJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000}, 198b0c1628bSJasvinder Singh .tc_period = 10, 199802d214dSSavinay Dharmappa }, 200802d214dSSavinay Dharmappa }; 201802d214dSSavinay Dharmappa 20206135957SWojciech Liguzinski struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { 20306135957SWojciech Liguzinski { 20406135957SWojciech Liguzinski .n_pipes_per_subport_enabled = 4096, 20506135957SWojciech Liguzinski .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, 20606135957SWojciech Liguzinski .pipe_profiles = pipe_profiles, 20706135957SWojciech Liguzinski .n_pipe_profiles = sizeof(pipe_profiles) / 20806135957SWojciech Liguzinski sizeof(struct rte_sched_pipe_params), 20906135957SWojciech Liguzinski .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, 210a61b3196SMarcin Danilewicz .cman_params = NULL, 211b0c1628bSJasvinder Singh }, 212b0c1628bSJasvinder Singh }; 213b0c1628bSJasvinder Singh 214b0c1628bSJasvinder Singh struct rte_sched_port_params port_params = { 215b0c1628bSJasvinder Singh .name = "port_scheduler_0", 216b0c1628bSJasvinder Singh .socket = 0, /* computed */ 217b0c1628bSJasvinder Singh .rate = 0, /* computed */ 218b0c1628bSJasvinder Singh .mtu = 6 + 6 + 4 + 4 + 2 + 1500, 219b0c1628bSJasvinder Singh .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT, 220b0c1628bSJasvinder Singh .n_subports_per_port = 1, 221802d214dSSavinay Dharmappa .n_subport_profiles = 1, 222802d214dSSavinay Dharmappa .subport_profiles = subport_profile, 223802d214dSSavinay Dharmappa .n_max_subport_profiles = MAX_SCHED_SUBPORT_PROFILES, 224b0c1628bSJasvinder Singh .n_pipes_per_subport = MAX_SCHED_PIPES, 225de3cfa2cSIntel }; 226de3cfa2cSIntel 227de3cfa2cSIntel static struct rte_sched_port * 228de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid) 229de3cfa2cSIntel { 230de3cfa2cSIntel static char port_name[32]; /* static as referenced from global port_params*/ 231de3cfa2cSIntel struct rte_eth_link link; 232de3cfa2cSIntel struct rte_sched_port *port = NULL; 233de3cfa2cSIntel uint32_t pipe, subport; 234de3cfa2cSIntel int err; 235de3cfa2cSIntel 23622e5c73bSIgor Romanov err = rte_eth_link_get(portid, &link); 23722e5c73bSIgor Romanov if (err < 0) 23822e5c73bSIgor Romanov rte_exit(EXIT_FAILURE, 23922e5c73bSIgor Romanov "rte_eth_link_get: err=%d, port=%u: %s\n", 24022e5c73bSIgor Romanov err, portid, rte_strerror(-err)); 241de3cfa2cSIntel 242de3cfa2cSIntel port_params.socket = socketid; 243de3cfa2cSIntel port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8; 2446f41fe75SStephen Hemminger snprintf(port_name, sizeof(port_name), "port_%d", portid); 245de3cfa2cSIntel port_params.name = port_name; 246de3cfa2cSIntel 247de3cfa2cSIntel port = rte_sched_port_config(&port_params); 248de3cfa2cSIntel if (port == NULL){ 249de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched port\n"); 250de3cfa2cSIntel } 251de3cfa2cSIntel 252de3cfa2cSIntel for (subport = 0; subport < port_params.n_subports_per_port; subport ++) { 253ac6fcb84SSavinay Dharmappa err = rte_sched_subport_config(port, subport, 254802d214dSSavinay Dharmappa &subport_params[subport], 255802d214dSSavinay Dharmappa 0); 256de3cfa2cSIntel if (err) { 257802d214dSSavinay Dharmappa rte_exit(EXIT_FAILURE, "Unable to config sched " 258802d214dSSavinay Dharmappa "subport %u, err=%d\n", subport, err); 259de3cfa2cSIntel } 260de3cfa2cSIntel 261b0c1628bSJasvinder Singh uint32_t n_pipes_per_subport = 262b0c1628bSJasvinder Singh subport_params[subport].n_pipes_per_subport_enabled; 263b0c1628bSJasvinder Singh 264b0c1628bSJasvinder Singh for (pipe = 0; pipe < n_pipes_per_subport; pipe++) { 265de3cfa2cSIntel if (app_pipe_to_profile[subport][pipe] != -1) { 266de3cfa2cSIntel err = rte_sched_pipe_config(port, subport, pipe, 267de3cfa2cSIntel app_pipe_to_profile[subport][pipe]); 268de3cfa2cSIntel if (err) { 269de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u " 270de3cfa2cSIntel "for profile %d, err=%d\n", pipe, 271de3cfa2cSIntel app_pipe_to_profile[subport][pipe], err); 272de3cfa2cSIntel } 273de3cfa2cSIntel } 274de3cfa2cSIntel } 275de3cfa2cSIntel } 276de3cfa2cSIntel 277de3cfa2cSIntel return port; 278de3cfa2cSIntel } 279de3cfa2cSIntel 280de3cfa2cSIntel static int 281de3cfa2cSIntel app_load_cfg_profile(const char *profile) 282de3cfa2cSIntel { 283*92e9fe0dSMegha Ajmera int ret = 0; 284de3cfa2cSIntel if (profile == NULL) 285de3cfa2cSIntel return 0; 286db935d01SMichal Jastrzebski struct rte_cfgfile *file = rte_cfgfile_load(profile, 0); 287db935d01SMichal Jastrzebski if (file == NULL) 288de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile); 289de3cfa2cSIntel 290*92e9fe0dSMegha Ajmera ret = cfg_load_port(file, &port_params); 291*92e9fe0dSMegha Ajmera if (ret) 292*92e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 293de3cfa2cSIntel 294*92e9fe0dSMegha Ajmera ret = cfg_load_subport(file, subport_params); 295*92e9fe0dSMegha Ajmera if (ret) 296*92e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 297*92e9fe0dSMegha Ajmera 298*92e9fe0dSMegha Ajmera ret = cfg_load_subport_profile(file, subport_profile); 299*92e9fe0dSMegha Ajmera if (ret) 300*92e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 301*92e9fe0dSMegha Ajmera 302*92e9fe0dSMegha Ajmera ret = cfg_load_pipe(file, pipe_profiles); 303*92e9fe0dSMegha Ajmera if (ret) 304*92e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 305*92e9fe0dSMegha Ajmera 306*92e9fe0dSMegha Ajmera _app_load_cfg_profile_error_return: 307db935d01SMichal Jastrzebski rte_cfgfile_close(file); 308de3cfa2cSIntel 309*92e9fe0dSMegha Ajmera return ret; 310de3cfa2cSIntel } 311de3cfa2cSIntel 312de3cfa2cSIntel int app_init(void) 313de3cfa2cSIntel { 314de3cfa2cSIntel uint32_t i; 315de3cfa2cSIntel char ring_name[MAX_NAME_LEN]; 316de3cfa2cSIntel char pool_name[MAX_NAME_LEN]; 317de3cfa2cSIntel 318d9a42a69SThomas Monjalon if (rte_eth_dev_count_avail() == 0) 319de3cfa2cSIntel rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n"); 320de3cfa2cSIntel 321de3cfa2cSIntel /* load configuration profile */ 322de3cfa2cSIntel if (app_load_cfg_profile(cfg_profile) != 0) 323de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Invalid configuration profile\n"); 324de3cfa2cSIntel 325de3cfa2cSIntel /* Initialize each active flow */ 326de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 327de3cfa2cSIntel uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); 328de3cfa2cSIntel struct rte_ring *ring; 329de3cfa2cSIntel 3306f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); 331de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 332de3cfa2cSIntel if (ring == NULL) 333de3cfa2cSIntel qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 334de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 335de3cfa2cSIntel else 336de3cfa2cSIntel qos_conf[i].rx_ring = ring; 337de3cfa2cSIntel 3386f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core); 339de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 340de3cfa2cSIntel if (ring == NULL) 341de3cfa2cSIntel qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 342de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 343de3cfa2cSIntel else 344de3cfa2cSIntel qos_conf[i].tx_ring = ring; 345de3cfa2cSIntel 346de3cfa2cSIntel 347de3cfa2cSIntel /* create the mbuf pools for each RX Port */ 3486f41fe75SStephen Hemminger snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i); 349ea0c20eaSOlivier Matz qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name, 350824cb29cSKonstantin Ananyev mp_size, burst_conf.rx_burst * 4, 0, 351824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, 352ea0c20eaSOlivier Matz rte_eth_dev_socket_id(qos_conf[i].rx_port)); 353de3cfa2cSIntel if (qos_conf[i].mbuf_pool == NULL) 354de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i); 355de3cfa2cSIntel 356de3cfa2cSIntel app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); 357de3cfa2cSIntel app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); 358de3cfa2cSIntel 359cfd5c971SIntel qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket); 360de3cfa2cSIntel } 361de3cfa2cSIntel 362de3cfa2cSIntel RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n", 363de3cfa2cSIntel rte_get_timer_hz()); 364de3cfa2cSIntel 365de3cfa2cSIntel RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," 366e93b24a3SIntel "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size, 367de3cfa2cSIntel ring_conf.tx_size); 368de3cfa2cSIntel 369de3cfa2cSIntel RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n" 370de3cfa2cSIntel " Worker read/QoS enqueue = %hu,\n" 371de3cfa2cSIntel " QoS dequeue = %hu, Worker write = %hu\n", 372de3cfa2cSIntel burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst, 373de3cfa2cSIntel burst_conf.qos_dequeue, burst_conf.tx_burst); 374de3cfa2cSIntel 375de3cfa2cSIntel RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," 376de3cfa2cSIntel "TX (p = %hhu, h = %hhu, w = %hhu)\n", 377de3cfa2cSIntel rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh, 378de3cfa2cSIntel tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh); 379de3cfa2cSIntel 380de3cfa2cSIntel return 0; 381de3cfa2cSIntel } 382