xref: /dpdk/examples/qos_sched/init.c (revision 72b452c5f2599f970f47fd17d3e8e5d60bfebe7a)
13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
23998e2a0SBruce Richardson  * Copyright(c) 2010-2014 Intel Corporation
3de3cfa2cSIntel  */
4de3cfa2cSIntel 
5de3cfa2cSIntel #include <stdint.h>
6*72b452c5SDmitry Kozlyuk #include <stdlib.h>
7de3cfa2cSIntel #include <memory.h>
8de3cfa2cSIntel 
9de3cfa2cSIntel #include <rte_log.h>
10de3cfa2cSIntel #include <rte_mbuf.h>
11de3cfa2cSIntel #include <rte_debug.h>
12de3cfa2cSIntel #include <rte_ethdev.h>
13de3cfa2cSIntel #include <rte_mempool.h>
14de3cfa2cSIntel #include <rte_sched.h>
15de3cfa2cSIntel #include <rte_cycles.h>
16de3cfa2cSIntel #include <rte_string_fns.h>
17db935d01SMichal Jastrzebski #include <rte_cfgfile.h>
18de3cfa2cSIntel 
19de3cfa2cSIntel #include "main.h"
20de3cfa2cSIntel #include "cfg_file.h"
21de3cfa2cSIntel 
22de3cfa2cSIntel uint32_t app_numa_mask = 0;
23de3cfa2cSIntel static uint32_t app_inited_port_mask = 0;
24de3cfa2cSIntel 
25de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES];
26de3cfa2cSIntel 
27de3cfa2cSIntel #define MAX_NAME_LEN 32
28de3cfa2cSIntel 
29de3cfa2cSIntel struct ring_conf ring_conf = {
30de3cfa2cSIntel 	.rx_size   = APP_RX_DESC_DEFAULT,
31de3cfa2cSIntel 	.ring_size = APP_RING_SIZE,
32de3cfa2cSIntel 	.tx_size   = APP_TX_DESC_DEFAULT,
33de3cfa2cSIntel };
34de3cfa2cSIntel 
35de3cfa2cSIntel struct burst_conf burst_conf = {
36de3cfa2cSIntel 	.rx_burst    = MAX_PKT_RX_BURST,
37de3cfa2cSIntel 	.ring_burst  = PKT_ENQUEUE,
38de3cfa2cSIntel 	.qos_dequeue = PKT_DEQUEUE,
39de3cfa2cSIntel 	.tx_burst    = MAX_PKT_TX_BURST,
40de3cfa2cSIntel };
41de3cfa2cSIntel 
42de3cfa2cSIntel struct ring_thresh rx_thresh = {
43de3cfa2cSIntel 	.pthresh = RX_PTHRESH,
44de3cfa2cSIntel 	.hthresh = RX_HTHRESH,
45de3cfa2cSIntel 	.wthresh = RX_WTHRESH,
46de3cfa2cSIntel };
47de3cfa2cSIntel 
48de3cfa2cSIntel struct ring_thresh tx_thresh = {
49de3cfa2cSIntel 	.pthresh = TX_PTHRESH,
50de3cfa2cSIntel 	.hthresh = TX_HTHRESH,
51de3cfa2cSIntel 	.wthresh = TX_WTHRESH,
52de3cfa2cSIntel };
53de3cfa2cSIntel 
54de3cfa2cSIntel uint32_t nb_pfc;
55de3cfa2cSIntel const char *cfg_profile = NULL;
56e93b24a3SIntel int mp_size = NB_MBUF;
57de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS];
58de3cfa2cSIntel 
59e2ef4628SShahaf Shuler static struct rte_eth_conf port_conf = {
60de3cfa2cSIntel 	.rxmode = {
61de3cfa2cSIntel 		.split_hdr_size = 0,
62de3cfa2cSIntel 	},
63de3cfa2cSIntel 	.txmode = {
64295968d1SFerruh Yigit 		.mq_mode = RTE_ETH_MQ_TX_NONE,
65de3cfa2cSIntel 	},
66de3cfa2cSIntel };
67de3cfa2cSIntel 
68de3cfa2cSIntel static int
69f8244c63SZhiyong Yang app_init_port(uint16_t portid, struct rte_mempool *mp)
70de3cfa2cSIntel {
71de3cfa2cSIntel 	int ret;
72de3cfa2cSIntel 	struct rte_eth_link link;
73e2ef4628SShahaf Shuler 	struct rte_eth_dev_info dev_info;
74de3cfa2cSIntel 	struct rte_eth_rxconf rx_conf;
75de3cfa2cSIntel 	struct rte_eth_txconf tx_conf;
7660efb44fSRoman Zhukov 	uint16_t rx_size;
7760efb44fSRoman Zhukov 	uint16_t tx_size;
78e2ef4628SShahaf Shuler 	struct rte_eth_conf local_port_conf = port_conf;
79db4e8135SIvan Dyukov 	char link_status_text[RTE_ETH_LINK_MAX_STR_LEN];
80de3cfa2cSIntel 
81de3cfa2cSIntel 	/* check if port already initialized (multistream configuration) */
82de3cfa2cSIntel 	if (app_inited_port_mask & (1u << portid))
83de3cfa2cSIntel 		return 0;
84de3cfa2cSIntel 
85de3cfa2cSIntel 	rx_conf.rx_thresh.pthresh = rx_thresh.pthresh;
86de3cfa2cSIntel 	rx_conf.rx_thresh.hthresh = rx_thresh.hthresh;
87de3cfa2cSIntel 	rx_conf.rx_thresh.wthresh = rx_thresh.wthresh;
88de3cfa2cSIntel 	rx_conf.rx_free_thresh = 32;
89de3cfa2cSIntel 	rx_conf.rx_drop_en = 0;
9096b5077cSJasvinder Singh 	rx_conf.rx_deferred_start = 0;
91de3cfa2cSIntel 
92de3cfa2cSIntel 	tx_conf.tx_thresh.pthresh = tx_thresh.pthresh;
93de3cfa2cSIntel 	tx_conf.tx_thresh.hthresh = tx_thresh.hthresh;
94de3cfa2cSIntel 	tx_conf.tx_thresh.wthresh = tx_thresh.wthresh;
95de3cfa2cSIntel 	tx_conf.tx_free_thresh = 0;
96de3cfa2cSIntel 	tx_conf.tx_rs_thresh = 0;
9796b5077cSJasvinder Singh 	tx_conf.tx_deferred_start = 0;
98de3cfa2cSIntel 
99de3cfa2cSIntel 	/* init port */
100f8244c63SZhiyong Yang 	RTE_LOG(INFO, APP, "Initializing port %"PRIu16"... ", portid);
101de3cfa2cSIntel 	fflush(stdout);
10245069992SIvan Ilchenko 
10345069992SIvan Ilchenko 	ret = rte_eth_dev_info_get(portid, &dev_info);
10445069992SIvan Ilchenko 	if (ret != 0)
10545069992SIvan Ilchenko 		rte_exit(EXIT_FAILURE,
10645069992SIvan Ilchenko 			"Error during getting device (port %u) info: %s\n",
10745069992SIvan Ilchenko 			portid, strerror(-ret));
10845069992SIvan Ilchenko 
109295968d1SFerruh Yigit 	if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
110e2ef4628SShahaf Shuler 		local_port_conf.txmode.offloads |=
111295968d1SFerruh Yigit 			RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
112e2ef4628SShahaf Shuler 	ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf);
113de3cfa2cSIntel 	if (ret < 0)
114f8244c63SZhiyong Yang 		rte_exit(EXIT_FAILURE,
115f8244c63SZhiyong Yang 			 "Cannot configure device: err=%d, port=%u\n",
116f8244c63SZhiyong Yang 			 ret, portid);
117de3cfa2cSIntel 
11860efb44fSRoman Zhukov 	rx_size = ring_conf.rx_size;
11960efb44fSRoman Zhukov 	tx_size = ring_conf.tx_size;
12060efb44fSRoman Zhukov 	ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &rx_size, &tx_size);
12160efb44fSRoman Zhukov 	if (ret < 0)
122f8244c63SZhiyong Yang 		rte_exit(EXIT_FAILURE,
123f8244c63SZhiyong Yang 			 "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n",
124f8244c63SZhiyong Yang 			 ret, portid);
12560efb44fSRoman Zhukov 	ring_conf.rx_size = rx_size;
12660efb44fSRoman Zhukov 	ring_conf.tx_size = tx_size;
12760efb44fSRoman Zhukov 
128de3cfa2cSIntel 	/* init one RX queue */
129de3cfa2cSIntel 	fflush(stdout);
130e2ef4628SShahaf Shuler 	rx_conf.offloads = local_port_conf.rxmode.offloads;
131de3cfa2cSIntel 	ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size,
132de3cfa2cSIntel 		rte_eth_dev_socket_id(portid), &rx_conf, mp);
133de3cfa2cSIntel 	if (ret < 0)
134f8244c63SZhiyong Yang 		rte_exit(EXIT_FAILURE,
135f8244c63SZhiyong Yang 			 "rte_eth_tx_queue_setup: err=%d, port=%u\n",
136f8244c63SZhiyong Yang 			 ret, portid);
137de3cfa2cSIntel 
138de3cfa2cSIntel 	/* init one TX queue */
139de3cfa2cSIntel 	fflush(stdout);
140e2ef4628SShahaf Shuler 	tx_conf.offloads = local_port_conf.txmode.offloads;
141de3cfa2cSIntel 	ret = rte_eth_tx_queue_setup(portid, 0,
142de3cfa2cSIntel 		(uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf);
143de3cfa2cSIntel 	if (ret < 0)
144f8244c63SZhiyong Yang 		rte_exit(EXIT_FAILURE,
145f8244c63SZhiyong Yang 			 "rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n",
146f8244c63SZhiyong Yang 			 ret, portid, 0);
147de3cfa2cSIntel 
148de3cfa2cSIntel 	/* Start device */
149de3cfa2cSIntel 	ret = rte_eth_dev_start(portid);
150de3cfa2cSIntel 	if (ret < 0)
151f8244c63SZhiyong Yang 		rte_exit(EXIT_FAILURE,
152f8244c63SZhiyong Yang 			 "rte_pmd_port_start: err=%d, port=%u\n",
153f8244c63SZhiyong Yang 			 ret, portid);
154de3cfa2cSIntel 
155de3cfa2cSIntel 	printf("done: ");
156de3cfa2cSIntel 
157de3cfa2cSIntel 	/* get link status */
15822e5c73bSIgor Romanov 	ret = rte_eth_link_get(portid, &link);
15922e5c73bSIgor Romanov 	if (ret < 0)
16022e5c73bSIgor Romanov 		rte_exit(EXIT_FAILURE,
16122e5c73bSIgor Romanov 			 "rte_eth_link_get: err=%d, port=%u: %s\n",
16222e5c73bSIgor Romanov 			 ret, portid, rte_strerror(-ret));
16322e5c73bSIgor Romanov 
164db4e8135SIvan Dyukov 	rte_eth_link_to_str(link_status_text, sizeof(link_status_text), &link);
165db4e8135SIvan Dyukov 	printf("%s\n", link_status_text);
166db4e8135SIvan Dyukov 
167f430bbceSIvan Ilchenko 	ret = rte_eth_promiscuous_enable(portid);
168f430bbceSIvan Ilchenko 	if (ret != 0)
169f430bbceSIvan Ilchenko 		rte_exit(EXIT_FAILURE,
170f430bbceSIvan Ilchenko 			"rte_eth_promiscuous_enable: err=%s, port=%u\n",
171f430bbceSIvan Ilchenko 			rte_strerror(-ret), portid);
172de3cfa2cSIntel 
173de3cfa2cSIntel 	/* mark port as initialized */
174de3cfa2cSIntel 	app_inited_port_mask |= 1u << portid;
175de3cfa2cSIntel 
176de3cfa2cSIntel 	return 0;
177de3cfa2cSIntel }
178de3cfa2cSIntel 
179be1e5332SJasvinder Singh static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = {
180de3cfa2cSIntel 	{ /* Profile #0 */
181de3cfa2cSIntel 		.tb_rate = 305175,
182de3cfa2cSIntel 		.tb_size = 1000000,
183de3cfa2cSIntel 
184be1e5332SJasvinder Singh 		.tc_rate = {305175, 305175, 305175, 305175, 305175, 305175,
185be1e5332SJasvinder Singh 			305175, 305175, 305175, 305175, 305175, 305175, 305175},
186de3cfa2cSIntel 		.tc_period = 40,
187835c5409SIntel 		.tc_ov_weight = 1,
188de3cfa2cSIntel 
189e16b06daSJasvinder Singh 		.wrr_weights = {1, 1, 1, 1},
190de3cfa2cSIntel 	},
191de3cfa2cSIntel };
192de3cfa2cSIntel 
193802d214dSSavinay Dharmappa static struct rte_sched_subport_profile_params
194802d214dSSavinay Dharmappa 		subport_profile[MAX_SCHED_SUBPORT_PROFILES] = {
195b0c1628bSJasvinder Singh 	{
196b0c1628bSJasvinder Singh 		.tb_rate = 1250000000,
197b0c1628bSJasvinder Singh 		.tb_size = 1000000,
198b0c1628bSJasvinder Singh 		.tc_rate = {1250000000, 1250000000, 1250000000, 1250000000,
199b0c1628bSJasvinder Singh 			1250000000, 1250000000, 1250000000, 1250000000, 1250000000,
200b0c1628bSJasvinder Singh 			1250000000, 1250000000, 1250000000, 1250000000},
201b0c1628bSJasvinder Singh 		.tc_period = 10,
202802d214dSSavinay Dharmappa 	},
203802d214dSSavinay Dharmappa };
204802d214dSSavinay Dharmappa 
20506135957SWojciech Liguzinski struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
20606135957SWojciech Liguzinski 	{
20706135957SWojciech Liguzinski 		.n_pipes_per_subport_enabled = 4096,
20806135957SWojciech Liguzinski 		.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
20906135957SWojciech Liguzinski 		.pipe_profiles = pipe_profiles,
21006135957SWojciech Liguzinski 		.n_pipe_profiles = sizeof(pipe_profiles) /
21106135957SWojciech Liguzinski 			sizeof(struct rte_sched_pipe_params),
21206135957SWojciech Liguzinski 		.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
213a61b3196SMarcin Danilewicz 		.cman_params = NULL,
214b0c1628bSJasvinder Singh 	},
215b0c1628bSJasvinder Singh };
216b0c1628bSJasvinder Singh 
217b0c1628bSJasvinder Singh struct rte_sched_port_params port_params = {
218b0c1628bSJasvinder Singh 	.name = "port_scheduler_0",
219b0c1628bSJasvinder Singh 	.socket = 0, /* computed */
220b0c1628bSJasvinder Singh 	.rate = 0, /* computed */
221b0c1628bSJasvinder Singh 	.mtu = 6 + 6 + 4 + 4 + 2 + 1500,
222b0c1628bSJasvinder Singh 	.frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT,
223b0c1628bSJasvinder Singh 	.n_subports_per_port = 1,
224802d214dSSavinay Dharmappa 	.n_subport_profiles = 1,
225802d214dSSavinay Dharmappa 	.subport_profiles = subport_profile,
226802d214dSSavinay Dharmappa 	.n_max_subport_profiles = MAX_SCHED_SUBPORT_PROFILES,
227b0c1628bSJasvinder Singh 	.n_pipes_per_subport = MAX_SCHED_PIPES,
228de3cfa2cSIntel };
229de3cfa2cSIntel 
230de3cfa2cSIntel static struct rte_sched_port *
231de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid)
232de3cfa2cSIntel {
233de3cfa2cSIntel 	static char port_name[32]; /* static as referenced from global port_params*/
234de3cfa2cSIntel 	struct rte_eth_link link;
235de3cfa2cSIntel 	struct rte_sched_port *port = NULL;
236de3cfa2cSIntel 	uint32_t pipe, subport;
237de3cfa2cSIntel 	int err;
238de3cfa2cSIntel 
23922e5c73bSIgor Romanov 	err = rte_eth_link_get(portid, &link);
24022e5c73bSIgor Romanov 	if (err < 0)
24122e5c73bSIgor Romanov 		rte_exit(EXIT_FAILURE,
24222e5c73bSIgor Romanov 			 "rte_eth_link_get: err=%d, port=%u: %s\n",
24322e5c73bSIgor Romanov 			 err, portid, rte_strerror(-err));
244de3cfa2cSIntel 
245de3cfa2cSIntel 	port_params.socket = socketid;
246de3cfa2cSIntel 	port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8;
2476f41fe75SStephen Hemminger 	snprintf(port_name, sizeof(port_name), "port_%d", portid);
248de3cfa2cSIntel 	port_params.name = port_name;
249de3cfa2cSIntel 
250de3cfa2cSIntel 	port = rte_sched_port_config(&port_params);
251de3cfa2cSIntel 	if (port == NULL){
252de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "Unable to config sched port\n");
253de3cfa2cSIntel 	}
254de3cfa2cSIntel 
255de3cfa2cSIntel 	for (subport = 0; subport < port_params.n_subports_per_port; subport ++) {
256ac6fcb84SSavinay Dharmappa 		err = rte_sched_subport_config(port, subport,
257802d214dSSavinay Dharmappa 				&subport_params[subport],
258802d214dSSavinay Dharmappa 				0);
259de3cfa2cSIntel 		if (err) {
260802d214dSSavinay Dharmappa 			rte_exit(EXIT_FAILURE, "Unable to config sched "
261802d214dSSavinay Dharmappa 				 "subport %u, err=%d\n", subport, err);
262de3cfa2cSIntel 		}
263de3cfa2cSIntel 
264b0c1628bSJasvinder Singh 		uint32_t n_pipes_per_subport =
265b0c1628bSJasvinder Singh 			subport_params[subport].n_pipes_per_subport_enabled;
266b0c1628bSJasvinder Singh 
267b0c1628bSJasvinder Singh 		for (pipe = 0; pipe < n_pipes_per_subport; pipe++) {
268de3cfa2cSIntel 			if (app_pipe_to_profile[subport][pipe] != -1) {
269de3cfa2cSIntel 				err = rte_sched_pipe_config(port, subport, pipe,
270de3cfa2cSIntel 						app_pipe_to_profile[subport][pipe]);
271de3cfa2cSIntel 				if (err) {
272de3cfa2cSIntel 					rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u "
273de3cfa2cSIntel 							"for profile %d, err=%d\n", pipe,
274de3cfa2cSIntel 							app_pipe_to_profile[subport][pipe], err);
275de3cfa2cSIntel 				}
276de3cfa2cSIntel 			}
277de3cfa2cSIntel 		}
278de3cfa2cSIntel 	}
279de3cfa2cSIntel 
280de3cfa2cSIntel 	return port;
281de3cfa2cSIntel }
282de3cfa2cSIntel 
283de3cfa2cSIntel static int
284de3cfa2cSIntel app_load_cfg_profile(const char *profile)
285de3cfa2cSIntel {
286de3cfa2cSIntel 	if (profile == NULL)
287de3cfa2cSIntel 		return 0;
288db935d01SMichal Jastrzebski 	struct rte_cfgfile *file = rte_cfgfile_load(profile, 0);
289db935d01SMichal Jastrzebski 	if (file == NULL)
290de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile);
291de3cfa2cSIntel 
292db935d01SMichal Jastrzebski 	cfg_load_port(file, &port_params);
293db935d01SMichal Jastrzebski 	cfg_load_subport(file, subport_params);
294802d214dSSavinay Dharmappa 	cfg_load_subport_profile(file, subport_profile);
295db935d01SMichal Jastrzebski 	cfg_load_pipe(file, pipe_profiles);
296de3cfa2cSIntel 
297db935d01SMichal Jastrzebski 	rte_cfgfile_close(file);
298de3cfa2cSIntel 
299de3cfa2cSIntel 	return 0;
300de3cfa2cSIntel }
301de3cfa2cSIntel 
302de3cfa2cSIntel int app_init(void)
303de3cfa2cSIntel {
304de3cfa2cSIntel 	uint32_t i;
305de3cfa2cSIntel 	char ring_name[MAX_NAME_LEN];
306de3cfa2cSIntel 	char pool_name[MAX_NAME_LEN];
307de3cfa2cSIntel 
308d9a42a69SThomas Monjalon 	if (rte_eth_dev_count_avail() == 0)
309de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n");
310de3cfa2cSIntel 
311de3cfa2cSIntel 	/* load configuration profile */
312de3cfa2cSIntel 	if (app_load_cfg_profile(cfg_profile) != 0)
313de3cfa2cSIntel 		rte_exit(EXIT_FAILURE, "Invalid configuration profile\n");
314de3cfa2cSIntel 
315de3cfa2cSIntel 	/* Initialize each active flow */
316de3cfa2cSIntel 	for(i = 0; i < nb_pfc; i++) {
317de3cfa2cSIntel 		uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core);
318de3cfa2cSIntel 		struct rte_ring *ring;
319de3cfa2cSIntel 
3206f41fe75SStephen Hemminger 		snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core);
321de3cfa2cSIntel 		ring = rte_ring_lookup(ring_name);
322de3cfa2cSIntel 		if (ring == NULL)
323de3cfa2cSIntel 			qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size,
324de3cfa2cSIntel 			 	socket, RING_F_SP_ENQ | RING_F_SC_DEQ);
325de3cfa2cSIntel 		else
326de3cfa2cSIntel 			qos_conf[i].rx_ring = ring;
327de3cfa2cSIntel 
3286f41fe75SStephen Hemminger 		snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core);
329de3cfa2cSIntel 		ring = rte_ring_lookup(ring_name);
330de3cfa2cSIntel 		if (ring == NULL)
331de3cfa2cSIntel 			qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size,
332de3cfa2cSIntel 				socket, RING_F_SP_ENQ | RING_F_SC_DEQ);
333de3cfa2cSIntel 		else
334de3cfa2cSIntel 			qos_conf[i].tx_ring = ring;
335de3cfa2cSIntel 
336de3cfa2cSIntel 
337de3cfa2cSIntel 		/* create the mbuf pools for each RX Port */
3386f41fe75SStephen Hemminger 		snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i);
339ea0c20eaSOlivier Matz 		qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name,
340824cb29cSKonstantin Ananyev 			mp_size, burst_conf.rx_burst * 4, 0,
341824cb29cSKonstantin Ananyev 			RTE_MBUF_DEFAULT_BUF_SIZE,
342ea0c20eaSOlivier Matz 			rte_eth_dev_socket_id(qos_conf[i].rx_port));
343de3cfa2cSIntel 		if (qos_conf[i].mbuf_pool == NULL)
344de3cfa2cSIntel 			rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i);
345de3cfa2cSIntel 
346de3cfa2cSIntel 		app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool);
347de3cfa2cSIntel 		app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool);
348de3cfa2cSIntel 
349cfd5c971SIntel 		qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket);
350de3cfa2cSIntel 	}
351de3cfa2cSIntel 
352de3cfa2cSIntel 	RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n",
353de3cfa2cSIntel 			 rte_get_timer_hz());
354de3cfa2cSIntel 
355de3cfa2cSIntel 	RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u,"
356e93b24a3SIntel 			 "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size,
357de3cfa2cSIntel 			 ring_conf.tx_size);
358de3cfa2cSIntel 
359de3cfa2cSIntel 	RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n"
360de3cfa2cSIntel 						  "             Worker read/QoS enqueue = %hu,\n"
361de3cfa2cSIntel 						  "             QoS dequeue = %hu, Worker write = %hu\n",
362de3cfa2cSIntel 		burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst,
363de3cfa2cSIntel 		burst_conf.qos_dequeue, burst_conf.tx_burst);
364de3cfa2cSIntel 
365de3cfa2cSIntel 	RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu),"
366de3cfa2cSIntel 				 "TX (p = %hhu, h = %hhu, w = %hhu)\n",
367de3cfa2cSIntel 		rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh,
368de3cfa2cSIntel 		tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh);
369de3cfa2cSIntel 
370de3cfa2cSIntel 	return 0;
371de3cfa2cSIntel }
372