13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation 3de3cfa2cSIntel */ 4de3cfa2cSIntel 5de3cfa2cSIntel #include <stdint.h> 672b452c5SDmitry Kozlyuk #include <stdlib.h> 7de3cfa2cSIntel #include <memory.h> 8de3cfa2cSIntel 9de3cfa2cSIntel #include <rte_log.h> 10de3cfa2cSIntel #include <rte_mbuf.h> 11de3cfa2cSIntel #include <rte_debug.h> 12de3cfa2cSIntel #include <rte_ethdev.h> 13de3cfa2cSIntel #include <rte_mempool.h> 14de3cfa2cSIntel #include <rte_sched.h> 15de3cfa2cSIntel #include <rte_cycles.h> 16de3cfa2cSIntel #include <rte_string_fns.h> 17db935d01SMichal Jastrzebski #include <rte_cfgfile.h> 18de3cfa2cSIntel 19de3cfa2cSIntel #include "main.h" 20de3cfa2cSIntel #include "cfg_file.h" 21de3cfa2cSIntel 22de3cfa2cSIntel uint32_t app_numa_mask = 0; 23de3cfa2cSIntel static uint32_t app_inited_port_mask = 0; 24de3cfa2cSIntel 25de3cfa2cSIntel int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES]; 26de3cfa2cSIntel 27de3cfa2cSIntel #define MAX_NAME_LEN 32 28de3cfa2cSIntel 29de3cfa2cSIntel struct ring_conf ring_conf = { 30de3cfa2cSIntel .rx_size = APP_RX_DESC_DEFAULT, 31de3cfa2cSIntel .ring_size = APP_RING_SIZE, 32de3cfa2cSIntel .tx_size = APP_TX_DESC_DEFAULT, 33de3cfa2cSIntel }; 34de3cfa2cSIntel 35de3cfa2cSIntel struct burst_conf burst_conf = { 36de3cfa2cSIntel .rx_burst = MAX_PKT_RX_BURST, 37de3cfa2cSIntel .ring_burst = PKT_ENQUEUE, 38de3cfa2cSIntel .qos_dequeue = PKT_DEQUEUE, 39de3cfa2cSIntel .tx_burst = MAX_PKT_TX_BURST, 40de3cfa2cSIntel }; 41de3cfa2cSIntel 42de3cfa2cSIntel struct ring_thresh rx_thresh = { 43de3cfa2cSIntel .pthresh = RX_PTHRESH, 44de3cfa2cSIntel .hthresh = RX_HTHRESH, 45de3cfa2cSIntel .wthresh = RX_WTHRESH, 46de3cfa2cSIntel }; 47de3cfa2cSIntel 48de3cfa2cSIntel struct ring_thresh tx_thresh = { 49de3cfa2cSIntel .pthresh = TX_PTHRESH, 50de3cfa2cSIntel .hthresh = TX_HTHRESH, 51de3cfa2cSIntel .wthresh = TX_WTHRESH, 52de3cfa2cSIntel }; 53de3cfa2cSIntel 54de3cfa2cSIntel uint32_t nb_pfc; 55de3cfa2cSIntel const char *cfg_profile = NULL; 56e93b24a3SIntel int mp_size = NB_MBUF; 57de3cfa2cSIntel struct flow_conf qos_conf[MAX_DATA_STREAMS]; 58de3cfa2cSIntel 59e2ef4628SShahaf Shuler static struct rte_eth_conf port_conf = { 60de3cfa2cSIntel .txmode = { 61295968d1SFerruh Yigit .mq_mode = RTE_ETH_MQ_TX_NONE, 62de3cfa2cSIntel }, 63de3cfa2cSIntel }; 64de3cfa2cSIntel 65de3cfa2cSIntel static int 66f8244c63SZhiyong Yang app_init_port(uint16_t portid, struct rte_mempool *mp) 67de3cfa2cSIntel { 68de3cfa2cSIntel int ret; 69de3cfa2cSIntel struct rte_eth_link link; 70e2ef4628SShahaf Shuler struct rte_eth_dev_info dev_info; 71de3cfa2cSIntel struct rte_eth_rxconf rx_conf; 72de3cfa2cSIntel struct rte_eth_txconf tx_conf; 7360efb44fSRoman Zhukov uint16_t rx_size; 7460efb44fSRoman Zhukov uint16_t tx_size; 75e2ef4628SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf; 76db4e8135SIvan Dyukov char link_status_text[RTE_ETH_LINK_MAX_STR_LEN]; 77de3cfa2cSIntel 78de3cfa2cSIntel /* check if port already initialized (multistream configuration) */ 79de3cfa2cSIntel if (app_inited_port_mask & (1u << portid)) 80de3cfa2cSIntel return 0; 81de3cfa2cSIntel 82af13b871SMegha Ajmera memset(&rx_conf, 0, sizeof(struct rte_eth_rxconf)); 83de3cfa2cSIntel rx_conf.rx_thresh.pthresh = rx_thresh.pthresh; 84de3cfa2cSIntel rx_conf.rx_thresh.hthresh = rx_thresh.hthresh; 85de3cfa2cSIntel rx_conf.rx_thresh.wthresh = rx_thresh.wthresh; 86de3cfa2cSIntel rx_conf.rx_free_thresh = 32; 87de3cfa2cSIntel rx_conf.rx_drop_en = 0; 8896b5077cSJasvinder Singh rx_conf.rx_deferred_start = 0; 89de3cfa2cSIntel 90af13b871SMegha Ajmera memset(&tx_conf, 0, sizeof(struct rte_eth_txconf)); 91de3cfa2cSIntel tx_conf.tx_thresh.pthresh = tx_thresh.pthresh; 92de3cfa2cSIntel tx_conf.tx_thresh.hthresh = tx_thresh.hthresh; 93de3cfa2cSIntel tx_conf.tx_thresh.wthresh = tx_thresh.wthresh; 94de3cfa2cSIntel tx_conf.tx_free_thresh = 0; 95de3cfa2cSIntel tx_conf.tx_rs_thresh = 0; 9696b5077cSJasvinder Singh tx_conf.tx_deferred_start = 0; 97de3cfa2cSIntel 98de3cfa2cSIntel /* init port */ 99f8244c63SZhiyong Yang RTE_LOG(INFO, APP, "Initializing port %"PRIu16"... ", portid); 100de3cfa2cSIntel fflush(stdout); 10145069992SIvan Ilchenko 10245069992SIvan Ilchenko ret = rte_eth_dev_info_get(portid, &dev_info); 10345069992SIvan Ilchenko if (ret != 0) 10445069992SIvan Ilchenko rte_exit(EXIT_FAILURE, 10545069992SIvan Ilchenko "Error during getting device (port %u) info: %s\n", 10645069992SIvan Ilchenko portid, strerror(-ret)); 10745069992SIvan Ilchenko 108295968d1SFerruh Yigit if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) 109e2ef4628SShahaf Shuler local_port_conf.txmode.offloads |= 110295968d1SFerruh Yigit RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 111e2ef4628SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf); 112de3cfa2cSIntel if (ret < 0) 113f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 114f8244c63SZhiyong Yang "Cannot configure device: err=%d, port=%u\n", 115f8244c63SZhiyong Yang ret, portid); 116de3cfa2cSIntel 11760efb44fSRoman Zhukov rx_size = ring_conf.rx_size; 11860efb44fSRoman Zhukov tx_size = ring_conf.tx_size; 11960efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &rx_size, &tx_size); 12060efb44fSRoman Zhukov if (ret < 0) 121f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 122f8244c63SZhiyong Yang "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n", 123f8244c63SZhiyong Yang ret, portid); 12460efb44fSRoman Zhukov ring_conf.rx_size = rx_size; 12560efb44fSRoman Zhukov ring_conf.tx_size = tx_size; 12660efb44fSRoman Zhukov 127de3cfa2cSIntel /* init one RX queue */ 128de3cfa2cSIntel fflush(stdout); 129e2ef4628SShahaf Shuler rx_conf.offloads = local_port_conf.rxmode.offloads; 130de3cfa2cSIntel ret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size, 131de3cfa2cSIntel rte_eth_dev_socket_id(portid), &rx_conf, mp); 132de3cfa2cSIntel if (ret < 0) 133f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 134f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u\n", 135f8244c63SZhiyong Yang ret, portid); 136de3cfa2cSIntel 137de3cfa2cSIntel /* init one TX queue */ 138de3cfa2cSIntel fflush(stdout); 139e2ef4628SShahaf Shuler tx_conf.offloads = local_port_conf.txmode.offloads; 140de3cfa2cSIntel ret = rte_eth_tx_queue_setup(portid, 0, 141de3cfa2cSIntel (uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf); 142de3cfa2cSIntel if (ret < 0) 143f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 144f8244c63SZhiyong Yang "rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n", 145f8244c63SZhiyong Yang ret, portid, 0); 146de3cfa2cSIntel 147de3cfa2cSIntel /* Start device */ 148de3cfa2cSIntel ret = rte_eth_dev_start(portid); 149de3cfa2cSIntel if (ret < 0) 150f8244c63SZhiyong Yang rte_exit(EXIT_FAILURE, 151f8244c63SZhiyong Yang "rte_pmd_port_start: err=%d, port=%u\n", 152f8244c63SZhiyong Yang ret, portid); 153de3cfa2cSIntel 154de3cfa2cSIntel printf("done: "); 155de3cfa2cSIntel 156de3cfa2cSIntel /* get link status */ 15722e5c73bSIgor Romanov ret = rte_eth_link_get(portid, &link); 15822e5c73bSIgor Romanov if (ret < 0) 15922e5c73bSIgor Romanov rte_exit(EXIT_FAILURE, 16022e5c73bSIgor Romanov "rte_eth_link_get: err=%d, port=%u: %s\n", 16122e5c73bSIgor Romanov ret, portid, rte_strerror(-ret)); 16222e5c73bSIgor Romanov 163db4e8135SIvan Dyukov rte_eth_link_to_str(link_status_text, sizeof(link_status_text), &link); 164db4e8135SIvan Dyukov printf("%s\n", link_status_text); 165db4e8135SIvan Dyukov 166f430bbceSIvan Ilchenko ret = rte_eth_promiscuous_enable(portid); 167f430bbceSIvan Ilchenko if (ret != 0) 168f430bbceSIvan Ilchenko rte_exit(EXIT_FAILURE, 169f430bbceSIvan Ilchenko "rte_eth_promiscuous_enable: err=%s, port=%u\n", 170f430bbceSIvan Ilchenko rte_strerror(-ret), portid); 171de3cfa2cSIntel 172de3cfa2cSIntel /* mark port as initialized */ 173de3cfa2cSIntel app_inited_port_mask |= 1u << portid; 174de3cfa2cSIntel 175de3cfa2cSIntel return 0; 176de3cfa2cSIntel } 177de3cfa2cSIntel 178be1e5332SJasvinder Singh static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = { 179de3cfa2cSIntel { /* Profile #0 */ 180de3cfa2cSIntel .tb_rate = 305175, 181de3cfa2cSIntel .tb_size = 1000000, 182de3cfa2cSIntel 183be1e5332SJasvinder Singh .tc_rate = {305175, 305175, 305175, 305175, 305175, 305175, 184be1e5332SJasvinder Singh 305175, 305175, 305175, 305175, 305175, 305175, 305175}, 185de3cfa2cSIntel .tc_period = 40, 186835c5409SIntel .tc_ov_weight = 1, 187de3cfa2cSIntel 188e16b06daSJasvinder Singh .wrr_weights = {1, 1, 1, 1}, 189de3cfa2cSIntel }, 190de3cfa2cSIntel }; 191de3cfa2cSIntel 192802d214dSSavinay Dharmappa static struct rte_sched_subport_profile_params 193802d214dSSavinay Dharmappa subport_profile[MAX_SCHED_SUBPORT_PROFILES] = { 194b0c1628bSJasvinder Singh { 195b0c1628bSJasvinder Singh .tb_rate = 1250000000, 196b0c1628bSJasvinder Singh .tb_size = 1000000, 197b0c1628bSJasvinder Singh .tc_rate = {1250000000, 1250000000, 1250000000, 1250000000, 198b0c1628bSJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000, 1250000000, 199b0c1628bSJasvinder Singh 1250000000, 1250000000, 1250000000, 1250000000}, 200b0c1628bSJasvinder Singh .tc_period = 10, 201802d214dSSavinay Dharmappa }, 202802d214dSSavinay Dharmappa }; 203802d214dSSavinay Dharmappa 20406135957SWojciech Liguzinski struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { 20506135957SWojciech Liguzinski { 20606135957SWojciech Liguzinski .n_pipes_per_subport_enabled = 4096, 20706135957SWojciech Liguzinski .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, 20806135957SWojciech Liguzinski .pipe_profiles = pipe_profiles, 20906135957SWojciech Liguzinski .n_pipe_profiles = sizeof(pipe_profiles) / 21006135957SWojciech Liguzinski sizeof(struct rte_sched_pipe_params), 21106135957SWojciech Liguzinski .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, 212a61b3196SMarcin Danilewicz .cman_params = NULL, 213b0c1628bSJasvinder Singh }, 214b0c1628bSJasvinder Singh }; 215b0c1628bSJasvinder Singh 216b0c1628bSJasvinder Singh struct rte_sched_port_params port_params = { 217b0c1628bSJasvinder Singh .name = "port_scheduler_0", 218b0c1628bSJasvinder Singh .socket = 0, /* computed */ 219b0c1628bSJasvinder Singh .rate = 0, /* computed */ 220b0c1628bSJasvinder Singh .mtu = 6 + 6 + 4 + 4 + 2 + 1500, 221b0c1628bSJasvinder Singh .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT, 222b0c1628bSJasvinder Singh .n_subports_per_port = 1, 223802d214dSSavinay Dharmappa .n_subport_profiles = 1, 224802d214dSSavinay Dharmappa .subport_profiles = subport_profile, 225802d214dSSavinay Dharmappa .n_max_subport_profiles = MAX_SCHED_SUBPORT_PROFILES, 226b0c1628bSJasvinder Singh .n_pipes_per_subport = MAX_SCHED_PIPES, 227de3cfa2cSIntel }; 228de3cfa2cSIntel 229de3cfa2cSIntel static struct rte_sched_port * 230de3cfa2cSIntel app_init_sched_port(uint32_t portid, uint32_t socketid) 231de3cfa2cSIntel { 232de3cfa2cSIntel static char port_name[32]; /* static as referenced from global port_params*/ 233de3cfa2cSIntel struct rte_eth_link link; 234de3cfa2cSIntel struct rte_sched_port *port = NULL; 235de3cfa2cSIntel uint32_t pipe, subport; 236e723a59eSBruce Richardson uint32_t pipe_count; 237de3cfa2cSIntel int err; 238de3cfa2cSIntel 23922e5c73bSIgor Romanov err = rte_eth_link_get(portid, &link); 24022e5c73bSIgor Romanov if (err < 0) 24122e5c73bSIgor Romanov rte_exit(EXIT_FAILURE, 24222e5c73bSIgor Romanov "rte_eth_link_get: err=%d, port=%u: %s\n", 24322e5c73bSIgor Romanov err, portid, rte_strerror(-err)); 244de3cfa2cSIntel 245de3cfa2cSIntel port_params.socket = socketid; 246de3cfa2cSIntel port_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8; 2476f41fe75SStephen Hemminger snprintf(port_name, sizeof(port_name), "port_%d", portid); 248de3cfa2cSIntel port_params.name = port_name; 249de3cfa2cSIntel 250de3cfa2cSIntel port = rte_sched_port_config(&port_params); 251de3cfa2cSIntel if (port == NULL){ 252de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched port\n"); 253de3cfa2cSIntel } 254de3cfa2cSIntel 255de3cfa2cSIntel for (subport = 0; subport < port_params.n_subports_per_port; subport ++) { 256ac6fcb84SSavinay Dharmappa err = rte_sched_subport_config(port, subport, 257802d214dSSavinay Dharmappa &subport_params[subport], 258802d214dSSavinay Dharmappa 0); 259de3cfa2cSIntel if (err) { 260802d214dSSavinay Dharmappa rte_exit(EXIT_FAILURE, "Unable to config sched " 261802d214dSSavinay Dharmappa "subport %u, err=%d\n", subport, err); 262de3cfa2cSIntel } 263de3cfa2cSIntel 264b0c1628bSJasvinder Singh uint32_t n_pipes_per_subport = 265b0c1628bSJasvinder Singh subport_params[subport].n_pipes_per_subport_enabled; 266b0c1628bSJasvinder Singh 267e723a59eSBruce Richardson pipe_count = 0; 268b0c1628bSJasvinder Singh for (pipe = 0; pipe < n_pipes_per_subport; pipe++) { 269de3cfa2cSIntel if (app_pipe_to_profile[subport][pipe] != -1) { 270de3cfa2cSIntel err = rte_sched_pipe_config(port, subport, pipe, 271de3cfa2cSIntel app_pipe_to_profile[subport][pipe]); 272de3cfa2cSIntel if (err) { 273de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Unable to config sched pipe %u " 274de3cfa2cSIntel "for profile %d, err=%d\n", pipe, 275de3cfa2cSIntel app_pipe_to_profile[subport][pipe], err); 276de3cfa2cSIntel } 277e723a59eSBruce Richardson pipe_count++; 278de3cfa2cSIntel } 279de3cfa2cSIntel } 280e723a59eSBruce Richardson 281e723a59eSBruce Richardson if (pipe_count == 0) 282e723a59eSBruce Richardson rte_exit(EXIT_FAILURE, "Error: invalid config, no pipes enabled for sched subport %u\n", 283e723a59eSBruce Richardson subport); 284de3cfa2cSIntel } 285de3cfa2cSIntel 286de3cfa2cSIntel return port; 287de3cfa2cSIntel } 288de3cfa2cSIntel 289de3cfa2cSIntel static int 290de3cfa2cSIntel app_load_cfg_profile(const char *profile) 291de3cfa2cSIntel { 29292e9fe0dSMegha Ajmera int ret = 0; 293de3cfa2cSIntel if (profile == NULL) 294de3cfa2cSIntel return 0; 295db935d01SMichal Jastrzebski struct rte_cfgfile *file = rte_cfgfile_load(profile, 0); 296db935d01SMichal Jastrzebski if (file == NULL) 297de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot load configuration profile %s\n", profile); 298de3cfa2cSIntel 29992e9fe0dSMegha Ajmera ret = cfg_load_port(file, &port_params); 30092e9fe0dSMegha Ajmera if (ret) 30192e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 302de3cfa2cSIntel 30392e9fe0dSMegha Ajmera ret = cfg_load_subport(file, subport_params); 30492e9fe0dSMegha Ajmera if (ret) 30592e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 30692e9fe0dSMegha Ajmera 30792e9fe0dSMegha Ajmera ret = cfg_load_subport_profile(file, subport_profile); 30892e9fe0dSMegha Ajmera if (ret) 30992e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 31092e9fe0dSMegha Ajmera 31192e9fe0dSMegha Ajmera ret = cfg_load_pipe(file, pipe_profiles); 31292e9fe0dSMegha Ajmera if (ret) 31392e9fe0dSMegha Ajmera goto _app_load_cfg_profile_error_return; 31492e9fe0dSMegha Ajmera 31592e9fe0dSMegha Ajmera _app_load_cfg_profile_error_return: 316db935d01SMichal Jastrzebski rte_cfgfile_close(file); 317de3cfa2cSIntel 31892e9fe0dSMegha Ajmera return ret; 319de3cfa2cSIntel } 320de3cfa2cSIntel 321de3cfa2cSIntel int app_init(void) 322de3cfa2cSIntel { 323de3cfa2cSIntel uint32_t i; 324de3cfa2cSIntel char ring_name[MAX_NAME_LEN]; 325de3cfa2cSIntel char pool_name[MAX_NAME_LEN]; 326*6c5e32c7SStephen Hemminger int ret; 327de3cfa2cSIntel 328d9a42a69SThomas Monjalon if (rte_eth_dev_count_avail() == 0) 329de3cfa2cSIntel rte_exit(EXIT_FAILURE, "No Ethernet port - bye\n"); 330de3cfa2cSIntel 331de3cfa2cSIntel /* load configuration profile */ 332de3cfa2cSIntel if (app_load_cfg_profile(cfg_profile) != 0) 333de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Invalid configuration profile\n"); 334de3cfa2cSIntel 335de3cfa2cSIntel /* Initialize each active flow */ 336de3cfa2cSIntel for(i = 0; i < nb_pfc; i++) { 337de3cfa2cSIntel uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); 338de3cfa2cSIntel struct rte_ring *ring; 339b9a87346SChengwen Feng struct rte_eth_link link; 340665b49c5SBruce Richardson int retry_count = 100, retry_delay = 100; /* try every 100ms for 10 sec */ 341de3cfa2cSIntel 3426f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); 343de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 344de3cfa2cSIntel if (ring == NULL) 345de3cfa2cSIntel qos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 346de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 347de3cfa2cSIntel else 348de3cfa2cSIntel qos_conf[i].rx_ring = ring; 349de3cfa2cSIntel 3506f41fe75SStephen Hemminger snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core); 351de3cfa2cSIntel ring = rte_ring_lookup(ring_name); 352de3cfa2cSIntel if (ring == NULL) 353de3cfa2cSIntel qos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size, 354de3cfa2cSIntel socket, RING_F_SP_ENQ | RING_F_SC_DEQ); 355de3cfa2cSIntel else 356de3cfa2cSIntel qos_conf[i].tx_ring = ring; 357de3cfa2cSIntel 358de3cfa2cSIntel 359de3cfa2cSIntel /* create the mbuf pools for each RX Port */ 3606f41fe75SStephen Hemminger snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i); 361ea0c20eaSOlivier Matz qos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name, 362824cb29cSKonstantin Ananyev mp_size, burst_conf.rx_burst * 4, 0, 363824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, 364ea0c20eaSOlivier Matz rte_eth_dev_socket_id(qos_conf[i].rx_port)); 365de3cfa2cSIntel if (qos_conf[i].mbuf_pool == NULL) 366de3cfa2cSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool for socket %u\n", i); 367de3cfa2cSIntel 368de3cfa2cSIntel app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); 369de3cfa2cSIntel app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); 370de3cfa2cSIntel 371b9a87346SChengwen Feng memset(&link, 0, sizeof(link)); 372*6c5e32c7SStephen Hemminger ret = rte_eth_link_get(qos_conf[i].tx_port, &link); 373*6c5e32c7SStephen Hemminger if (ret < 0) 374*6c5e32c7SStephen Hemminger rte_exit(EXIT_FAILURE, 375*6c5e32c7SStephen Hemminger "rte_eth_link_get: err=%d, port=%u: %s\n", 376*6c5e32c7SStephen Hemminger ret, qos_conf[i].tx_port, rte_strerror(-ret)); 377665b49c5SBruce Richardson if (link.link_status == 0) 378665b49c5SBruce Richardson printf("Waiting for link on port %u\n", qos_conf[i].tx_port); 379*6c5e32c7SStephen Hemminger 380665b49c5SBruce Richardson while (link.link_status == 0 && retry_count--) { 381665b49c5SBruce Richardson rte_delay_ms(retry_delay); 382*6c5e32c7SStephen Hemminger ret = rte_eth_link_get(qos_conf[i].tx_port, &link); 383*6c5e32c7SStephen Hemminger rte_exit(EXIT_FAILURE, 384*6c5e32c7SStephen Hemminger "rte_eth_link_get: err=%d, port=%u: %s\n", 385*6c5e32c7SStephen Hemminger ret, qos_conf[i].tx_port, rte_strerror(-ret)); 386665b49c5SBruce Richardson } 387665b49c5SBruce Richardson 388cfd5c971SIntel qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket); 389de3cfa2cSIntel } 390de3cfa2cSIntel 391de3cfa2cSIntel RTE_LOG(INFO, APP, "time stamp clock running at %" PRIu64 " Hz\n", 392de3cfa2cSIntel rte_get_timer_hz()); 393de3cfa2cSIntel 394de3cfa2cSIntel RTE_LOG(INFO, APP, "Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," 395e93b24a3SIntel "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size, 396de3cfa2cSIntel ring_conf.tx_size); 397de3cfa2cSIntel 398de3cfa2cSIntel RTE_LOG(INFO, APP, "Burst sizes: RX read = %hu, RX write = %hu,\n" 399de3cfa2cSIntel " Worker read/QoS enqueue = %hu,\n" 400de3cfa2cSIntel " QoS dequeue = %hu, Worker write = %hu\n", 401de3cfa2cSIntel burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst, 402de3cfa2cSIntel burst_conf.qos_dequeue, burst_conf.tx_burst); 403de3cfa2cSIntel 404de3cfa2cSIntel RTE_LOG(INFO, APP, "NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," 405de3cfa2cSIntel "TX (p = %hhu, h = %hhu, w = %hhu)\n", 406de3cfa2cSIntel rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh, 407de3cfa2cSIntel tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh); 408de3cfa2cSIntel 409de3cfa2cSIntel return 0; 410de3cfa2cSIntel } 411