1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stdio.h> 35 #include <string.h> 36 #include <stdlib.h> 37 #include <stdint.h> 38 #include <locale.h> 39 #include <unistd.h> 40 #include <limits.h> 41 #include <getopt.h> 42 43 #include <rte_log.h> 44 #include <rte_eal.h> 45 #include <rte_lcore.h> 46 #include <rte_string_fns.h> 47 48 #include "main.h" 49 50 #define APP_NAME "qos_sched" 51 #define MAX_OPT_VALUES 8 52 #define SYS_CPU_DIR "/sys/devices/system/cpu/cpu%u/topology/" 53 54 static uint32_t app_master_core = 1; 55 static uint32_t app_numa_mask; 56 static uint64_t app_used_core_mask = 0; 57 static uint64_t app_used_port_mask = 0; 58 static uint64_t app_used_rx_port_mask = 0; 59 static uint64_t app_used_tx_port_mask = 0; 60 61 62 static const char usage[] = 63 " \n" 64 " %s <APP PARAMS> \n" 65 " \n" 66 "Application mandatory parameters: \n" 67 " --pfc \"RX PORT, TX PORT, RX LCORE, WT LCORE\" : Packet flow configuration \n" 68 " multiple pfc can be configured in command line \n" 69 " \n" 70 "Application optional parameters: \n" 71 " --mst I : master core index (default value is %u) \n" 72 " --rsz \"A, B, C\" : Ring sizes \n" 73 " A = Size (in number of buffer descriptors) of each of the NIC RX \n" 74 " rings read by the I/O RX lcores (default value is %u) \n" 75 " B = Size (in number of elements) of each of the SW rings used by the\n" 76 " I/O RX lcores to send packets to worker lcores (default value is\n" 77 " %u) \n" 78 " C = Size (in number of buffer descriptors) of each of the NIC TX \n" 79 " rings written by worker lcores (default value is %u) \n" 80 " --bsz \"A, B, C, D\": Burst sizes \n" 81 " A = I/O RX lcore read burst size from NIC RX (default value is %u) \n" 82 " B = I/O RX lcore write burst size to output SW rings, \n" 83 " Worker lcore read burst size from input SW rings, \n" 84 " QoS enqueue size (default value is %u) \n" 85 " C = QoS dequeue size (default value is %u) \n" 86 " D = Worker lcore write burst size to NIC TX (default value is %u) \n" 87 " --msz M : Mempool size (in number of mbufs) for each pfc (default %u) \n" 88 " --rth \"A, B, C\" : RX queue threshold parameters \n" 89 " A = RX prefetch threshold (default value is %u) \n" 90 " B = RX host threshold (default value is %u) \n" 91 " C = RX write-back threshold (default value is %u) \n" 92 " --tth \"A, B, C\" : TX queue threshold parameters \n" 93 " A = TX prefetch threshold (default value is %u) \n" 94 " B = TX host threshold (default value is %u) \n" 95 " C = TX write-back threshold (default value is %u) \n" 96 " --cfg FILE : profile configuration to load \n" 97 ; 98 99 /* display usage */ 100 static void 101 app_usage(const char *prgname) 102 { 103 printf(usage, prgname, app_master_core, 104 APP_RX_DESC_DEFAULT, APP_RING_SIZE, APP_TX_DESC_DEFAULT, 105 MAX_PKT_RX_BURST, PKT_ENQUEUE, PKT_DEQUEUE, 106 MAX_PKT_TX_BURST, NB_MBUF, 107 RX_PTHRESH, RX_HTHRESH, RX_WTHRESH, 108 TX_PTHRESH, TX_HTHRESH, TX_WTHRESH 109 ); 110 } 111 112 static inline int str_is(const char *str, const char *is) 113 { 114 return (strcmp(str, is) == 0); 115 } 116 117 /* returns core mask used by DPDK */ 118 static uint64_t 119 app_eal_core_mask(void) 120 { 121 uint32_t i; 122 uint64_t cm = 0; 123 struct rte_config *cfg = rte_eal_get_configuration(); 124 125 for (i = 0; i < RTE_MAX_LCORE; i++) { 126 if (cfg->lcore_role[i] == ROLE_RTE) 127 cm |= (1ULL << i); 128 } 129 130 cm |= (1ULL << cfg->master_lcore); 131 132 return cm; 133 } 134 135 136 /* returns total number of cores presented in a system */ 137 static uint32_t 138 app_cpu_core_count(void) 139 { 140 int i, len; 141 char path[PATH_MAX]; 142 uint32_t ncores = 0; 143 144 for(i = 0; i < RTE_MAX_LCORE; i++) { 145 len = rte_snprintf(path, sizeof(path), SYS_CPU_DIR, i); 146 if (len <= 0 || (unsigned)len >= sizeof(path)) 147 continue; 148 149 if (access(path, F_OK) == 0) 150 ncores++; 151 } 152 153 return ncores; 154 } 155 156 /* returns: 157 number of values parsed 158 -1 in case of error 159 */ 160 static int 161 app_parse_opt_vals(const char *conf_str, char separator, uint32_t n_vals, uint32_t *opt_vals) 162 { 163 char *string; 164 uint32_t i, n_tokens; 165 char *tokens[MAX_OPT_VALUES]; 166 167 if (conf_str == NULL || opt_vals == NULL || n_vals == 0 || n_vals > MAX_OPT_VALUES) 168 return -1; 169 170 /* duplicate configuration string before splitting it to tokens */ 171 string = strdup(conf_str); 172 if (string == NULL) 173 return -1; 174 175 n_tokens = rte_strsplit(string, strnlen(string, 32), tokens, n_vals, separator); 176 177 for(i = 0; i < n_tokens; i++) { 178 opt_vals[i] = (uint32_t)atol(tokens[i]); 179 } 180 181 free(string); 182 183 return n_tokens; 184 } 185 186 static int 187 app_parse_ring_conf(const char *conf_str) 188 { 189 int ret; 190 uint32_t vals[3]; 191 192 ret = app_parse_opt_vals(conf_str, ',', 3, vals); 193 if (ret != 3) 194 return ret; 195 196 ring_conf.rx_size = vals[0]; 197 ring_conf.ring_size = vals[1]; 198 ring_conf.tx_size = vals[2]; 199 200 return 0; 201 } 202 203 static int 204 app_parse_rth_conf(const char *conf_str) 205 { 206 int ret; 207 uint32_t vals[3]; 208 209 ret = app_parse_opt_vals(conf_str, ',', 3, vals); 210 if (ret != 3) 211 return ret; 212 213 rx_thresh.pthresh = (uint8_t)vals[0]; 214 rx_thresh.hthresh = (uint8_t)vals[1]; 215 rx_thresh.wthresh = (uint8_t)vals[2]; 216 217 return 0; 218 } 219 220 static int 221 app_parse_tth_conf(const char *conf_str) 222 { 223 int ret; 224 uint32_t vals[3]; 225 226 ret = app_parse_opt_vals(conf_str, ',', 3, vals); 227 if (ret != 3) 228 return ret; 229 230 tx_thresh.pthresh = (uint8_t)vals[0]; 231 tx_thresh.hthresh = (uint8_t)vals[1]; 232 tx_thresh.wthresh = (uint8_t)vals[2]; 233 234 return 0; 235 } 236 237 static int 238 app_parse_flow_conf(const char *conf_str) 239 { 240 int ret; 241 uint32_t vals[5]; 242 struct flow_conf *pconf; 243 uint64_t mask; 244 245 ret = app_parse_opt_vals(conf_str, ',', 6, vals); 246 if (ret < 4 || ret > 5) 247 return ret; 248 249 pconf = &qos_conf[nb_pfc]; 250 251 pconf->rx_port = (uint8_t)vals[0]; 252 pconf->tx_port = (uint8_t)vals[1]; 253 pconf->rx_core = (uint8_t)vals[2]; 254 pconf->wt_core = (uint8_t)vals[3]; 255 if (ret == 5) 256 pconf->tx_core = (uint8_t)vals[4]; 257 else 258 pconf->tx_core = pconf->wt_core; 259 260 if (pconf->rx_core == pconf->wt_core) { 261 RTE_LOG(ERR, APP, "pfc %u: rx thread and worker thread cannot share same core\n", nb_pfc); 262 return -1; 263 } 264 265 if (pconf->rx_port >= RTE_MAX_ETHPORTS) { 266 RTE_LOG(ERR, APP, "pfc %u: invalid rx port %hu index\n", nb_pfc, pconf->rx_port); 267 return -1; 268 } 269 if (pconf->tx_port >= RTE_MAX_ETHPORTS) { 270 RTE_LOG(ERR, APP, "pfc %u: invalid tx port %hu index\n", nb_pfc, pconf->rx_port); 271 return -1; 272 } 273 274 mask = 1lu << pconf->rx_port; 275 if (app_used_rx_port_mask & mask) { 276 RTE_LOG(ERR, APP, "pfc %u: rx port %hu is used already\n", nb_pfc, pconf->rx_port); 277 return -1; 278 } 279 app_used_rx_port_mask |= mask; 280 app_used_port_mask |= mask; 281 282 mask = 1lu << pconf->tx_port; 283 if (app_used_tx_port_mask & mask) { 284 RTE_LOG(ERR, APP, "pfc %u: port %hu is used already\n", nb_pfc, pconf->tx_port); 285 return -1; 286 } 287 app_used_tx_port_mask |= mask; 288 app_used_port_mask |= mask; 289 290 mask = 1lu << pconf->rx_core; 291 app_used_core_mask |= mask; 292 293 mask = 1lu << pconf->wt_core; 294 app_used_core_mask |= mask; 295 296 mask = 1lu << pconf->tx_core; 297 app_used_core_mask |= mask; 298 299 nb_pfc++; 300 301 return 0; 302 } 303 304 static int 305 app_parse_burst_conf(const char *conf_str) 306 { 307 int ret; 308 uint32_t vals[4]; 309 310 ret = app_parse_opt_vals(conf_str, ',', 4, vals); 311 if (ret != 4) 312 return ret; 313 314 burst_conf.rx_burst = (uint16_t)vals[0]; 315 burst_conf.ring_burst = (uint16_t)vals[1]; 316 burst_conf.qos_dequeue = (uint16_t)vals[2]; 317 burst_conf.tx_burst = (uint16_t)vals[3]; 318 319 return 0; 320 } 321 322 /* 323 * Parses the argument given in the command line of the application, 324 * calculates mask for used cores and initializes EAL with calculated core mask 325 */ 326 int 327 app_parse_args(int argc, char **argv) 328 { 329 int opt, ret; 330 int option_index; 331 const char *optname; 332 char *prgname = argv[0]; 333 uint32_t i, nb_lcores; 334 335 static struct option lgopts[] = { 336 { "pfc", 1, 0, 0 }, 337 { "mst", 1, 0, 0 }, 338 { "rsz", 1, 0, 0 }, 339 { "bsz", 1, 0, 0 }, 340 { "msz", 1, 0, 0 }, 341 { "rth", 1, 0, 0 }, 342 { "tth", 1, 0, 0 }, 343 { "cfg", 1, 0, 0 }, 344 { NULL, 0, 0, 0 } 345 }; 346 347 /* initialize EAL first */ 348 ret = rte_eal_init(argc, argv); 349 if (ret < 0) 350 return -1; 351 352 argc -= ret; 353 argv += ret; 354 355 /* set en_US locale to print big numbers with ',' */ 356 setlocale(LC_NUMERIC, "en_US.utf-8"); 357 358 while ((opt = getopt_long(argc, argv, "", 359 lgopts, &option_index)) != EOF) { 360 361 switch (opt) { 362 /* long options */ 363 case 0: 364 optname = lgopts[option_index].name; 365 if (str_is(optname, "pfc")) { 366 ret = app_parse_flow_conf(optarg); 367 if (ret) { 368 RTE_LOG(ERR, APP, "Invalid pipe configuration %s\n", optarg); 369 return -1; 370 } 371 break; 372 } 373 if (str_is(optname, "mst")) { 374 app_master_core = (uint32_t)atoi(optarg); 375 break; 376 } 377 if (str_is(optname, "rsz")) { 378 ret = app_parse_ring_conf(optarg); 379 if (ret) { 380 RTE_LOG(ERR, APP, "Invalid ring configuration %s\n", optarg); 381 return -1; 382 } 383 break; 384 } 385 if (str_is(optname, "bsz")) { 386 ret = app_parse_burst_conf(optarg); 387 if (ret) { 388 RTE_LOG(ERR, APP, "Invalid burst configuration %s\n", optarg); 389 return -1; 390 } 391 break; 392 } 393 if (str_is(optname, "msz")) { 394 mp_size = atoi(optarg); 395 if (mp_size <= 0) { 396 RTE_LOG(ERR, APP, "Invalid mempool size %s\n", optarg); 397 return -1; 398 } 399 break; 400 } 401 if (str_is(optname, "rth")) { 402 ret = app_parse_rth_conf(optarg); 403 if (ret) { 404 RTE_LOG(ERR, APP, "Invalid RX threshold configuration %s\n", optarg); 405 return -1; 406 } 407 break; 408 } 409 if (str_is(optname, "tth")) { 410 ret = app_parse_tth_conf(optarg); 411 if (ret) { 412 RTE_LOG(ERR, APP, "Invalid TX threshold configuration %s\n", optarg); 413 return -1; 414 } 415 break; 416 } 417 if (str_is(optname, "cfg")) { 418 cfg_profile = optarg; 419 break; 420 } 421 break; 422 423 default: 424 app_usage(prgname); 425 return -1; 426 } 427 } 428 429 /* check master core index validity */ 430 for(i = 0; i <= app_master_core; i++) { 431 if (app_used_core_mask & (1u << app_master_core)) { 432 RTE_LOG(ERR, APP, "Master core index is not configured properly\n"); 433 app_usage(prgname); 434 return -1; 435 } 436 } 437 app_used_core_mask |= 1u << app_master_core; 438 439 if ((app_used_core_mask != app_eal_core_mask()) || 440 (app_master_core != rte_get_master_lcore())) { 441 RTE_LOG(ERR, APP, "EAL core mask not configured properly, must be %" PRIx64 442 " instead of %" PRIx64 "\n" , app_used_core_mask, app_eal_core_mask()); 443 return -1; 444 } 445 446 if (nb_pfc == 0) { 447 RTE_LOG(ERR, APP, "Packet flow not configured!\n"); 448 app_usage(prgname); 449 return -1; 450 } 451 452 /* sanity check for cores assignment */ 453 nb_lcores = app_cpu_core_count(); 454 455 for(i = 0; i < nb_pfc; i++) { 456 if (qos_conf[i].rx_core >= nb_lcores) { 457 RTE_LOG(ERR, APP, "pfc %u: invalid RX lcore index %u\n", i + 1, 458 qos_conf[i].rx_core); 459 return -1; 460 } 461 if (qos_conf[i].wt_core >= nb_lcores) { 462 RTE_LOG(ERR, APP, "pfc %u: invalid WT lcore index %u\n", i + 1, 463 qos_conf[i].wt_core); 464 return -1; 465 } 466 uint32_t rx_sock = rte_lcore_to_socket_id(qos_conf[i].rx_core); 467 uint32_t wt_sock = rte_lcore_to_socket_id(qos_conf[i].wt_core); 468 if (rx_sock != wt_sock) { 469 RTE_LOG(ERR, APP, "pfc %u: RX and WT must be on the same socket\n", i + 1); 470 return -1; 471 } 472 app_numa_mask |= 1 << rte_lcore_to_socket_id(qos_conf[i].rx_core); 473 } 474 475 return 0; 476 } 477 478