1e6541fdeSIntel /*- 2e6541fdeSIntel * BSD LICENSE 3e6541fdeSIntel * 4*e9d48c00SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5e6541fdeSIntel * All rights reserved. 6e6541fdeSIntel * 7e6541fdeSIntel * Redistribution and use in source and binary forms, with or without 8e6541fdeSIntel * modification, are permitted provided that the following conditions 9e6541fdeSIntel * are met: 10e6541fdeSIntel * 11e6541fdeSIntel * * Redistributions of source code must retain the above copyright 12e6541fdeSIntel * notice, this list of conditions and the following disclaimer. 13e6541fdeSIntel * * Redistributions in binary form must reproduce the above copyright 14e6541fdeSIntel * notice, this list of conditions and the following disclaimer in 15e6541fdeSIntel * the documentation and/or other materials provided with the 16e6541fdeSIntel * distribution. 17e6541fdeSIntel * * Neither the name of Intel Corporation nor the names of its 18e6541fdeSIntel * contributors may be used to endorse or promote products derived 19e6541fdeSIntel * from this software without specific prior written permission. 20e6541fdeSIntel * 21e6541fdeSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22e6541fdeSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23e6541fdeSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24e6541fdeSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25e6541fdeSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26e6541fdeSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27e6541fdeSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28e6541fdeSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29e6541fdeSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30e6541fdeSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31e6541fdeSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32e6541fdeSIntel */ 33e6541fdeSIntel 34e6541fdeSIntel #include <stdio.h> 35e6541fdeSIntel #include <getopt.h> 36e6541fdeSIntel 37e6541fdeSIntel #include <rte_common.h> 38e6541fdeSIntel #include <rte_eal.h> 39e6541fdeSIntel #include <rte_mempool.h> 40e6541fdeSIntel #include <rte_ethdev.h> 41e6541fdeSIntel #include <rte_cycles.h> 42e6541fdeSIntel #include <rte_mbuf.h> 43e6541fdeSIntel #include <rte_meter.h> 44e6541fdeSIntel 45e6541fdeSIntel /* 46e6541fdeSIntel * Traffic metering configuration 47e6541fdeSIntel * 48e6541fdeSIntel */ 49e6541fdeSIntel #define APP_MODE_FWD 0 50e6541fdeSIntel #define APP_MODE_SRTCM_COLOR_BLIND 1 51e6541fdeSIntel #define APP_MODE_SRTCM_COLOR_AWARE 2 52e6541fdeSIntel #define APP_MODE_TRTCM_COLOR_BLIND 3 53e6541fdeSIntel #define APP_MODE_TRTCM_COLOR_AWARE 4 54e6541fdeSIntel 55e6541fdeSIntel #define APP_MODE APP_MODE_SRTCM_COLOR_BLIND 56e6541fdeSIntel 57e6541fdeSIntel 58e6541fdeSIntel #include "main.h" 59e6541fdeSIntel 60e6541fdeSIntel 61e6541fdeSIntel #define APP_PKT_FLOW_POS 33 62e6541fdeSIntel #define APP_PKT_COLOR_POS 5 63e6541fdeSIntel 64e6541fdeSIntel 65e6541fdeSIntel #if APP_PKT_FLOW_POS > 64 || APP_PKT_COLOR_POS > 64 66e6541fdeSIntel #error Byte offset needs to be less than 64 67e6541fdeSIntel #endif 68e6541fdeSIntel 69e6541fdeSIntel /* 70e6541fdeSIntel * Buffer pool configuration 71e6541fdeSIntel * 72e6541fdeSIntel ***/ 73e6541fdeSIntel #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM) 74e6541fdeSIntel #define NB_MBUF 8192 75e6541fdeSIntel #define MEMPOOL_CACHE_SIZE 256 76e6541fdeSIntel 77e6541fdeSIntel static struct rte_mempool *pool = NULL; 78e6541fdeSIntel 79e6541fdeSIntel /* 80e6541fdeSIntel * NIC configuration 81e6541fdeSIntel * 82e6541fdeSIntel ***/ 83e6541fdeSIntel static struct rte_eth_conf port_conf = { 84e6541fdeSIntel .rxmode = { 85e6541fdeSIntel .max_rx_pkt_len = ETHER_MAX_LEN, 86e6541fdeSIntel .split_hdr_size = 0, 87e6541fdeSIntel .header_split = 0, 88e6541fdeSIntel .hw_ip_checksum = 1, 89e6541fdeSIntel .hw_vlan_filter = 0, 90e6541fdeSIntel .jumbo_frame = 0, 91e6541fdeSIntel .hw_strip_crc = 0, 92e6541fdeSIntel }, 93e6541fdeSIntel .rx_adv_conf = { 94e6541fdeSIntel .rss_conf = { 95e6541fdeSIntel .rss_key = NULL, 96e6541fdeSIntel .rss_hf = ETH_RSS_IPV4 | ETH_RSS_IPV6, 97e6541fdeSIntel }, 98e6541fdeSIntel }, 99e6541fdeSIntel .txmode = { 100e6541fdeSIntel .mq_mode = ETH_DCB_NONE, 101e6541fdeSIntel }, 102e6541fdeSIntel }; 103e6541fdeSIntel 104e6541fdeSIntel static const struct rte_eth_rxconf rx_conf = { 105e6541fdeSIntel .rx_thresh = { 106e6541fdeSIntel .pthresh = 8, /* RX prefetch threshold reg */ 107e6541fdeSIntel .hthresh = 8, /* RX host threshold reg */ 108e6541fdeSIntel .wthresh = 4, /* RX write-back threshold reg */ 109e6541fdeSIntel }, 110e6541fdeSIntel .rx_free_thresh = 32, 111e6541fdeSIntel }; 112e6541fdeSIntel 113e6541fdeSIntel static const struct rte_eth_txconf tx_conf = { 114e6541fdeSIntel .tx_thresh = { 115e6541fdeSIntel .pthresh = 36, /* TX prefetch threshold reg */ 116e6541fdeSIntel .hthresh = 0, /* TX host threshold reg */ 117e6541fdeSIntel .wthresh = 0, /* TX write-back threshold reg */ 118e6541fdeSIntel }, 119e6541fdeSIntel .tx_free_thresh = 0, 120e6541fdeSIntel .tx_rs_thresh = 0, 121e6541fdeSIntel .txq_flags = 0x0, 122e6541fdeSIntel }; 123e6541fdeSIntel 124e6541fdeSIntel #define NIC_RX_QUEUE_DESC 128 125e6541fdeSIntel #define NIC_TX_QUEUE_DESC 512 126e6541fdeSIntel 127e6541fdeSIntel #define NIC_RX_QUEUE 0 128e6541fdeSIntel #define NIC_TX_QUEUE 0 129e6541fdeSIntel 130e6541fdeSIntel /* 131e6541fdeSIntel * Packet RX/TX 132e6541fdeSIntel * 133e6541fdeSIntel ***/ 134e6541fdeSIntel #define PKT_RX_BURST_MAX 32 135e6541fdeSIntel #define PKT_TX_BURST_MAX 32 136e6541fdeSIntel #define TIME_TX_DRAIN 200000ULL 137e6541fdeSIntel 138e6541fdeSIntel static uint8_t port_rx; 139e6541fdeSIntel static uint8_t port_tx; 140e6541fdeSIntel static struct rte_mbuf *pkts_rx[PKT_RX_BURST_MAX]; 141e6541fdeSIntel static struct rte_mbuf *pkts_tx[PKT_TX_BURST_MAX]; 142e6541fdeSIntel static uint16_t pkts_tx_len = 0; 143e6541fdeSIntel 144e6541fdeSIntel 145e6541fdeSIntel struct rte_meter_srtcm_params app_srtcm_params[] = { 146e6541fdeSIntel {.cir = 1000000 * 46, .cbs = 2048, .ebs = 2048}, 147e6541fdeSIntel }; 148e6541fdeSIntel 149e6541fdeSIntel struct rte_meter_trtcm_params app_trtcm_params[] = { 150e6541fdeSIntel {.cir = 1000000 * 46, .pir = 1500000 * 46, .cbs = 2048, .pbs = 2048}, 151e6541fdeSIntel }; 152e6541fdeSIntel 153e6541fdeSIntel #define DIM(a) (sizeof (a) / sizeof ((a)[0])) 154e6541fdeSIntel #define APP_FLOWS_MAX 256 155e6541fdeSIntel 156e6541fdeSIntel FLOW_METER app_flows[APP_FLOWS_MAX]; 157e6541fdeSIntel 158e6541fdeSIntel static void 159e6541fdeSIntel app_configure_flow_table(void) 160e6541fdeSIntel { 161e6541fdeSIntel uint32_t i, j; 162e6541fdeSIntel 163e6541fdeSIntel for (i = 0, j = 0; i < APP_FLOWS_MAX; i ++, j = (j + 1) % DIM(PARAMS)){ 164e6541fdeSIntel FUNC_CONFIG(&app_flows[i], &PARAMS[j]); 165e6541fdeSIntel } 166e6541fdeSIntel } 167e6541fdeSIntel 168e6541fdeSIntel static inline void 169fc8a10d8SIntel app_set_pkt_color(uint8_t *pkt_data, enum policer_action color) 170fc8a10d8SIntel { 171fc8a10d8SIntel pkt_data[APP_PKT_COLOR_POS] = (uint8_t)color; 172fc8a10d8SIntel } 173fc8a10d8SIntel 174fc8a10d8SIntel static inline int 175e6541fdeSIntel app_pkt_handle(struct rte_mbuf *pkt, uint64_t time) 176e6541fdeSIntel { 177fc8a10d8SIntel uint8_t input_color, output_color; 178e6541fdeSIntel uint8_t *pkt_data = rte_pktmbuf_mtod(pkt, uint8_t *); 179e6541fdeSIntel uint32_t pkt_len = rte_pktmbuf_pkt_len(pkt) - sizeof(struct ether_hdr); 180e6541fdeSIntel uint8_t flow_id = (uint8_t)(pkt_data[APP_PKT_FLOW_POS] & (APP_FLOWS_MAX - 1)); 181fc8a10d8SIntel input_color = pkt_data[APP_PKT_COLOR_POS]; 182fc8a10d8SIntel enum policer_action action; 183e6541fdeSIntel 184e6541fdeSIntel /* color input is not used for blind modes */ 185fc8a10d8SIntel output_color = (uint8_t) FUNC_METER(&app_flows[flow_id], time, pkt_len, 186fc8a10d8SIntel (enum rte_meter_color) input_color); 187fc8a10d8SIntel 188fc8a10d8SIntel /* Apply policing and set the output color */ 189fc8a10d8SIntel action = policer_table[input_color][output_color]; 190fc8a10d8SIntel app_set_pkt_color(pkt_data, action); 191fc8a10d8SIntel 192fc8a10d8SIntel return action; 193e6541fdeSIntel } 194e6541fdeSIntel 195e6541fdeSIntel 196e6541fdeSIntel static __attribute__((noreturn)) int 197e6541fdeSIntel main_loop(__attribute__((unused)) void *dummy) 198e6541fdeSIntel { 199e6541fdeSIntel uint64_t current_time, last_time = rte_rdtsc(); 200e6541fdeSIntel uint32_t lcore_id = rte_lcore_id(); 201e6541fdeSIntel 202e6541fdeSIntel printf("Core %u: port RX = %d, port TX = %d\n", lcore_id, port_rx, port_tx); 203e6541fdeSIntel 204e6541fdeSIntel while (1) { 205e6541fdeSIntel uint64_t time_diff; 206e6541fdeSIntel int i, nb_rx; 207e6541fdeSIntel 208e6541fdeSIntel /* Mechanism to avoid stale packets in the output buffer */ 209e6541fdeSIntel current_time = rte_rdtsc(); 210e6541fdeSIntel time_diff = current_time - last_time; 211e6541fdeSIntel if (unlikely(time_diff > TIME_TX_DRAIN)) { 212e6541fdeSIntel int ret; 213e6541fdeSIntel 214e6541fdeSIntel if (pkts_tx_len == 0) { 215e6541fdeSIntel last_time = current_time; 216e6541fdeSIntel 217e6541fdeSIntel continue; 218e6541fdeSIntel } 219e6541fdeSIntel 220e6541fdeSIntel /* Write packet burst to NIC TX */ 221e6541fdeSIntel ret = rte_eth_tx_burst(port_tx, NIC_TX_QUEUE, pkts_tx, pkts_tx_len); 222e6541fdeSIntel 223e6541fdeSIntel /* Free buffers for any packets not written successfully */ 224e6541fdeSIntel if (unlikely(ret < pkts_tx_len)) { 225e6541fdeSIntel for ( ; ret < pkts_tx_len; ret ++) { 226e6541fdeSIntel rte_pktmbuf_free(pkts_tx[ret]); 227e6541fdeSIntel } 228e6541fdeSIntel } 229e6541fdeSIntel 230e6541fdeSIntel /* Empty the output buffer */ 231e6541fdeSIntel pkts_tx_len = 0; 232e6541fdeSIntel 233e6541fdeSIntel last_time = current_time; 234e6541fdeSIntel } 235e6541fdeSIntel 236e6541fdeSIntel /* Read packet burst from NIC RX */ 237e6541fdeSIntel nb_rx = rte_eth_rx_burst(port_rx, NIC_RX_QUEUE, pkts_rx, PKT_RX_BURST_MAX); 238e6541fdeSIntel 239e6541fdeSIntel /* Handle packets */ 240e6541fdeSIntel for (i = 0; i < nb_rx; i ++) { 241e6541fdeSIntel struct rte_mbuf *pkt = pkts_rx[i]; 242e6541fdeSIntel 243e6541fdeSIntel /* Handle current packet */ 244fc8a10d8SIntel if (app_pkt_handle(pkt, current_time) == DROP) 245fc8a10d8SIntel rte_pktmbuf_free(pkt); 246fc8a10d8SIntel else { 247e6541fdeSIntel pkts_tx[pkts_tx_len] = pkt; 248e6541fdeSIntel pkts_tx_len ++; 249fc8a10d8SIntel } 250e6541fdeSIntel 251e6541fdeSIntel /* Write packets from output buffer to NIC TX when full burst is available */ 252e6541fdeSIntel if (unlikely(pkts_tx_len == PKT_TX_BURST_MAX)) { 253e6541fdeSIntel /* Write packet burst to NIC TX */ 254e6541fdeSIntel int ret = rte_eth_tx_burst(port_tx, NIC_TX_QUEUE, pkts_tx, PKT_TX_BURST_MAX); 255e6541fdeSIntel 256e6541fdeSIntel /* Free buffers for any packets not written successfully */ 257e6541fdeSIntel if (unlikely(ret < PKT_TX_BURST_MAX)) { 258e6541fdeSIntel for ( ; ret < PKT_TX_BURST_MAX; ret ++) { 259e6541fdeSIntel rte_pktmbuf_free(pkts_tx[ret]); 260e6541fdeSIntel } 261e6541fdeSIntel } 262e6541fdeSIntel 263e6541fdeSIntel /* Empty the output buffer */ 264e6541fdeSIntel pkts_tx_len = 0; 265e6541fdeSIntel } 266e6541fdeSIntel } 267e6541fdeSIntel } 268e6541fdeSIntel } 269e6541fdeSIntel 270e6541fdeSIntel static void 271e6541fdeSIntel print_usage(const char *prgname) 272e6541fdeSIntel { 273e6541fdeSIntel printf ("%s [EAL options] -- -p PORTMASK\n" 274e6541fdeSIntel " -p PORTMASK: hexadecimal bitmask of ports to configure\n", 275e6541fdeSIntel prgname); 276e6541fdeSIntel } 277e6541fdeSIntel 278e6541fdeSIntel static int 279e6541fdeSIntel parse_portmask(const char *portmask) 280e6541fdeSIntel { 281e6541fdeSIntel char *end = NULL; 282e6541fdeSIntel unsigned long pm; 283e6541fdeSIntel 284e6541fdeSIntel /* parse hexadecimal string */ 285e6541fdeSIntel pm = strtoul(portmask, &end, 16); 286e6541fdeSIntel if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0')) 287e6541fdeSIntel return -1; 288e6541fdeSIntel 289e6541fdeSIntel if (pm == 0) 290e6541fdeSIntel return -1; 291e6541fdeSIntel 292e6541fdeSIntel return pm; 293e6541fdeSIntel } 294e6541fdeSIntel 295e6541fdeSIntel /* Parse the argument given in the command line of the application */ 296e6541fdeSIntel static int 297e6541fdeSIntel parse_args(int argc, char **argv) 298e6541fdeSIntel { 299e6541fdeSIntel int opt; 300e6541fdeSIntel char **argvopt; 301e6541fdeSIntel int option_index; 302e6541fdeSIntel char *prgname = argv[0]; 303e6541fdeSIntel static struct option lgopts[] = { 304e6541fdeSIntel {NULL, 0, 0, 0} 305e6541fdeSIntel }; 306e6541fdeSIntel uint64_t port_mask, i, mask; 307e6541fdeSIntel 308e6541fdeSIntel argvopt = argv; 309e6541fdeSIntel 310e6541fdeSIntel while ((opt = getopt_long(argc, argvopt, "p:", lgopts, &option_index)) != EOF) { 311e6541fdeSIntel switch (opt) { 312e6541fdeSIntel case 'p': 313e6541fdeSIntel port_mask = parse_portmask(optarg); 314e6541fdeSIntel if (port_mask == 0) { 315e6541fdeSIntel printf("invalid port mask (null port mask)\n"); 316e6541fdeSIntel print_usage(prgname); 317e6541fdeSIntel return -1; 318e6541fdeSIntel } 319e6541fdeSIntel 320e6541fdeSIntel for (i = 0, mask = 1; i < 64; i ++, mask <<= 1){ 321e6541fdeSIntel if (mask & port_mask){ 322e6541fdeSIntel port_rx = i; 323e6541fdeSIntel port_mask &= ~ mask; 324e6541fdeSIntel break; 325e6541fdeSIntel } 326e6541fdeSIntel } 327e6541fdeSIntel 328e6541fdeSIntel for (i = 0, mask = 1; i < 64; i ++, mask <<= 1){ 329e6541fdeSIntel if (mask & port_mask){ 330e6541fdeSIntel port_tx = i; 331e6541fdeSIntel port_mask &= ~ mask; 332e6541fdeSIntel break; 333e6541fdeSIntel } 334e6541fdeSIntel } 335e6541fdeSIntel 336e6541fdeSIntel if (port_mask != 0) { 337e6541fdeSIntel printf("invalid port mask (more than 2 ports)\n"); 338e6541fdeSIntel print_usage(prgname); 339e6541fdeSIntel return -1; 340e6541fdeSIntel } 341e6541fdeSIntel break; 342e6541fdeSIntel 343e6541fdeSIntel default: 344e6541fdeSIntel print_usage(prgname); 345e6541fdeSIntel return -1; 346e6541fdeSIntel } 347e6541fdeSIntel } 348e6541fdeSIntel 349e6541fdeSIntel if (optind <= 1) { 350e6541fdeSIntel print_usage(prgname); 351e6541fdeSIntel return -1; 352e6541fdeSIntel } 353e6541fdeSIntel 354e6541fdeSIntel argv[optind-1] = prgname; 355e6541fdeSIntel 356e6541fdeSIntel optind = 0; /* reset getopt lib */ 357e6541fdeSIntel return 0; 358e6541fdeSIntel } 359e6541fdeSIntel 360e6541fdeSIntel int 361e6541fdeSIntel MAIN(int argc, char **argv) 362e6541fdeSIntel { 363e6541fdeSIntel uint32_t lcore_id; 364e6541fdeSIntel int ret; 365e6541fdeSIntel 366e6541fdeSIntel /* EAL init */ 367e6541fdeSIntel ret = rte_eal_init(argc, argv); 368e6541fdeSIntel if (ret < 0) 369e6541fdeSIntel rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n"); 370e6541fdeSIntel argc -= ret; 371e6541fdeSIntel argv += ret; 372e6541fdeSIntel if (rte_lcore_count() != 1) { 373e6541fdeSIntel rte_exit(EXIT_FAILURE, "This application does not accept more than one core. " 374e6541fdeSIntel "Please adjust the \"-c COREMASK\" parameter accordingly.\n"); 375e6541fdeSIntel } 376e6541fdeSIntel 377e6541fdeSIntel /* Application non-EAL arguments parse */ 378e6541fdeSIntel ret = parse_args(argc, argv); 379e6541fdeSIntel if (ret < 0) 380e6541fdeSIntel rte_exit(EXIT_FAILURE, "Invalid input arguments\n"); 381e6541fdeSIntel 382e6541fdeSIntel /* Buffer pool init */ 383e6541fdeSIntel pool = rte_mempool_create("pool", NB_MBUF, MBUF_SIZE, MEMPOOL_CACHE_SIZE, 384e6541fdeSIntel sizeof(struct rte_pktmbuf_pool_private), rte_pktmbuf_pool_init, NULL, 385e6541fdeSIntel rte_pktmbuf_init, NULL, rte_socket_id(), 0); 386e6541fdeSIntel if (pool == NULL) 387e6541fdeSIntel rte_exit(EXIT_FAILURE, "Buffer pool creation error\n"); 388e6541fdeSIntel 389e6541fdeSIntel /* PMD init */ 390e6541fdeSIntel if (rte_pmd_init_all() < 0) 391e6541fdeSIntel rte_exit(EXIT_FAILURE, "PMD init error\n"); 392e6541fdeSIntel 393e6541fdeSIntel if (rte_eal_pci_probe() < 0) 394e6541fdeSIntel rte_exit(EXIT_FAILURE, "PCI probe error\n"); 395e6541fdeSIntel 396e6541fdeSIntel /* NIC init */ 397e6541fdeSIntel ret = rte_eth_dev_configure(port_rx, 1, 1, &port_conf); 398e6541fdeSIntel if (ret < 0) 399e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d configuration error (%d)\n", port_rx, ret); 400e6541fdeSIntel 401e6541fdeSIntel ret = rte_eth_rx_queue_setup(port_rx, NIC_RX_QUEUE, NIC_RX_QUEUE_DESC, rte_eth_dev_socket_id(port_rx), &rx_conf, pool); 402e6541fdeSIntel if (ret < 0) 403e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d RX queue setup error (%d)\n", port_rx, ret); 404e6541fdeSIntel 405e6541fdeSIntel ret = rte_eth_tx_queue_setup(port_rx, NIC_TX_QUEUE, NIC_TX_QUEUE_DESC, rte_eth_dev_socket_id(port_rx), &tx_conf); 406e6541fdeSIntel if (ret < 0) 407e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d TX queue setup error (%d)\n", port_rx, ret); 408e6541fdeSIntel 409e6541fdeSIntel ret = rte_eth_dev_configure(port_tx, 1, 1, &port_conf); 410e6541fdeSIntel if (ret < 0) 411e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d configuration error (%d)\n", port_tx, ret); 412e6541fdeSIntel 413e6541fdeSIntel ret = rte_eth_rx_queue_setup(port_tx, NIC_RX_QUEUE, NIC_RX_QUEUE_DESC, rte_eth_dev_socket_id(port_tx), &rx_conf, pool); 414e6541fdeSIntel if (ret < 0) 415e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d RX queue setup error (%d)\n", port_tx, ret); 416e6541fdeSIntel 417e6541fdeSIntel ret = rte_eth_tx_queue_setup(port_tx, NIC_TX_QUEUE, NIC_TX_QUEUE_DESC, rte_eth_dev_socket_id(port_tx), &tx_conf); 418e6541fdeSIntel if (ret < 0) 419e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d TX queue setup error (%d)\n", port_tx, ret); 420e6541fdeSIntel 421e6541fdeSIntel ret = rte_eth_dev_start(port_rx); 422e6541fdeSIntel if (ret < 0) 423e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d start error (%d)\n", port_rx, ret); 424e6541fdeSIntel 425e6541fdeSIntel ret = rte_eth_dev_start(port_tx); 426e6541fdeSIntel if (ret < 0) 427e6541fdeSIntel rte_exit(EXIT_FAILURE, "Port %d start error (%d)\n", port_tx, ret); 428e6541fdeSIntel 429e6541fdeSIntel rte_eth_promiscuous_enable(port_rx); 430e6541fdeSIntel 431e6541fdeSIntel rte_eth_promiscuous_enable(port_tx); 432e6541fdeSIntel 433e6541fdeSIntel /* App configuration */ 434e6541fdeSIntel app_configure_flow_table(); 435e6541fdeSIntel 436e6541fdeSIntel /* Launch per-lcore init on every lcore */ 437e6541fdeSIntel rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER); 438e6541fdeSIntel RTE_LCORE_FOREACH_SLAVE(lcore_id) { 439e6541fdeSIntel if (rte_eal_wait_lcore(lcore_id) < 0) 440e6541fdeSIntel return -1; 441e6541fdeSIntel } 442e6541fdeSIntel 443e6541fdeSIntel return 0; 444e6541fdeSIntel } 445