xref: /dpdk/examples/qos_meter/main.c (revision 98a1648109b8dbaa4e6b821c17d1f6bd86d33a9a)
1e6541fdeSIntel /*-
2e6541fdeSIntel  *   BSD LICENSE
3e6541fdeSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5e6541fdeSIntel  *   All rights reserved.
6e6541fdeSIntel  *
7e6541fdeSIntel  *   Redistribution and use in source and binary forms, with or without
8e6541fdeSIntel  *   modification, are permitted provided that the following conditions
9e6541fdeSIntel  *   are met:
10e6541fdeSIntel  *
11e6541fdeSIntel  *     * Redistributions of source code must retain the above copyright
12e6541fdeSIntel  *       notice, this list of conditions and the following disclaimer.
13e6541fdeSIntel  *     * Redistributions in binary form must reproduce the above copyright
14e6541fdeSIntel  *       notice, this list of conditions and the following disclaimer in
15e6541fdeSIntel  *       the documentation and/or other materials provided with the
16e6541fdeSIntel  *       distribution.
17e6541fdeSIntel  *     * Neither the name of Intel Corporation nor the names of its
18e6541fdeSIntel  *       contributors may be used to endorse or promote products derived
19e6541fdeSIntel  *       from this software without specific prior written permission.
20e6541fdeSIntel  *
21e6541fdeSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22e6541fdeSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23e6541fdeSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24e6541fdeSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25e6541fdeSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26e6541fdeSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27e6541fdeSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28e6541fdeSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29e6541fdeSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30e6541fdeSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31e6541fdeSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32e6541fdeSIntel  */
33e6541fdeSIntel 
34e6541fdeSIntel #include <stdio.h>
35e6541fdeSIntel #include <getopt.h>
36e6541fdeSIntel 
37e6541fdeSIntel #include <rte_common.h>
38e6541fdeSIntel #include <rte_eal.h>
39e6541fdeSIntel #include <rte_mempool.h>
40e6541fdeSIntel #include <rte_ethdev.h>
41e6541fdeSIntel #include <rte_cycles.h>
42e6541fdeSIntel #include <rte_mbuf.h>
43e6541fdeSIntel #include <rte_meter.h>
44e6541fdeSIntel 
45e6541fdeSIntel /*
46e6541fdeSIntel  * Traffic metering configuration
47e6541fdeSIntel  *
48e6541fdeSIntel  */
49e6541fdeSIntel #define APP_MODE_FWD                    0
50e6541fdeSIntel #define APP_MODE_SRTCM_COLOR_BLIND      1
51e6541fdeSIntel #define APP_MODE_SRTCM_COLOR_AWARE      2
52e6541fdeSIntel #define APP_MODE_TRTCM_COLOR_BLIND      3
53e6541fdeSIntel #define APP_MODE_TRTCM_COLOR_AWARE      4
54e6541fdeSIntel 
55e6541fdeSIntel #define APP_MODE	APP_MODE_SRTCM_COLOR_BLIND
56e6541fdeSIntel 
57e6541fdeSIntel 
58e6541fdeSIntel #include "main.h"
59e6541fdeSIntel 
60e6541fdeSIntel 
61e6541fdeSIntel #define APP_PKT_FLOW_POS                33
62e6541fdeSIntel #define APP_PKT_COLOR_POS               5
63e6541fdeSIntel 
64e6541fdeSIntel 
65e6541fdeSIntel #if APP_PKT_FLOW_POS > 64 || APP_PKT_COLOR_POS > 64
66e6541fdeSIntel #error Byte offset needs to be less than 64
67e6541fdeSIntel #endif
68e6541fdeSIntel 
69e6541fdeSIntel /*
70e6541fdeSIntel  * Buffer pool configuration
71e6541fdeSIntel  *
72e6541fdeSIntel  ***/
73e6541fdeSIntel #define MBUF_SIZE           (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
74e6541fdeSIntel #define NB_MBUF             8192
75e6541fdeSIntel #define MEMPOOL_CACHE_SIZE  256
76e6541fdeSIntel 
77e6541fdeSIntel static struct rte_mempool *pool = NULL;
78e6541fdeSIntel 
79e6541fdeSIntel /*
80e6541fdeSIntel  * NIC configuration
81e6541fdeSIntel  *
82e6541fdeSIntel  ***/
83e6541fdeSIntel static struct rte_eth_conf port_conf = {
84e6541fdeSIntel 	.rxmode = {
8513c4ebd6SBruce Richardson 		.mq_mode	= ETH_MQ_RX_RSS,
86e6541fdeSIntel 		.max_rx_pkt_len = ETHER_MAX_LEN,
87e6541fdeSIntel 		.split_hdr_size = 0,
88e6541fdeSIntel 		.header_split   = 0,
89e6541fdeSIntel 		.hw_ip_checksum = 1,
90e6541fdeSIntel 		.hw_vlan_filter = 0,
91e6541fdeSIntel 		.jumbo_frame    = 0,
92e6541fdeSIntel 		.hw_strip_crc   = 0,
93e6541fdeSIntel 	},
94e6541fdeSIntel 	.rx_adv_conf = {
95e6541fdeSIntel 		.rss_conf = {
96e6541fdeSIntel 			.rss_key = NULL,
978a387fa8SHelin Zhang 			.rss_hf = ETH_RSS_IP,
98e6541fdeSIntel 		},
99e6541fdeSIntel 	},
100e6541fdeSIntel 	.txmode = {
101e6541fdeSIntel 		.mq_mode = ETH_DCB_NONE,
102e6541fdeSIntel 	},
103e6541fdeSIntel };
104e6541fdeSIntel 
105e6541fdeSIntel #define NIC_RX_QUEUE_DESC               128
106e6541fdeSIntel #define NIC_TX_QUEUE_DESC               512
107e6541fdeSIntel 
108e6541fdeSIntel #define NIC_RX_QUEUE                    0
109e6541fdeSIntel #define NIC_TX_QUEUE                    0
110e6541fdeSIntel 
111e6541fdeSIntel /*
112e6541fdeSIntel  * Packet RX/TX
113e6541fdeSIntel  *
114e6541fdeSIntel  ***/
115e6541fdeSIntel #define PKT_RX_BURST_MAX                32
116e6541fdeSIntel #define PKT_TX_BURST_MAX                32
117e6541fdeSIntel #define TIME_TX_DRAIN                   200000ULL
118e6541fdeSIntel 
119e6541fdeSIntel static uint8_t port_rx;
120e6541fdeSIntel static uint8_t port_tx;
121e6541fdeSIntel static struct rte_mbuf *pkts_rx[PKT_RX_BURST_MAX];
122e6541fdeSIntel static struct rte_mbuf *pkts_tx[PKT_TX_BURST_MAX];
123e6541fdeSIntel static uint16_t pkts_tx_len = 0;
124e6541fdeSIntel 
125e6541fdeSIntel 
126e6541fdeSIntel struct rte_meter_srtcm_params app_srtcm_params[] = {
127e6541fdeSIntel 	{.cir = 1000000 * 46,  .cbs = 2048, .ebs = 2048},
128e6541fdeSIntel };
129e6541fdeSIntel 
130e6541fdeSIntel struct rte_meter_trtcm_params app_trtcm_params[] = {
131e6541fdeSIntel 	{.cir = 1000000 * 46,  .pir = 1500000 * 46,  .cbs = 2048, .pbs = 2048},
132e6541fdeSIntel };
133e6541fdeSIntel 
134e6541fdeSIntel #define APP_FLOWS_MAX  256
135e6541fdeSIntel 
136e6541fdeSIntel FLOW_METER app_flows[APP_FLOWS_MAX];
137e6541fdeSIntel 
138e6541fdeSIntel static void
139e6541fdeSIntel app_configure_flow_table(void)
140e6541fdeSIntel {
141e6541fdeSIntel 	uint32_t i, j;
142e6541fdeSIntel 
14313c4ebd6SBruce Richardson 	for (i = 0, j = 0; i < APP_FLOWS_MAX; i ++, j = (j + 1) % RTE_DIM(PARAMS)){
144e6541fdeSIntel 		FUNC_CONFIG(&app_flows[i], &PARAMS[j]);
145e6541fdeSIntel 	}
146e6541fdeSIntel }
147e6541fdeSIntel 
148e6541fdeSIntel static inline void
149fc8a10d8SIntel app_set_pkt_color(uint8_t *pkt_data, enum policer_action color)
150fc8a10d8SIntel {
151fc8a10d8SIntel 	pkt_data[APP_PKT_COLOR_POS] = (uint8_t)color;
152fc8a10d8SIntel }
153fc8a10d8SIntel 
154fc8a10d8SIntel static inline int
155e6541fdeSIntel app_pkt_handle(struct rte_mbuf *pkt, uint64_t time)
156e6541fdeSIntel {
157fc8a10d8SIntel 	uint8_t input_color, output_color;
158e6541fdeSIntel 	uint8_t *pkt_data = rte_pktmbuf_mtod(pkt, uint8_t *);
159e6541fdeSIntel 	uint32_t pkt_len = rte_pktmbuf_pkt_len(pkt) - sizeof(struct ether_hdr);
160e6541fdeSIntel 	uint8_t flow_id = (uint8_t)(pkt_data[APP_PKT_FLOW_POS] & (APP_FLOWS_MAX - 1));
161fc8a10d8SIntel 	input_color = pkt_data[APP_PKT_COLOR_POS];
162fc8a10d8SIntel 	enum policer_action action;
163e6541fdeSIntel 
164e6541fdeSIntel 	/* color input is not used for blind modes */
165fc8a10d8SIntel 	output_color = (uint8_t) FUNC_METER(&app_flows[flow_id], time, pkt_len,
166fc8a10d8SIntel 		(enum rte_meter_color) input_color);
167fc8a10d8SIntel 
168fc8a10d8SIntel 	/* Apply policing and set the output color */
169fc8a10d8SIntel 	action = policer_table[input_color][output_color];
170fc8a10d8SIntel 	app_set_pkt_color(pkt_data, action);
171fc8a10d8SIntel 
172fc8a10d8SIntel 	return action;
173e6541fdeSIntel }
174e6541fdeSIntel 
175e6541fdeSIntel 
176e6541fdeSIntel static __attribute__((noreturn)) int
177e6541fdeSIntel main_loop(__attribute__((unused)) void *dummy)
178e6541fdeSIntel {
179e6541fdeSIntel 	uint64_t current_time, last_time = rte_rdtsc();
180e6541fdeSIntel 	uint32_t lcore_id = rte_lcore_id();
181e6541fdeSIntel 
182e6541fdeSIntel 	printf("Core %u: port RX = %d, port TX = %d\n", lcore_id, port_rx, port_tx);
183e6541fdeSIntel 
184e6541fdeSIntel 	while (1) {
185e6541fdeSIntel 		uint64_t time_diff;
186e6541fdeSIntel 		int i, nb_rx;
187e6541fdeSIntel 
188e6541fdeSIntel 		/* Mechanism to avoid stale packets in the output buffer */
189e6541fdeSIntel 		current_time = rte_rdtsc();
190e6541fdeSIntel 		time_diff = current_time - last_time;
191e6541fdeSIntel 		if (unlikely(time_diff > TIME_TX_DRAIN)) {
192e6541fdeSIntel 			int ret;
193e6541fdeSIntel 
194e6541fdeSIntel 			if (pkts_tx_len == 0) {
195e6541fdeSIntel 				last_time = current_time;
196e6541fdeSIntel 
197e6541fdeSIntel 				continue;
198e6541fdeSIntel 			}
199e6541fdeSIntel 
200e6541fdeSIntel 			/* Write packet burst to NIC TX */
201e6541fdeSIntel 			ret = rte_eth_tx_burst(port_tx, NIC_TX_QUEUE, pkts_tx, pkts_tx_len);
202e6541fdeSIntel 
203e6541fdeSIntel 			/* Free buffers for any packets not written successfully */
204e6541fdeSIntel 			if (unlikely(ret < pkts_tx_len)) {
205e6541fdeSIntel 				for ( ; ret < pkts_tx_len; ret ++) {
206e6541fdeSIntel 					rte_pktmbuf_free(pkts_tx[ret]);
207e6541fdeSIntel 				}
208e6541fdeSIntel 			}
209e6541fdeSIntel 
210e6541fdeSIntel 			/* Empty the output buffer */
211e6541fdeSIntel 			pkts_tx_len = 0;
212e6541fdeSIntel 
213e6541fdeSIntel 			last_time = current_time;
214e6541fdeSIntel 		}
215e6541fdeSIntel 
216e6541fdeSIntel 		/* Read packet burst from NIC RX */
217e6541fdeSIntel 		nb_rx = rte_eth_rx_burst(port_rx, NIC_RX_QUEUE, pkts_rx, PKT_RX_BURST_MAX);
218e6541fdeSIntel 
219e6541fdeSIntel 		/* Handle packets */
220e6541fdeSIntel 		for (i = 0; i < nb_rx; i ++) {
221e6541fdeSIntel 			struct rte_mbuf *pkt = pkts_rx[i];
222e6541fdeSIntel 
223e6541fdeSIntel 			/* Handle current packet */
224fc8a10d8SIntel 			if (app_pkt_handle(pkt, current_time) == DROP)
225fc8a10d8SIntel 				rte_pktmbuf_free(pkt);
226fc8a10d8SIntel 			else {
227e6541fdeSIntel 				pkts_tx[pkts_tx_len] = pkt;
228e6541fdeSIntel 				pkts_tx_len ++;
229fc8a10d8SIntel 			}
230e6541fdeSIntel 
231e6541fdeSIntel 			/* Write packets from output buffer to NIC TX when full burst is available */
232e6541fdeSIntel 			if (unlikely(pkts_tx_len == PKT_TX_BURST_MAX)) {
233e6541fdeSIntel 				/* Write packet burst to NIC TX */
234e6541fdeSIntel 				int ret = rte_eth_tx_burst(port_tx, NIC_TX_QUEUE, pkts_tx, PKT_TX_BURST_MAX);
235e6541fdeSIntel 
236e6541fdeSIntel 				/* Free buffers for any packets not written successfully */
237e6541fdeSIntel 				if (unlikely(ret < PKT_TX_BURST_MAX)) {
238e6541fdeSIntel 					for ( ; ret < PKT_TX_BURST_MAX; ret ++) {
239e6541fdeSIntel 						rte_pktmbuf_free(pkts_tx[ret]);
240e6541fdeSIntel 					}
241e6541fdeSIntel 				}
242e6541fdeSIntel 
243e6541fdeSIntel 				/* Empty the output buffer */
244e6541fdeSIntel 				pkts_tx_len = 0;
245e6541fdeSIntel 			}
246e6541fdeSIntel 		}
247e6541fdeSIntel 	}
248e6541fdeSIntel }
249e6541fdeSIntel 
250e6541fdeSIntel static void
251e6541fdeSIntel print_usage(const char *prgname)
252e6541fdeSIntel {
253e6541fdeSIntel 	printf ("%s [EAL options] -- -p PORTMASK\n"
254e6541fdeSIntel 		"  -p PORTMASK: hexadecimal bitmask of ports to configure\n",
255e6541fdeSIntel 		prgname);
256e6541fdeSIntel }
257e6541fdeSIntel 
258e6541fdeSIntel static int
259e6541fdeSIntel parse_portmask(const char *portmask)
260e6541fdeSIntel {
261e6541fdeSIntel 	char *end = NULL;
262e6541fdeSIntel 	unsigned long pm;
263e6541fdeSIntel 
264e6541fdeSIntel 	/* parse hexadecimal string */
265e6541fdeSIntel 	pm = strtoul(portmask, &end, 16);
266e6541fdeSIntel 	if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
267e6541fdeSIntel 		return -1;
268e6541fdeSIntel 
269e6541fdeSIntel 	if (pm == 0)
270e6541fdeSIntel 		return -1;
271e6541fdeSIntel 
272e6541fdeSIntel 	return pm;
273e6541fdeSIntel }
274e6541fdeSIntel 
275e6541fdeSIntel /* Parse the argument given in the command line of the application */
276e6541fdeSIntel static int
277e6541fdeSIntel parse_args(int argc, char **argv)
278e6541fdeSIntel {
279e6541fdeSIntel 	int opt;
280e6541fdeSIntel 	char **argvopt;
281e6541fdeSIntel 	int option_index;
282e6541fdeSIntel 	char *prgname = argv[0];
283e6541fdeSIntel 	static struct option lgopts[] = {
284e6541fdeSIntel 		{NULL, 0, 0, 0}
285e6541fdeSIntel 	};
286e6541fdeSIntel 	uint64_t port_mask, i, mask;
287e6541fdeSIntel 
288e6541fdeSIntel 	argvopt = argv;
289e6541fdeSIntel 
290e6541fdeSIntel 	while ((opt = getopt_long(argc, argvopt, "p:", lgopts, &option_index)) != EOF) {
291e6541fdeSIntel 		switch (opt) {
292e6541fdeSIntel 		case 'p':
293e6541fdeSIntel 			port_mask = parse_portmask(optarg);
294e6541fdeSIntel 			if (port_mask == 0) {
295e6541fdeSIntel 				printf("invalid port mask (null port mask)\n");
296e6541fdeSIntel 				print_usage(prgname);
297e6541fdeSIntel 				return -1;
298e6541fdeSIntel 			}
299e6541fdeSIntel 
300e6541fdeSIntel 			for (i = 0, mask = 1; i < 64; i ++, mask <<= 1){
301e6541fdeSIntel 				if (mask & port_mask){
302e6541fdeSIntel 					port_rx = i;
303e6541fdeSIntel 					port_mask &= ~ mask;
304e6541fdeSIntel 					break;
305e6541fdeSIntel 				}
306e6541fdeSIntel 			}
307e6541fdeSIntel 
308e6541fdeSIntel 			for (i = 0, mask = 1; i < 64; i ++, mask <<= 1){
309e6541fdeSIntel 				if (mask & port_mask){
310e6541fdeSIntel 					port_tx = i;
311e6541fdeSIntel 					port_mask &= ~ mask;
312e6541fdeSIntel 					break;
313e6541fdeSIntel 				}
314e6541fdeSIntel 			}
315e6541fdeSIntel 
316e6541fdeSIntel 			if (port_mask != 0) {
317e6541fdeSIntel 				printf("invalid port mask (more than 2 ports)\n");
318e6541fdeSIntel 				print_usage(prgname);
319e6541fdeSIntel 				return -1;
320e6541fdeSIntel 			}
321e6541fdeSIntel 			break;
322e6541fdeSIntel 
323e6541fdeSIntel 		default:
324e6541fdeSIntel 			print_usage(prgname);
325e6541fdeSIntel 			return -1;
326e6541fdeSIntel 		}
327e6541fdeSIntel 	}
328e6541fdeSIntel 
329e6541fdeSIntel 	if (optind <= 1) {
330e6541fdeSIntel 		print_usage(prgname);
331e6541fdeSIntel 		return -1;
332e6541fdeSIntel 	}
333e6541fdeSIntel 
334e6541fdeSIntel 	argv[optind-1] = prgname;
335e6541fdeSIntel 
336e6541fdeSIntel 	optind = 0; /* reset getopt lib */
337e6541fdeSIntel 	return 0;
338e6541fdeSIntel }
339e6541fdeSIntel 
340e6541fdeSIntel int
341*98a16481SDavid Marchand main(int argc, char **argv)
342e6541fdeSIntel {
343e6541fdeSIntel 	uint32_t lcore_id;
344e6541fdeSIntel 	int ret;
345e6541fdeSIntel 
346e6541fdeSIntel 	/* EAL init */
347e6541fdeSIntel 	ret = rte_eal_init(argc, argv);
348e6541fdeSIntel 	if (ret < 0)
349e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n");
350e6541fdeSIntel 	argc -= ret;
351e6541fdeSIntel 	argv += ret;
352e6541fdeSIntel 	if (rte_lcore_count() != 1) {
353e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "This application does not accept more than one core. "
354e6541fdeSIntel 		"Please adjust the \"-c COREMASK\" parameter accordingly.\n");
355e6541fdeSIntel 	}
356e6541fdeSIntel 
357e6541fdeSIntel 	/* Application non-EAL arguments parse */
358e6541fdeSIntel 	ret = parse_args(argc, argv);
359e6541fdeSIntel 	if (ret < 0)
360e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Invalid input arguments\n");
361e6541fdeSIntel 
362e6541fdeSIntel 	/* Buffer pool init */
363e6541fdeSIntel 	pool = rte_mempool_create("pool", NB_MBUF, MBUF_SIZE, MEMPOOL_CACHE_SIZE,
364e6541fdeSIntel 		sizeof(struct rte_pktmbuf_pool_private), rte_pktmbuf_pool_init, NULL,
365e6541fdeSIntel 		rte_pktmbuf_init, NULL, rte_socket_id(), 0);
366e6541fdeSIntel 	if (pool == NULL)
367e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Buffer pool creation error\n");
368e6541fdeSIntel 
369e6541fdeSIntel 	/* NIC init */
370e6541fdeSIntel 	ret = rte_eth_dev_configure(port_rx, 1, 1, &port_conf);
371e6541fdeSIntel 	if (ret < 0)
372e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d configuration error (%d)\n", port_rx, ret);
373e6541fdeSIntel 
37481f7ecd9SPablo de Lara 	ret = rte_eth_rx_queue_setup(port_rx, NIC_RX_QUEUE, NIC_RX_QUEUE_DESC,
37581f7ecd9SPablo de Lara 				rte_eth_dev_socket_id(port_rx),
37681f7ecd9SPablo de Lara 				NULL, pool);
377e6541fdeSIntel 	if (ret < 0)
378e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d RX queue setup error (%d)\n", port_rx, ret);
379e6541fdeSIntel 
38081f7ecd9SPablo de Lara 	ret = rte_eth_tx_queue_setup(port_rx, NIC_TX_QUEUE, NIC_TX_QUEUE_DESC,
38181f7ecd9SPablo de Lara 				rte_eth_dev_socket_id(port_rx),
38281f7ecd9SPablo de Lara 				NULL);
383e6541fdeSIntel 	if (ret < 0)
384e6541fdeSIntel 	rte_exit(EXIT_FAILURE, "Port %d TX queue setup error (%d)\n", port_rx, ret);
385e6541fdeSIntel 
386e6541fdeSIntel 	ret = rte_eth_dev_configure(port_tx, 1, 1, &port_conf);
387e6541fdeSIntel 	if (ret < 0)
388e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d configuration error (%d)\n", port_tx, ret);
389e6541fdeSIntel 
39081f7ecd9SPablo de Lara 	ret = rte_eth_rx_queue_setup(port_tx, NIC_RX_QUEUE, NIC_RX_QUEUE_DESC,
39181f7ecd9SPablo de Lara 				rte_eth_dev_socket_id(port_tx),
39281f7ecd9SPablo de Lara 				NULL, pool);
393e6541fdeSIntel 	if (ret < 0)
394e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d RX queue setup error (%d)\n", port_tx, ret);
395e6541fdeSIntel 
39681f7ecd9SPablo de Lara 	ret = rte_eth_tx_queue_setup(port_tx, NIC_TX_QUEUE, NIC_TX_QUEUE_DESC,
39781f7ecd9SPablo de Lara 				rte_eth_dev_socket_id(port_tx),
39881f7ecd9SPablo de Lara 				NULL);
399e6541fdeSIntel 	if (ret < 0)
400e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d TX queue setup error (%d)\n", port_tx, ret);
401e6541fdeSIntel 
402e6541fdeSIntel 	ret = rte_eth_dev_start(port_rx);
403e6541fdeSIntel 	if (ret < 0)
404e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d start error (%d)\n", port_rx, ret);
405e6541fdeSIntel 
406e6541fdeSIntel 	ret = rte_eth_dev_start(port_tx);
407e6541fdeSIntel 	if (ret < 0)
408e6541fdeSIntel 		rte_exit(EXIT_FAILURE, "Port %d start error (%d)\n", port_tx, ret);
409e6541fdeSIntel 
410e6541fdeSIntel 	rte_eth_promiscuous_enable(port_rx);
411e6541fdeSIntel 
412e6541fdeSIntel 	rte_eth_promiscuous_enable(port_tx);
413e6541fdeSIntel 
414e6541fdeSIntel 	/* App configuration */
415e6541fdeSIntel 	app_configure_flow_table();
416e6541fdeSIntel 
417e6541fdeSIntel 	/* Launch per-lcore init on every lcore */
418e6541fdeSIntel 	rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
419e6541fdeSIntel 	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
420e6541fdeSIntel 		if (rte_eal_wait_lcore(lcore_id) < 0)
421e6541fdeSIntel 			return -1;
422e6541fdeSIntel 	}
423e6541fdeSIntel 
424e6541fdeSIntel 	return 0;
425e6541fdeSIntel }
426