xref: /dpdk/examples/multi_process/client_server_mp/shared/common.h (revision af75078fece3615088e561357c1e97603e43a5fe)
1*af75078fSIntel /*-
2*af75078fSIntel  *   BSD LICENSE
3*af75078fSIntel  *
4*af75078fSIntel  *   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
5*af75078fSIntel  *   All rights reserved.
6*af75078fSIntel  *
7*af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8*af75078fSIntel  *   modification, are permitted provided that the following conditions
9*af75078fSIntel  *   are met:
10*af75078fSIntel  *
11*af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12*af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13*af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14*af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15*af75078fSIntel  *       the documentation and/or other materials provided with the
16*af75078fSIntel  *       distribution.
17*af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18*af75078fSIntel  *       contributors may be used to endorse or promote products derived
19*af75078fSIntel  *       from this software without specific prior written permission.
20*af75078fSIntel  *
21*af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22*af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23*af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24*af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25*af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26*af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27*af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28*af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29*af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30*af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31*af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*af75078fSIntel  *
33*af75078fSIntel  *  version: DPDK.L.1.2.3-3
34*af75078fSIntel  */
35*af75078fSIntel 
36*af75078fSIntel #ifndef _COMMON_H_
37*af75078fSIntel #define _COMMON_H_
38*af75078fSIntel 
39*af75078fSIntel #define MAX_CLIENTS             16
40*af75078fSIntel 
41*af75078fSIntel /*
42*af75078fSIntel  * Shared port info, including statistics information for display by server.
43*af75078fSIntel  * Structure will be put in a memzone.
44*af75078fSIntel  * - All port id values share one cache line as this data will be read-only
45*af75078fSIntel  * during operation.
46*af75078fSIntel  * - All rx statistic values share cache lines, as this data is written only
47*af75078fSIntel  * by the server process. (rare reads by stats display)
48*af75078fSIntel  * - The tx statistics have values for all ports per cache line, but the stats
49*af75078fSIntel  * themselves are written by the clients, so we have a distinct set, on different
50*af75078fSIntel  * cache lines for each client to use.
51*af75078fSIntel  */
52*af75078fSIntel struct rx_stats{
53*af75078fSIntel 	uint64_t rx[RTE_MAX_ETHPORTS];
54*af75078fSIntel } __rte_cache_aligned;
55*af75078fSIntel 
56*af75078fSIntel struct tx_stats{
57*af75078fSIntel 	uint64_t tx[RTE_MAX_ETHPORTS];
58*af75078fSIntel 	uint64_t tx_drop[RTE_MAX_ETHPORTS];
59*af75078fSIntel } __rte_cache_aligned;
60*af75078fSIntel 
61*af75078fSIntel struct port_info {
62*af75078fSIntel 	uint8_t num_ports;
63*af75078fSIntel 	uint8_t id[RTE_MAX_ETHPORTS];
64*af75078fSIntel 	volatile struct rx_stats rx_stats;
65*af75078fSIntel 	volatile struct tx_stats tx_stats[MAX_CLIENTS];
66*af75078fSIntel };
67*af75078fSIntel 
68*af75078fSIntel /* define common names for structures shared between server and client */
69*af75078fSIntel #define MP_CLIENT_RXQ_NAME "MProc_Client_%u_RX"
70*af75078fSIntel #define PKTMBUF_POOL_NAME "MProc_pktmbuf_pool"
71*af75078fSIntel #define MZ_PORT_INFO "MProc_port_info"
72*af75078fSIntel 
73*af75078fSIntel /*
74*af75078fSIntel  * Given the rx queue name template above, get the queue name
75*af75078fSIntel  */
76*af75078fSIntel static inline const char *
77*af75078fSIntel get_rx_queue_name(unsigned id)
78*af75078fSIntel {
79*af75078fSIntel 	/* buffer for return value. Size calculated by %u being replaced
80*af75078fSIntel 	 * by maximum 3 digits (plus an extra byte for safety) */
81*af75078fSIntel 	static char buffer[sizeof(MP_CLIENT_RXQ_NAME) + 2];
82*af75078fSIntel 
83*af75078fSIntel 	rte_snprintf(buffer, sizeof(buffer) - 1, MP_CLIENT_RXQ_NAME, id);
84*af75078fSIntel 	return buffer;
85*af75078fSIntel }
86*af75078fSIntel 
87*af75078fSIntel #define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1
88*af75078fSIntel 
89*af75078fSIntel #endif
90