xref: /dpdk/examples/l3fwd-power/main.c (revision ec3d82db2dc13d3b96b7d97801d85dcbaaa1d1cb)
1d7937e2eSIntel /*-
2d7937e2eSIntel  *   BSD LICENSE
3d7937e2eSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5d7937e2eSIntel  *   All rights reserved.
6d7937e2eSIntel  *
7d7937e2eSIntel  *   Redistribution and use in source and binary forms, with or without
8d7937e2eSIntel  *   modification, are permitted provided that the following conditions
9d7937e2eSIntel  *   are met:
10d7937e2eSIntel  *
11d7937e2eSIntel  *     * Redistributions of source code must retain the above copyright
12d7937e2eSIntel  *       notice, this list of conditions and the following disclaimer.
13d7937e2eSIntel  *     * Redistributions in binary form must reproduce the above copyright
14d7937e2eSIntel  *       notice, this list of conditions and the following disclaimer in
15d7937e2eSIntel  *       the documentation and/or other materials provided with the
16d7937e2eSIntel  *       distribution.
17d7937e2eSIntel  *     * Neither the name of Intel Corporation nor the names of its
18d7937e2eSIntel  *       contributors may be used to endorse or promote products derived
19d7937e2eSIntel  *       from this software without specific prior written permission.
20d7937e2eSIntel  *
21d7937e2eSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22d7937e2eSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23d7937e2eSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24d7937e2eSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25d7937e2eSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26d7937e2eSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27d7937e2eSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28d7937e2eSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29d7937e2eSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30d7937e2eSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31d7937e2eSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32d7937e2eSIntel  */
33d7937e2eSIntel 
34d7937e2eSIntel #include <stdio.h>
35d7937e2eSIntel #include <stdlib.h>
36d7937e2eSIntel #include <stdint.h>
37d7937e2eSIntel #include <inttypes.h>
38d7937e2eSIntel #include <sys/types.h>
39d7937e2eSIntel #include <string.h>
40d7937e2eSIntel #include <sys/queue.h>
41d7937e2eSIntel #include <stdarg.h>
42d7937e2eSIntel #include <errno.h>
43d7937e2eSIntel #include <getopt.h>
44d7937e2eSIntel #include <unistd.h>
45d7937e2eSIntel #include <signal.h>
46d7937e2eSIntel 
47d7937e2eSIntel #include <rte_common.h>
48d7937e2eSIntel #include <rte_byteorder.h>
49d7937e2eSIntel #include <rte_log.h>
50d7937e2eSIntel #include <rte_memory.h>
51d7937e2eSIntel #include <rte_memcpy.h>
52d7937e2eSIntel #include <rte_memzone.h>
53d7937e2eSIntel #include <rte_tailq.h>
54d7937e2eSIntel #include <rte_eal.h>
55d7937e2eSIntel #include <rte_per_lcore.h>
56d7937e2eSIntel #include <rte_launch.h>
57d7937e2eSIntel #include <rte_atomic.h>
58d7937e2eSIntel #include <rte_cycles.h>
59d7937e2eSIntel #include <rte_prefetch.h>
60d7937e2eSIntel #include <rte_lcore.h>
61d7937e2eSIntel #include <rte_per_lcore.h>
62d7937e2eSIntel #include <rte_branch_prediction.h>
63d7937e2eSIntel #include <rte_interrupts.h>
64d7937e2eSIntel #include <rte_pci.h>
65d7937e2eSIntel #include <rte_random.h>
66d7937e2eSIntel #include <rte_debug.h>
67d7937e2eSIntel #include <rte_ether.h>
68d7937e2eSIntel #include <rte_ethdev.h>
69d7937e2eSIntel #include <rte_ring.h>
70d7937e2eSIntel #include <rte_mempool.h>
71d7937e2eSIntel #include <rte_mbuf.h>
72d7937e2eSIntel #include <rte_ip.h>
73d7937e2eSIntel #include <rte_tcp.h>
74d7937e2eSIntel #include <rte_udp.h>
75d7937e2eSIntel #include <rte_string_fns.h>
76d7937e2eSIntel #include <rte_timer.h>
77d7937e2eSIntel #include <rte_power.h>
78d7937e2eSIntel 
79d7937e2eSIntel #include "main.h"
80d7937e2eSIntel 
81d7937e2eSIntel #define RTE_LOGTYPE_L3FWD_POWER RTE_LOGTYPE_USER1
82d7937e2eSIntel 
83d7937e2eSIntel #define MAX_PKT_BURST 32
84d7937e2eSIntel 
85d7937e2eSIntel #define MIN_ZERO_POLL_COUNT 5
86d7937e2eSIntel 
87d7937e2eSIntel /* around 100ms at 2 Ghz */
88d7937e2eSIntel #define TIMER_RESOLUTION_CYCLES           200000000ULL
89d7937e2eSIntel /* 100 ms interval */
90d7937e2eSIntel #define TIMER_NUMBER_PER_SECOND           10
91d7937e2eSIntel /* 100000 us */
92d7937e2eSIntel #define SCALING_PERIOD                    (1000000/TIMER_NUMBER_PER_SECOND)
93d7937e2eSIntel #define SCALING_DOWN_TIME_RATIO_THRESHOLD 0.25
94d7937e2eSIntel 
95d7937e2eSIntel #define APP_LOOKUP_EXACT_MATCH          0
96d7937e2eSIntel #define APP_LOOKUP_LPM                  1
97d7937e2eSIntel #define DO_RFC_1812_CHECKS
98d7937e2eSIntel 
99d7937e2eSIntel #ifndef APP_LOOKUP_METHOD
100d7937e2eSIntel #define APP_LOOKUP_METHOD             APP_LOOKUP_LPM
101d7937e2eSIntel #endif
102d7937e2eSIntel 
103d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
104d7937e2eSIntel #include <rte_hash.h>
105d7937e2eSIntel #elif (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)
106d7937e2eSIntel #include <rte_lpm.h>
107d7937e2eSIntel #else
108d7937e2eSIntel #error "APP_LOOKUP_METHOD set to incorrect value"
109d7937e2eSIntel #endif
110d7937e2eSIntel 
111d7937e2eSIntel #ifndef IPv6_BYTES
112d7937e2eSIntel #define IPv6_BYTES_FMT "%02x%02x:%02x%02x:%02x%02x:%02x%02x:"\
113d7937e2eSIntel                        "%02x%02x:%02x%02x:%02x%02x:%02x%02x"
114d7937e2eSIntel #define IPv6_BYTES(addr) \
115d7937e2eSIntel 	addr[0],  addr[1], addr[2],  addr[3], \
116d7937e2eSIntel 	addr[4],  addr[5], addr[6],  addr[7], \
117d7937e2eSIntel 	addr[8],  addr[9], addr[10], addr[11],\
118d7937e2eSIntel 	addr[12], addr[13],addr[14], addr[15]
119d7937e2eSIntel #endif
120d7937e2eSIntel 
121d7937e2eSIntel #define MAX_JUMBO_PKT_LEN  9600
122d7937e2eSIntel 
123d7937e2eSIntel #define IPV6_ADDR_LEN 16
124d7937e2eSIntel 
125d7937e2eSIntel #define MEMPOOL_CACHE_SIZE 256
126d7937e2eSIntel 
127d7937e2eSIntel #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
128d7937e2eSIntel 
129d7937e2eSIntel /*
130d7937e2eSIntel  * This expression is used to calculate the number of mbufs needed depending on
131d7937e2eSIntel  * user input, taking into account memory for rx and tx hardware rings, cache
132d7937e2eSIntel  * per lcore and mtable per port per lcore. RTE_MAX is used to ensure that
133d7937e2eSIntel  * NB_MBUF never goes below a minimum value of 8192.
134d7937e2eSIntel  */
135d7937e2eSIntel 
136d7937e2eSIntel #define NB_MBUF RTE_MAX	( \
137d7937e2eSIntel 	(nb_ports*nb_rx_queue*RTE_TEST_RX_DESC_DEFAULT + \
138d7937e2eSIntel 	nb_ports*nb_lcores*MAX_PKT_BURST + \
139d7937e2eSIntel 	nb_ports*n_tx_queue*RTE_TEST_TX_DESC_DEFAULT + \
140d7937e2eSIntel 	nb_lcores*MEMPOOL_CACHE_SIZE), \
141d7937e2eSIntel 	(unsigned)8192)
142d7937e2eSIntel 
143d7937e2eSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
144d7937e2eSIntel 
145d7937e2eSIntel #define NB_SOCKETS 8
146d7937e2eSIntel 
147d7937e2eSIntel /* Configure how many packets ahead to prefetch, when reading packets */
148d7937e2eSIntel #define PREFETCH_OFFSET	3
149d7937e2eSIntel 
150d7937e2eSIntel /*
151d7937e2eSIntel  * Configurable number of RX/TX ring descriptors
152d7937e2eSIntel  */
153d7937e2eSIntel #define RTE_TEST_RX_DESC_DEFAULT 128
154d7937e2eSIntel #define RTE_TEST_TX_DESC_DEFAULT 512
155d7937e2eSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
156d7937e2eSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
157d7937e2eSIntel 
158d7937e2eSIntel /* ethernet addresses of ports */
159d7937e2eSIntel static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
160d7937e2eSIntel 
161d7937e2eSIntel /* mask of enabled ports */
162d7937e2eSIntel static uint32_t enabled_port_mask = 0;
163d7937e2eSIntel /* Ports set in promiscuous mode off by default. */
164d7937e2eSIntel static int promiscuous_on = 0;
165d7937e2eSIntel /* NUMA is enabled by default. */
166d7937e2eSIntel static int numa_on = 1;
167d7937e2eSIntel 
168d7937e2eSIntel enum freq_scale_hint_t
169d7937e2eSIntel {
170d7937e2eSIntel 	FREQ_LOWER    =      -1,
171d7937e2eSIntel 	FREQ_CURRENT  =       0,
172d7937e2eSIntel 	FREQ_HIGHER   =       1,
173d7937e2eSIntel 	FREQ_HIGHEST  =       2
174d7937e2eSIntel };
175d7937e2eSIntel 
176d7937e2eSIntel struct mbuf_table {
177d7937e2eSIntel 	uint16_t len;
178d7937e2eSIntel 	struct rte_mbuf *m_table[MAX_PKT_BURST];
179d7937e2eSIntel };
180d7937e2eSIntel 
181d7937e2eSIntel struct lcore_rx_queue {
182d7937e2eSIntel 	uint8_t port_id;
183d7937e2eSIntel 	uint8_t queue_id;
184d7937e2eSIntel 	enum freq_scale_hint_t freq_up_hint;
185d7937e2eSIntel 	uint32_t zero_rx_packet_count;
186d7937e2eSIntel 	uint32_t idle_hint;
187d7937e2eSIntel } __rte_cache_aligned;
188d7937e2eSIntel 
189d7937e2eSIntel #define MAX_RX_QUEUE_PER_LCORE 16
190d7937e2eSIntel #define MAX_TX_QUEUE_PER_PORT RTE_MAX_ETHPORTS
191d7937e2eSIntel #define MAX_RX_QUEUE_PER_PORT 128
192d7937e2eSIntel 
193d7937e2eSIntel #define MAX_LCORE_PARAMS 1024
194d7937e2eSIntel struct lcore_params {
195d7937e2eSIntel 	uint8_t port_id;
196d7937e2eSIntel 	uint8_t queue_id;
197d7937e2eSIntel 	uint8_t lcore_id;
198d7937e2eSIntel } __rte_cache_aligned;
199d7937e2eSIntel 
200d7937e2eSIntel static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
201d7937e2eSIntel static struct lcore_params lcore_params_array_default[] = {
202d7937e2eSIntel 	{0, 0, 2},
203d7937e2eSIntel 	{0, 1, 2},
204d7937e2eSIntel 	{0, 2, 2},
205d7937e2eSIntel 	{1, 0, 2},
206d7937e2eSIntel 	{1, 1, 2},
207d7937e2eSIntel 	{1, 2, 2},
208d7937e2eSIntel 	{2, 0, 2},
209d7937e2eSIntel 	{3, 0, 3},
210d7937e2eSIntel 	{3, 1, 3},
211d7937e2eSIntel };
212d7937e2eSIntel 
213d7937e2eSIntel static struct lcore_params * lcore_params = lcore_params_array_default;
214d7937e2eSIntel static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
215d7937e2eSIntel 				sizeof(lcore_params_array_default[0]);
216d7937e2eSIntel 
217d7937e2eSIntel static struct rte_eth_conf port_conf = {
218d7937e2eSIntel 	.rxmode = {
21913c4ebd6SBruce Richardson 		.mq_mode	= ETH_MQ_RX_RSS,
220d7937e2eSIntel 		.max_rx_pkt_len = ETHER_MAX_LEN,
221d7937e2eSIntel 		.split_hdr_size = 0,
222d7937e2eSIntel 		.header_split   = 0, /**< Header Split disabled */
223d7937e2eSIntel 		.hw_ip_checksum = 1, /**< IP checksum offload enabled */
224d7937e2eSIntel 		.hw_vlan_filter = 0, /**< VLAN filtering disabled */
225d7937e2eSIntel 		.jumbo_frame    = 0, /**< Jumbo Frame Support disabled */
226d7937e2eSIntel 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
227d7937e2eSIntel 	},
228d7937e2eSIntel 	.rx_adv_conf = {
229d7937e2eSIntel 		.rss_conf = {
230d7937e2eSIntel 			.rss_key = NULL,
2318a387fa8SHelin Zhang 			.rss_hf = ETH_RSS_IP,
232d7937e2eSIntel 		},
233d7937e2eSIntel 	},
234d7937e2eSIntel 	.txmode = {
235d7937e2eSIntel 		.mq_mode = ETH_DCB_NONE,
236d7937e2eSIntel 	},
237d7937e2eSIntel };
238d7937e2eSIntel 
239d7937e2eSIntel static struct rte_mempool * pktmbuf_pool[NB_SOCKETS];
240d7937e2eSIntel 
241d7937e2eSIntel 
242d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
243d7937e2eSIntel 
244d7937e2eSIntel #ifdef RTE_MACHINE_CPUFLAG_SSE4_2
245d7937e2eSIntel #include <rte_hash_crc.h>
246d7937e2eSIntel #define DEFAULT_HASH_FUNC       rte_hash_crc
247d7937e2eSIntel #else
248d7937e2eSIntel #include <rte_jhash.h>
249d7937e2eSIntel #define DEFAULT_HASH_FUNC       rte_jhash
250d7937e2eSIntel #endif
251d7937e2eSIntel 
252d7937e2eSIntel struct ipv4_5tuple {
253d7937e2eSIntel 	uint32_t ip_dst;
254d7937e2eSIntel 	uint32_t ip_src;
255d7937e2eSIntel 	uint16_t port_dst;
256d7937e2eSIntel 	uint16_t port_src;
257d7937e2eSIntel 	uint8_t  proto;
258d7937e2eSIntel } __attribute__((__packed__));
259d7937e2eSIntel 
260d7937e2eSIntel struct ipv6_5tuple {
261d7937e2eSIntel 	uint8_t  ip_dst[IPV6_ADDR_LEN];
262d7937e2eSIntel 	uint8_t  ip_src[IPV6_ADDR_LEN];
263d7937e2eSIntel 	uint16_t port_dst;
264d7937e2eSIntel 	uint16_t port_src;
265d7937e2eSIntel 	uint8_t  proto;
266d7937e2eSIntel } __attribute__((__packed__));
267d7937e2eSIntel 
268d7937e2eSIntel struct ipv4_l3fwd_route {
269d7937e2eSIntel 	struct ipv4_5tuple key;
270d7937e2eSIntel 	uint8_t if_out;
271d7937e2eSIntel };
272d7937e2eSIntel 
273d7937e2eSIntel struct ipv6_l3fwd_route {
274d7937e2eSIntel 	struct ipv6_5tuple key;
275d7937e2eSIntel 	uint8_t if_out;
276d7937e2eSIntel };
277d7937e2eSIntel 
278d7937e2eSIntel static struct ipv4_l3fwd_route ipv4_l3fwd_route_array[] = {
279d7937e2eSIntel 	{{IPv4(100,10,0,1), IPv4(200,10,0,1), 101, 11, IPPROTO_TCP}, 0},
280d7937e2eSIntel 	{{IPv4(100,20,0,2), IPv4(200,20,0,2), 102, 12, IPPROTO_TCP}, 1},
281d7937e2eSIntel 	{{IPv4(100,30,0,3), IPv4(200,30,0,3), 103, 13, IPPROTO_TCP}, 2},
282d7937e2eSIntel 	{{IPv4(100,40,0,4), IPv4(200,40,0,4), 104, 14, IPPROTO_TCP}, 3},
283d7937e2eSIntel };
284d7937e2eSIntel 
285d7937e2eSIntel static struct ipv6_l3fwd_route ipv6_l3fwd_route_array[] = {
286d7937e2eSIntel 	{
287d7937e2eSIntel 		{
288d7937e2eSIntel 			{0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
289d7937e2eSIntel 			 0x02, 0x1b, 0x21, 0xff, 0xfe, 0x91, 0x38, 0x05},
290d7937e2eSIntel 			{0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
291d7937e2eSIntel 			 0x02, 0x1e, 0x67, 0xff, 0xfe, 0x0d, 0xb6, 0x0a},
292d7937e2eSIntel 			 1, 10, IPPROTO_UDP
293d7937e2eSIntel 		}, 4
294d7937e2eSIntel 	},
295d7937e2eSIntel };
296d7937e2eSIntel 
297d7937e2eSIntel typedef struct rte_hash lookup_struct_t;
298d7937e2eSIntel static lookup_struct_t *ipv4_l3fwd_lookup_struct[NB_SOCKETS];
299d7937e2eSIntel static lookup_struct_t *ipv6_l3fwd_lookup_struct[NB_SOCKETS];
300d7937e2eSIntel 
301d7937e2eSIntel #define L3FWD_HASH_ENTRIES	1024
302d7937e2eSIntel 
303d7937e2eSIntel #define IPV4_L3FWD_NUM_ROUTES \
304d7937e2eSIntel 	(sizeof(ipv4_l3fwd_route_array) / sizeof(ipv4_l3fwd_route_array[0]))
305d7937e2eSIntel 
306d7937e2eSIntel #define IPV6_L3FWD_NUM_ROUTES \
307d7937e2eSIntel 	(sizeof(ipv6_l3fwd_route_array) / sizeof(ipv6_l3fwd_route_array[0]))
308d7937e2eSIntel 
309d7937e2eSIntel static uint8_t ipv4_l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;
310d7937e2eSIntel static uint8_t ipv6_l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;
311d7937e2eSIntel #endif
312d7937e2eSIntel 
313d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)
314d7937e2eSIntel struct ipv4_l3fwd_route {
315d7937e2eSIntel 	uint32_t ip;
316d7937e2eSIntel 	uint8_t  depth;
317d7937e2eSIntel 	uint8_t  if_out;
318d7937e2eSIntel };
319d7937e2eSIntel 
320d7937e2eSIntel static struct ipv4_l3fwd_route ipv4_l3fwd_route_array[] = {
321d7937e2eSIntel 	{IPv4(1,1,1,0), 24, 0},
322d7937e2eSIntel 	{IPv4(2,1,1,0), 24, 1},
323d7937e2eSIntel 	{IPv4(3,1,1,0), 24, 2},
324d7937e2eSIntel 	{IPv4(4,1,1,0), 24, 3},
325d7937e2eSIntel 	{IPv4(5,1,1,0), 24, 4},
326d7937e2eSIntel 	{IPv4(6,1,1,0), 24, 5},
327d7937e2eSIntel 	{IPv4(7,1,1,0), 24, 6},
328d7937e2eSIntel 	{IPv4(8,1,1,0), 24, 7},
329d7937e2eSIntel };
330d7937e2eSIntel 
331d7937e2eSIntel #define IPV4_L3FWD_NUM_ROUTES \
332d7937e2eSIntel 	(sizeof(ipv4_l3fwd_route_array) / sizeof(ipv4_l3fwd_route_array[0]))
333d7937e2eSIntel 
334d7937e2eSIntel #define IPV4_L3FWD_LPM_MAX_RULES     1024
335d7937e2eSIntel 
336d7937e2eSIntel typedef struct rte_lpm lookup_struct_t;
337d7937e2eSIntel static lookup_struct_t *ipv4_l3fwd_lookup_struct[NB_SOCKETS];
338d7937e2eSIntel #endif
339d7937e2eSIntel 
340d7937e2eSIntel struct lcore_conf {
341d7937e2eSIntel 	uint16_t n_rx_queue;
342d7937e2eSIntel 	struct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];
343d7937e2eSIntel 	uint16_t tx_queue_id[RTE_MAX_ETHPORTS];
344d7937e2eSIntel 	struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];
345d7937e2eSIntel 	lookup_struct_t * ipv4_lookup_struct;
346d7937e2eSIntel 	lookup_struct_t * ipv6_lookup_struct;
347d7937e2eSIntel } __rte_cache_aligned;
348d7937e2eSIntel 
349d7937e2eSIntel struct lcore_stats {
350d7937e2eSIntel 	/* total sleep time in ms since last frequency scaling down */
351d7937e2eSIntel 	uint32_t sleep_time;
352d7937e2eSIntel 	/* number of long sleep recently */
353d7937e2eSIntel 	uint32_t nb_long_sleep;
354d7937e2eSIntel 	/* freq. scaling up trend */
355d7937e2eSIntel 	uint32_t trend;
356d7937e2eSIntel 	/* total packet processed recently */
357d7937e2eSIntel 	uint64_t nb_rx_processed;
358d7937e2eSIntel 	/* total iterations looped recently */
359d7937e2eSIntel 	uint64_t nb_iteration_looped;
360d7937e2eSIntel 	uint32_t padding[9];
361d7937e2eSIntel } __rte_cache_aligned;
362d7937e2eSIntel 
363d7937e2eSIntel static struct lcore_conf lcore_conf[RTE_MAX_LCORE] __rte_cache_aligned;
364d7937e2eSIntel static struct lcore_stats stats[RTE_MAX_LCORE] __rte_cache_aligned;
365d7937e2eSIntel static struct rte_timer power_timers[RTE_MAX_LCORE];
366d7937e2eSIntel 
367d7937e2eSIntel static inline uint32_t power_idle_heuristic(uint32_t zero_rx_packet_count);
368d7937e2eSIntel static inline enum freq_scale_hint_t power_freq_scaleup_heuristic( \
369b451aa39SIntel 			unsigned lcore_id, uint8_t port_id, uint16_t queue_id);
370d7937e2eSIntel 
371d7937e2eSIntel /* exit signal handler */
372d7937e2eSIntel static void
373d7937e2eSIntel signal_exit_now(int sigtype)
374d7937e2eSIntel {
375d7937e2eSIntel 	unsigned lcore_id;
376d7937e2eSIntel 	int ret;
377d7937e2eSIntel 
378d7937e2eSIntel 	if (sigtype == SIGINT) {
379d7937e2eSIntel 		for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
380d7937e2eSIntel 			if (rte_lcore_is_enabled(lcore_id) == 0)
381d7937e2eSIntel 				continue;
382d7937e2eSIntel 
383d7937e2eSIntel 			/* init power management library */
384d7937e2eSIntel 			ret = rte_power_exit(lcore_id);
385d7937e2eSIntel 			if (ret)
386d7937e2eSIntel 				rte_exit(EXIT_FAILURE, "Power management "
387d7937e2eSIntel 					"library de-initialization failed on "
388d7937e2eSIntel 							"core%u\n", lcore_id);
389d7937e2eSIntel 		}
390d7937e2eSIntel 	}
391d7937e2eSIntel 
392d7937e2eSIntel 	rte_exit(EXIT_SUCCESS, "User forced exit\n");
393d7937e2eSIntel }
394d7937e2eSIntel 
395d7937e2eSIntel /*  Freqency scale down timer callback */
396d7937e2eSIntel static void
397d7937e2eSIntel power_timer_cb(__attribute__((unused)) struct rte_timer *tim,
398d7937e2eSIntel 			  __attribute__((unused)) void *arg)
399d7937e2eSIntel {
400d7937e2eSIntel 	uint64_t hz;
401d7937e2eSIntel 	float sleep_time_ratio;
402d7937e2eSIntel 	unsigned lcore_id = rte_lcore_id();
403d7937e2eSIntel 
404d7937e2eSIntel 	/* accumulate total execution time in us when callback is invoked */
405d7937e2eSIntel 	sleep_time_ratio = (float)(stats[lcore_id].sleep_time) /
406d7937e2eSIntel 					(float)SCALING_PERIOD;
407d7937e2eSIntel 
408d7937e2eSIntel 	/**
409d7937e2eSIntel 	 * check whether need to scale down frequency a step if it sleep a lot.
410d7937e2eSIntel 	 */
411d7937e2eSIntel 	if (sleep_time_ratio >= SCALING_DOWN_TIME_RATIO_THRESHOLD)
412d7937e2eSIntel 		rte_power_freq_down(lcore_id);
413d7937e2eSIntel 	else if ( (unsigned)(stats[lcore_id].nb_rx_processed /
414d7937e2eSIntel 		stats[lcore_id].nb_iteration_looped) < MAX_PKT_BURST)
415d7937e2eSIntel 		/**
416d7937e2eSIntel 		 * scale down a step if average packet per iteration less
417d7937e2eSIntel 		 * than expectation.
418d7937e2eSIntel 		 */
419d7937e2eSIntel 		rte_power_freq_down(lcore_id);
420d7937e2eSIntel 
421d7937e2eSIntel 	/**
422d7937e2eSIntel 	 * initialize another timer according to current frequency to ensure
423d7937e2eSIntel 	 * timer interval is relatively fixed.
424d7937e2eSIntel 	 */
425d7937e2eSIntel 	hz = rte_get_timer_hz();
426d7937e2eSIntel 	rte_timer_reset(&power_timers[lcore_id], hz/TIMER_NUMBER_PER_SECOND,
427d7937e2eSIntel 				SINGLE, lcore_id, power_timer_cb, NULL);
428d7937e2eSIntel 
429d7937e2eSIntel 	stats[lcore_id].nb_rx_processed = 0;
430d7937e2eSIntel 	stats[lcore_id].nb_iteration_looped = 0;
431d7937e2eSIntel 
432d7937e2eSIntel 	stats[lcore_id].sleep_time = 0;
433d7937e2eSIntel }
434d7937e2eSIntel 
435d7937e2eSIntel /* Send burst of packets on an output interface */
436d7937e2eSIntel static inline int
437d7937e2eSIntel send_burst(struct lcore_conf *qconf, uint16_t n, uint8_t port)
438d7937e2eSIntel {
439d7937e2eSIntel 	struct rte_mbuf **m_table;
440d7937e2eSIntel 	int ret;
441d7937e2eSIntel 	uint16_t queueid;
442d7937e2eSIntel 
443d7937e2eSIntel 	queueid = qconf->tx_queue_id[port];
444d7937e2eSIntel 	m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;
445d7937e2eSIntel 
446d7937e2eSIntel 	ret = rte_eth_tx_burst(port, queueid, m_table, n);
447d7937e2eSIntel 	if (unlikely(ret < n)) {
448d7937e2eSIntel 		do {
449d7937e2eSIntel 			rte_pktmbuf_free(m_table[ret]);
450d7937e2eSIntel 		} while (++ret < n);
451d7937e2eSIntel 	}
452d7937e2eSIntel 
453d7937e2eSIntel 	return 0;
454d7937e2eSIntel }
455d7937e2eSIntel 
456d7937e2eSIntel /* Enqueue a single packet, and send burst if queue is filled */
457d7937e2eSIntel static inline int
458d7937e2eSIntel send_single_packet(struct rte_mbuf *m, uint8_t port)
459d7937e2eSIntel {
460d7937e2eSIntel 	uint32_t lcore_id;
461d7937e2eSIntel 	uint16_t len;
462d7937e2eSIntel 	struct lcore_conf *qconf;
463d7937e2eSIntel 
464d7937e2eSIntel 	lcore_id = rte_lcore_id();
465d7937e2eSIntel 
466d7937e2eSIntel 	qconf = &lcore_conf[lcore_id];
467d7937e2eSIntel 	len = qconf->tx_mbufs[port].len;
468d7937e2eSIntel 	qconf->tx_mbufs[port].m_table[len] = m;
469d7937e2eSIntel 	len++;
470d7937e2eSIntel 
471d7937e2eSIntel 	/* enough pkts to be sent */
472d7937e2eSIntel 	if (unlikely(len == MAX_PKT_BURST)) {
473d7937e2eSIntel 		send_burst(qconf, MAX_PKT_BURST, port);
474d7937e2eSIntel 		len = 0;
475d7937e2eSIntel 	}
476d7937e2eSIntel 
477d7937e2eSIntel 	qconf->tx_mbufs[port].len = len;
478d7937e2eSIntel 	return 0;
479d7937e2eSIntel }
480d7937e2eSIntel 
481d7937e2eSIntel #ifdef DO_RFC_1812_CHECKS
482d7937e2eSIntel static inline int
483d7937e2eSIntel is_valid_ipv4_pkt(struct ipv4_hdr *pkt, uint32_t link_len)
484d7937e2eSIntel {
485d7937e2eSIntel 	/* From http://www.rfc-editor.org/rfc/rfc1812.txt section 5.2.2 */
486d7937e2eSIntel 	/*
487d7937e2eSIntel 	 * 1. The packet length reported by the Link Layer must be large
488d7937e2eSIntel 	 * enough to hold the minimum length legal IP datagram (20 bytes).
489d7937e2eSIntel 	 */
490d7937e2eSIntel 	if (link_len < sizeof(struct ipv4_hdr))
491d7937e2eSIntel 		return -1;
492d7937e2eSIntel 
493d7937e2eSIntel 	/* 2. The IP checksum must be correct. */
494d7937e2eSIntel 	/* this is checked in H/W */
495d7937e2eSIntel 
496d7937e2eSIntel 	/*
497d7937e2eSIntel 	 * 3. The IP version number must be 4. If the version number is not 4
498d7937e2eSIntel 	 * then the packet may be another version of IP, such as IPng or
499d7937e2eSIntel 	 * ST-II.
500d7937e2eSIntel 	 */
501d7937e2eSIntel 	if (((pkt->version_ihl) >> 4) != 4)
502d7937e2eSIntel 		return -3;
503d7937e2eSIntel 	/*
504d7937e2eSIntel 	 * 4. The IP header length field must be large enough to hold the
505d7937e2eSIntel 	 * minimum length legal IP datagram (20 bytes = 5 words).
506d7937e2eSIntel 	 */
507d7937e2eSIntel 	if ((pkt->version_ihl & 0xf) < 5)
508d7937e2eSIntel 		return -4;
509d7937e2eSIntel 
510d7937e2eSIntel 	/*
511d7937e2eSIntel 	 * 5. The IP total length field must be large enough to hold the IP
512d7937e2eSIntel 	 * datagram header, whose length is specified in the IP header length
513d7937e2eSIntel 	 * field.
514d7937e2eSIntel 	 */
515d7937e2eSIntel 	if (rte_cpu_to_be_16(pkt->total_length) < sizeof(struct ipv4_hdr))
516d7937e2eSIntel 		return -5;
517d7937e2eSIntel 
518d7937e2eSIntel 	return 0;
519d7937e2eSIntel }
520d7937e2eSIntel #endif
521d7937e2eSIntel 
522d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
523d7937e2eSIntel static void
524d7937e2eSIntel print_ipv4_key(struct ipv4_5tuple key)
525d7937e2eSIntel {
526d7937e2eSIntel 	printf("IP dst = %08x, IP src = %08x, port dst = %d, port src = %d, "
527d7937e2eSIntel 		"proto = %d\n", (unsigned)key.ip_dst, (unsigned)key.ip_src,
528d7937e2eSIntel 				key.port_dst, key.port_src, key.proto);
529d7937e2eSIntel }
530d7937e2eSIntel static void
531d7937e2eSIntel print_ipv6_key(struct ipv6_5tuple key)
532d7937e2eSIntel {
533d7937e2eSIntel 	printf( "IP dst = " IPv6_BYTES_FMT ", IP src = " IPv6_BYTES_FMT ", "
534d7937e2eSIntel 	        "port dst = %d, port src = %d, proto = %d\n",
535d7937e2eSIntel 	        IPv6_BYTES(key.ip_dst), IPv6_BYTES(key.ip_src),
536d7937e2eSIntel 	        key.port_dst, key.port_src, key.proto);
537d7937e2eSIntel }
538d7937e2eSIntel 
539d7937e2eSIntel static inline uint8_t
540d7937e2eSIntel get_ipv4_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid,
541d7937e2eSIntel 		lookup_struct_t * ipv4_l3fwd_lookup_struct)
542d7937e2eSIntel {
543d7937e2eSIntel 	struct ipv4_5tuple key;
544d7937e2eSIntel 	struct tcp_hdr *tcp;
545d7937e2eSIntel 	struct udp_hdr *udp;
546d7937e2eSIntel 	int ret = 0;
547d7937e2eSIntel 
548d7937e2eSIntel 	key.ip_dst = rte_be_to_cpu_32(ipv4_hdr->dst_addr);
549d7937e2eSIntel 	key.ip_src = rte_be_to_cpu_32(ipv4_hdr->src_addr);
550d7937e2eSIntel 	key.proto = ipv4_hdr->next_proto_id;
551d7937e2eSIntel 
552d7937e2eSIntel 	switch (ipv4_hdr->next_proto_id) {
553d7937e2eSIntel 	case IPPROTO_TCP:
554d7937e2eSIntel 		tcp = (struct tcp_hdr *)((unsigned char *)ipv4_hdr +
555d7937e2eSIntel 					sizeof(struct ipv4_hdr));
556d7937e2eSIntel 		key.port_dst = rte_be_to_cpu_16(tcp->dst_port);
557d7937e2eSIntel 		key.port_src = rte_be_to_cpu_16(tcp->src_port);
558d7937e2eSIntel 		break;
559d7937e2eSIntel 
560d7937e2eSIntel 	case IPPROTO_UDP:
561d7937e2eSIntel 		udp = (struct udp_hdr *)((unsigned char *)ipv4_hdr +
562d7937e2eSIntel 					sizeof(struct ipv4_hdr));
563d7937e2eSIntel 		key.port_dst = rte_be_to_cpu_16(udp->dst_port);
564d7937e2eSIntel 		key.port_src = rte_be_to_cpu_16(udp->src_port);
565d7937e2eSIntel 		break;
566d7937e2eSIntel 
567d7937e2eSIntel 	default:
568d7937e2eSIntel 		key.port_dst = 0;
569d7937e2eSIntel 		key.port_src = 0;
570d7937e2eSIntel 		break;
571d7937e2eSIntel 	}
572d7937e2eSIntel 
573d7937e2eSIntel 	/* Find destination port */
574d7937e2eSIntel 	ret = rte_hash_lookup(ipv4_l3fwd_lookup_struct, (const void *)&key);
575d7937e2eSIntel 	return (uint8_t)((ret < 0)? portid : ipv4_l3fwd_out_if[ret]);
576d7937e2eSIntel }
577d7937e2eSIntel 
578d7937e2eSIntel static inline uint8_t
579d7937e2eSIntel get_ipv6_dst_port(struct ipv6_hdr *ipv6_hdr,  uint8_t portid,
580d7937e2eSIntel 			lookup_struct_t *ipv6_l3fwd_lookup_struct)
581d7937e2eSIntel {
582d7937e2eSIntel 	struct ipv6_5tuple key;
583d7937e2eSIntel 	struct tcp_hdr *tcp;
584d7937e2eSIntel 	struct udp_hdr *udp;
585d7937e2eSIntel 	int ret = 0;
586d7937e2eSIntel 
587d7937e2eSIntel 	memcpy(key.ip_dst, ipv6_hdr->dst_addr, IPV6_ADDR_LEN);
588d7937e2eSIntel 	memcpy(key.ip_src, ipv6_hdr->src_addr, IPV6_ADDR_LEN);
589d7937e2eSIntel 
590d7937e2eSIntel 	key.proto = ipv6_hdr->proto;
591d7937e2eSIntel 
592d7937e2eSIntel 	switch (ipv6_hdr->proto) {
593d7937e2eSIntel 	case IPPROTO_TCP:
594d7937e2eSIntel 		tcp = (struct tcp_hdr *)((unsigned char *) ipv6_hdr +
595d7937e2eSIntel 					sizeof(struct ipv6_hdr));
596d7937e2eSIntel 		key.port_dst = rte_be_to_cpu_16(tcp->dst_port);
597d7937e2eSIntel 		key.port_src = rte_be_to_cpu_16(tcp->src_port);
598d7937e2eSIntel 		break;
599d7937e2eSIntel 
600d7937e2eSIntel 	case IPPROTO_UDP:
601d7937e2eSIntel 		udp = (struct udp_hdr *)((unsigned char *) ipv6_hdr +
602d7937e2eSIntel 					sizeof(struct ipv6_hdr));
603d7937e2eSIntel 		key.port_dst = rte_be_to_cpu_16(udp->dst_port);
604d7937e2eSIntel 		key.port_src = rte_be_to_cpu_16(udp->src_port);
605d7937e2eSIntel 		break;
606d7937e2eSIntel 
607d7937e2eSIntel 	default:
608d7937e2eSIntel 		key.port_dst = 0;
609d7937e2eSIntel 		key.port_src = 0;
610d7937e2eSIntel 		break;
611d7937e2eSIntel 	}
612d7937e2eSIntel 
613d7937e2eSIntel 	/* Find destination port */
614d7937e2eSIntel 	ret = rte_hash_lookup(ipv6_l3fwd_lookup_struct, (const void *)&key);
615d7937e2eSIntel 	return (uint8_t)((ret < 0)? portid : ipv6_l3fwd_out_if[ret]);
616d7937e2eSIntel }
617d7937e2eSIntel #endif
618d7937e2eSIntel 
619d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)
620d7937e2eSIntel static inline uint8_t
621d7937e2eSIntel get_ipv4_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid,
622d7937e2eSIntel 		lookup_struct_t *ipv4_l3fwd_lookup_struct)
623d7937e2eSIntel {
624d7937e2eSIntel 	uint8_t next_hop;
625d7937e2eSIntel 
626d7937e2eSIntel 	return (uint8_t) ((rte_lpm_lookup(ipv4_l3fwd_lookup_struct,
627d7937e2eSIntel 			rte_be_to_cpu_32(ipv4_hdr->dst_addr), &next_hop) == 0)?
628d7937e2eSIntel 			next_hop : portid);
629d7937e2eSIntel }
630d7937e2eSIntel #endif
631d7937e2eSIntel 
632d7937e2eSIntel static inline void
633d7937e2eSIntel l3fwd_simple_forward(struct rte_mbuf *m, uint8_t portid,
634d7937e2eSIntel 				struct lcore_conf *qconf)
635d7937e2eSIntel {
636d7937e2eSIntel 	struct ether_hdr *eth_hdr;
637d7937e2eSIntel 	struct ipv4_hdr *ipv4_hdr;
638d7937e2eSIntel 	void *d_addr_bytes;
639d7937e2eSIntel 	uint8_t dst_port;
640d7937e2eSIntel 
641d7937e2eSIntel 	eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
642d7937e2eSIntel 
643d7937e2eSIntel 	if (m->ol_flags & PKT_RX_IPV4_HDR) {
644d7937e2eSIntel 		/* Handle IPv4 headers.*/
645d7937e2eSIntel 		ipv4_hdr =
646d7937e2eSIntel 			(struct ipv4_hdr *)(rte_pktmbuf_mtod(m, unsigned char*)
647d7937e2eSIntel 						+ sizeof(struct ether_hdr));
648d7937e2eSIntel 
649d7937e2eSIntel #ifdef DO_RFC_1812_CHECKS
650d7937e2eSIntel 		/* Check to make sure the packet is valid (RFC1812) */
651ea672a8bSOlivier Matz 		if (is_valid_ipv4_pkt(ipv4_hdr, m->pkt_len) < 0) {
652d7937e2eSIntel 			rte_pktmbuf_free(m);
653d7937e2eSIntel 			return;
654d7937e2eSIntel 		}
655d7937e2eSIntel #endif
656d7937e2eSIntel 
657d7937e2eSIntel 		dst_port = get_ipv4_dst_port(ipv4_hdr, portid,
658d7937e2eSIntel 					qconf->ipv4_lookup_struct);
659d7937e2eSIntel 		if (dst_port >= RTE_MAX_ETHPORTS ||
660d7937e2eSIntel 				(enabled_port_mask & 1 << dst_port) == 0)
661d7937e2eSIntel 			dst_port = portid;
662d7937e2eSIntel 
663d7937e2eSIntel 		/* 02:00:00:00:00:xx */
664d7937e2eSIntel 		d_addr_bytes = &eth_hdr->d_addr.addr_bytes[0];
665d7937e2eSIntel 		*((uint64_t *)d_addr_bytes) =
666d7937e2eSIntel 			0x000000000002 + ((uint64_t)dst_port << 40);
667d7937e2eSIntel 
668d7937e2eSIntel #ifdef DO_RFC_1812_CHECKS
669d7937e2eSIntel 		/* Update time to live and header checksum */
670d7937e2eSIntel 		--(ipv4_hdr->time_to_live);
671d7937e2eSIntel 		++(ipv4_hdr->hdr_checksum);
672d7937e2eSIntel #endif
673d7937e2eSIntel 
674d7937e2eSIntel 		/* src addr */
675d7937e2eSIntel 		ether_addr_copy(&ports_eth_addr[dst_port], &eth_hdr->s_addr);
676d7937e2eSIntel 
677d7937e2eSIntel 		send_single_packet(m, dst_port);
678d7937e2eSIntel 	}
679d7937e2eSIntel 	else {
680d7937e2eSIntel 		/* Handle IPv6 headers.*/
681d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
682d7937e2eSIntel 		struct ipv6_hdr *ipv6_hdr;
683d7937e2eSIntel 
684d7937e2eSIntel 		ipv6_hdr =
685d7937e2eSIntel 			(struct ipv6_hdr *)(rte_pktmbuf_mtod(m, unsigned char*)
686d7937e2eSIntel 						+ sizeof(struct ether_hdr));
687d7937e2eSIntel 
688d7937e2eSIntel 		dst_port = get_ipv6_dst_port(ipv6_hdr, portid,
689d7937e2eSIntel 					qconf->ipv6_lookup_struct);
690d7937e2eSIntel 
691d7937e2eSIntel 		if (dst_port >= RTE_MAX_ETHPORTS ||
692d7937e2eSIntel 				(enabled_port_mask & 1 << dst_port) == 0)
693d7937e2eSIntel 			dst_port = portid;
694d7937e2eSIntel 
695d7937e2eSIntel 		/* 02:00:00:00:00:xx */
696d7937e2eSIntel 		d_addr_bytes = &eth_hdr->d_addr.addr_bytes[0];
697d7937e2eSIntel 		*((uint64_t *)d_addr_bytes) =
698d7937e2eSIntel 			0x000000000002 + ((uint64_t)dst_port << 40);
699d7937e2eSIntel 
700d7937e2eSIntel 		/* src addr */
701d7937e2eSIntel 		ether_addr_copy(&ports_eth_addr[dst_port], &eth_hdr->s_addr);
702d7937e2eSIntel 
703d7937e2eSIntel 		send_single_packet(m, dst_port);
704d7937e2eSIntel #else
705d7937e2eSIntel 		/* We don't currently handle IPv6 packets in LPM mode. */
706d7937e2eSIntel 		rte_pktmbuf_free(m);
707d7937e2eSIntel #endif
708d7937e2eSIntel 	}
709d7937e2eSIntel 
710d7937e2eSIntel }
711d7937e2eSIntel 
712d7937e2eSIntel #define SLEEP_GEAR1_THRESHOLD            100
713d7937e2eSIntel #define SLEEP_GEAR2_THRESHOLD            1000
714d7937e2eSIntel 
715d7937e2eSIntel static inline uint32_t
716d7937e2eSIntel power_idle_heuristic(uint32_t zero_rx_packet_count)
717d7937e2eSIntel {
718d7937e2eSIntel 	/* If zero count is less than 100, use it as the sleep time in us */
719d7937e2eSIntel 	if (zero_rx_packet_count < SLEEP_GEAR1_THRESHOLD)
720d7937e2eSIntel 		return zero_rx_packet_count;
721d7937e2eSIntel 	/* If zero count is less than 1000, sleep time should be 100 us */
722d7937e2eSIntel 	else if ((zero_rx_packet_count >= SLEEP_GEAR1_THRESHOLD) &&
723d7937e2eSIntel 			(zero_rx_packet_count < SLEEP_GEAR2_THRESHOLD))
724d7937e2eSIntel 		return SLEEP_GEAR1_THRESHOLD;
725d7937e2eSIntel 	/* If zero count is greater than 1000, sleep time should be 1000 us */
726d7937e2eSIntel 	else if (zero_rx_packet_count >= SLEEP_GEAR2_THRESHOLD)
727d7937e2eSIntel 		return SLEEP_GEAR2_THRESHOLD;
728d7937e2eSIntel 
729d7937e2eSIntel 	return 0;
730d7937e2eSIntel }
731d7937e2eSIntel 
732d7937e2eSIntel static inline enum freq_scale_hint_t
733b451aa39SIntel power_freq_scaleup_heuristic(unsigned lcore_id,
734b451aa39SIntel 			     uint8_t port_id,
735b451aa39SIntel 			     uint16_t queue_id)
736d7937e2eSIntel {
737d7937e2eSIntel /**
738d7937e2eSIntel  * HW Rx queue size is 128 by default, Rx burst read at maximum 32 entries
739d7937e2eSIntel  * per iteration
740d7937e2eSIntel  */
741d7937e2eSIntel #define FREQ_GEAR1_RX_PACKET_THRESHOLD             MAX_PKT_BURST
742b451aa39SIntel #define FREQ_GEAR2_RX_PACKET_THRESHOLD             (MAX_PKT_BURST*2)
743b451aa39SIntel #define FREQ_GEAR3_RX_PACKET_THRESHOLD             (MAX_PKT_BURST*3)
744d7937e2eSIntel #define FREQ_UP_TREND1_ACC   1
745d7937e2eSIntel #define FREQ_UP_TREND2_ACC   100
746d7937e2eSIntel #define FREQ_UP_THRESHOLD    10000
747d7937e2eSIntel 
748b451aa39SIntel 	if (likely(rte_eth_rx_descriptor_done(port_id, queue_id,
749b451aa39SIntel 			FREQ_GEAR3_RX_PACKET_THRESHOLD) > 0)) {
750d7937e2eSIntel 		stats[lcore_id].trend = 0;
751d7937e2eSIntel 		return FREQ_HIGHEST;
752b451aa39SIntel 	} else if (likely(rte_eth_rx_descriptor_done(port_id, queue_id,
753b451aa39SIntel 			FREQ_GEAR2_RX_PACKET_THRESHOLD) > 0))
754d7937e2eSIntel 		stats[lcore_id].trend += FREQ_UP_TREND2_ACC;
755b451aa39SIntel 	else if (likely(rte_eth_rx_descriptor_done(port_id, queue_id,
756b451aa39SIntel 			FREQ_GEAR1_RX_PACKET_THRESHOLD) > 0))
757d7937e2eSIntel 		stats[lcore_id].trend += FREQ_UP_TREND1_ACC;
758d7937e2eSIntel 
759b451aa39SIntel 	if (likely(stats[lcore_id].trend > FREQ_UP_THRESHOLD)) {
760d7937e2eSIntel 		stats[lcore_id].trend = 0;
761d7937e2eSIntel 		return FREQ_HIGHER;
762d7937e2eSIntel 	}
763d7937e2eSIntel 
764d7937e2eSIntel 	return FREQ_CURRENT;
765d7937e2eSIntel }
766d7937e2eSIntel 
767d7937e2eSIntel /* main processing loop */
768d7937e2eSIntel static int
769d7937e2eSIntel main_loop(__attribute__((unused)) void *dummy)
770d7937e2eSIntel {
771d7937e2eSIntel 	struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
772d7937e2eSIntel 	unsigned lcore_id;
773d7937e2eSIntel 	uint64_t prev_tsc, diff_tsc, cur_tsc;
774d7937e2eSIntel 	uint64_t prev_tsc_power = 0, cur_tsc_power, diff_tsc_power;
775d7937e2eSIntel 	int i, j, nb_rx;
776d7937e2eSIntel 	uint8_t portid, queueid;
777d7937e2eSIntel 	struct lcore_conf *qconf;
778d7937e2eSIntel 	struct lcore_rx_queue *rx_queue;
779d7937e2eSIntel 	enum freq_scale_hint_t lcore_scaleup_hint;
780d7937e2eSIntel 
781d7937e2eSIntel 	uint32_t lcore_rx_idle_count = 0;
782d7937e2eSIntel 	uint32_t lcore_idle_hint = 0;
783d7937e2eSIntel 
784d7937e2eSIntel 	const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
785d7937e2eSIntel 
786d7937e2eSIntel 	prev_tsc = 0;
787d7937e2eSIntel 
788d7937e2eSIntel 	lcore_id = rte_lcore_id();
789d7937e2eSIntel 	qconf = &lcore_conf[lcore_id];
790d7937e2eSIntel 
791d7937e2eSIntel 	if (qconf->n_rx_queue == 0) {
792d7937e2eSIntel 		RTE_LOG(INFO, L3FWD_POWER, "lcore %u has nothing to do\n", lcore_id);
793d7937e2eSIntel 		return 0;
794d7937e2eSIntel 	}
795d7937e2eSIntel 
796d7937e2eSIntel 	RTE_LOG(INFO, L3FWD_POWER, "entering main loop on lcore %u\n", lcore_id);
797d7937e2eSIntel 
798d7937e2eSIntel 	for (i = 0; i < qconf->n_rx_queue; i++) {
799d7937e2eSIntel 
800d7937e2eSIntel 		portid = qconf->rx_queue_list[i].port_id;
801d7937e2eSIntel 		queueid = qconf->rx_queue_list[i].queue_id;
802d7937e2eSIntel 		RTE_LOG(INFO, L3FWD_POWER, " -- lcoreid=%u portid=%hhu "
803d7937e2eSIntel 			"rxqueueid=%hhu\n", lcore_id, portid, queueid);
804d7937e2eSIntel 	}
805d7937e2eSIntel 
806d7937e2eSIntel 	while (1) {
807d7937e2eSIntel 		stats[lcore_id].nb_iteration_looped++;
808d7937e2eSIntel 
809d7937e2eSIntel 		cur_tsc = rte_rdtsc();
810d7937e2eSIntel 		cur_tsc_power = cur_tsc;
811d7937e2eSIntel 
812d7937e2eSIntel 		/*
813d7937e2eSIntel 		 * TX burst queue drain
814d7937e2eSIntel 		 */
815d7937e2eSIntel 		diff_tsc = cur_tsc - prev_tsc;
816d7937e2eSIntel 		if (unlikely(diff_tsc > drain_tsc)) {
817d7937e2eSIntel 
818d7937e2eSIntel 			/*
819d7937e2eSIntel 			 * This could be optimized (use queueid instead of
820d7937e2eSIntel 			 * portid), but it is not called so often
821d7937e2eSIntel 			 */
822d7937e2eSIntel 			for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
823d7937e2eSIntel 				if (qconf->tx_mbufs[portid].len == 0)
824d7937e2eSIntel 					continue;
825d7937e2eSIntel 				send_burst(&lcore_conf[lcore_id],
826d7937e2eSIntel 					qconf->tx_mbufs[portid].len,
827d7937e2eSIntel 					portid);
828d7937e2eSIntel 				qconf->tx_mbufs[portid].len = 0;
829d7937e2eSIntel 			}
830d7937e2eSIntel 
831d7937e2eSIntel 			prev_tsc = cur_tsc;
832d7937e2eSIntel 		}
833d7937e2eSIntel 
834d7937e2eSIntel 		diff_tsc_power = cur_tsc_power - prev_tsc_power;
835d7937e2eSIntel 		if (diff_tsc_power > TIMER_RESOLUTION_CYCLES) {
836d7937e2eSIntel 			rte_timer_manage();
837d7937e2eSIntel 			prev_tsc_power = cur_tsc_power;
838d7937e2eSIntel 		}
839d7937e2eSIntel 
840d7937e2eSIntel 		/*
841d7937e2eSIntel 		 * Read packet from RX queues
842d7937e2eSIntel 		 */
843d7937e2eSIntel 		lcore_scaleup_hint = FREQ_CURRENT;
844d7937e2eSIntel 		lcore_rx_idle_count = 0;
845d7937e2eSIntel 		for (i = 0; i < qconf->n_rx_queue; ++i) {
846d7937e2eSIntel 			rx_queue = &(qconf->rx_queue_list[i]);
847d7937e2eSIntel 			rx_queue->idle_hint = 0;
848d7937e2eSIntel 			portid = rx_queue->port_id;
849d7937e2eSIntel 			queueid = rx_queue->queue_id;
850d7937e2eSIntel 
851d7937e2eSIntel 			nb_rx = rte_eth_rx_burst(portid, queueid, pkts_burst,
852d7937e2eSIntel 								MAX_PKT_BURST);
853d7937e2eSIntel 			stats[lcore_id].nb_rx_processed += nb_rx;
854d7937e2eSIntel 			if (unlikely(nb_rx == 0)) {
855d7937e2eSIntel 				/**
856d7937e2eSIntel 				 * no packet received from rx queue, try to
857d7937e2eSIntel 				 * sleep for a while forcing CPU enter deeper
858d7937e2eSIntel 				 * C states.
859d7937e2eSIntel 				 */
860d7937e2eSIntel 				rx_queue->zero_rx_packet_count++;
861d7937e2eSIntel 
862d7937e2eSIntel 				if (rx_queue->zero_rx_packet_count <=
863d7937e2eSIntel 							MIN_ZERO_POLL_COUNT)
864d7937e2eSIntel 					continue;
865d7937e2eSIntel 
866d7937e2eSIntel 				rx_queue->idle_hint = power_idle_heuristic(\
867d7937e2eSIntel 					rx_queue->zero_rx_packet_count);
868d7937e2eSIntel 				lcore_rx_idle_count++;
869d7937e2eSIntel 			} else {
870d7937e2eSIntel 				rx_queue->zero_rx_packet_count = 0;
871d7937e2eSIntel 
872d7937e2eSIntel 				/**
873d7937e2eSIntel 				 * do not scale up frequency immediately as
874d7937e2eSIntel 				 * user to kernel space communication is costly
875d7937e2eSIntel 				 * which might impact packet I/O for received
876d7937e2eSIntel 				 * packets.
877d7937e2eSIntel 				 */
878d7937e2eSIntel 				rx_queue->freq_up_hint =
879d7937e2eSIntel 					power_freq_scaleup_heuristic(lcore_id,
880b451aa39SIntel 							portid, queueid);
881d7937e2eSIntel  			}
882d7937e2eSIntel 
883d7937e2eSIntel 			/* Prefetch first packets */
884d7937e2eSIntel 			for (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {
885d7937e2eSIntel 				rte_prefetch0(rte_pktmbuf_mtod(
886d7937e2eSIntel 						pkts_burst[j], void *));
887d7937e2eSIntel 			}
888d7937e2eSIntel 
889d7937e2eSIntel 			/* Prefetch and forward already prefetched packets */
890d7937e2eSIntel 			for (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {
891d7937e2eSIntel 				rte_prefetch0(rte_pktmbuf_mtod(pkts_burst[
892d7937e2eSIntel 						j + PREFETCH_OFFSET], void *));
893d7937e2eSIntel 				l3fwd_simple_forward(pkts_burst[j], portid,
894d7937e2eSIntel 								qconf);
895d7937e2eSIntel 			}
896d7937e2eSIntel 
897d7937e2eSIntel 			/* Forward remaining prefetched packets */
898d7937e2eSIntel 			for (; j < nb_rx; j++) {
899d7937e2eSIntel 				l3fwd_simple_forward(pkts_burst[j], portid,
900d7937e2eSIntel 								qconf);
901d7937e2eSIntel 			}
902d7937e2eSIntel 		}
903d7937e2eSIntel 
904d7937e2eSIntel 		if (likely(lcore_rx_idle_count != qconf->n_rx_queue)) {
905d7937e2eSIntel 			for (i = 1, lcore_scaleup_hint =
906d7937e2eSIntel 				qconf->rx_queue_list[0].freq_up_hint;
907d7937e2eSIntel 					i < qconf->n_rx_queue; ++i) {
908d7937e2eSIntel 				rx_queue = &(qconf->rx_queue_list[i]);
909d7937e2eSIntel 				if (rx_queue->freq_up_hint >
910d7937e2eSIntel 						lcore_scaleup_hint)
911d7937e2eSIntel 					lcore_scaleup_hint =
912d7937e2eSIntel 						rx_queue->freq_up_hint;
913d7937e2eSIntel 			}
914d7937e2eSIntel 
915d7937e2eSIntel 			if (lcore_scaleup_hint == FREQ_HIGHEST)
916d7937e2eSIntel 				rte_power_freq_max(lcore_id);
917d7937e2eSIntel 			else if (lcore_scaleup_hint == FREQ_HIGHER)
918d7937e2eSIntel 				rte_power_freq_up(lcore_id);
919d7937e2eSIntel 		} else {
920d7937e2eSIntel 			/**
921d7937e2eSIntel 			 * All Rx queues empty in recent consecutive polls,
922d7937e2eSIntel 			 * sleep in a conservative manner, meaning sleep as
923d7937e2eSIntel  			 * less as possible.
924d7937e2eSIntel  			 */
925d7937e2eSIntel 			for (i = 1, lcore_idle_hint =
926d7937e2eSIntel 				qconf->rx_queue_list[0].idle_hint;
927d7937e2eSIntel 					i < qconf->n_rx_queue; ++i) {
928d7937e2eSIntel 				rx_queue = &(qconf->rx_queue_list[i]);
929d7937e2eSIntel 				if (rx_queue->idle_hint < lcore_idle_hint)
930d7937e2eSIntel 					lcore_idle_hint = rx_queue->idle_hint;
931d7937e2eSIntel 			}
932d7937e2eSIntel 
933d7937e2eSIntel 			if ( lcore_idle_hint < SLEEP_GEAR1_THRESHOLD)
934d7937e2eSIntel 				/**
935d7937e2eSIntel 				 * execute "pause" instruction to avoid context
936d7937e2eSIntel 				 * switch for short sleep.
937d7937e2eSIntel  				 */
938d7937e2eSIntel 				rte_delay_us(lcore_idle_hint);
939d7937e2eSIntel 			else
940d7937e2eSIntel 				/* long sleep force runing thread to suspend */
941d7937e2eSIntel 				usleep(lcore_idle_hint);
942d7937e2eSIntel 
943d7937e2eSIntel 			stats[lcore_id].sleep_time += lcore_idle_hint;
944d7937e2eSIntel 		}
945d7937e2eSIntel 	}
946d7937e2eSIntel }
947d7937e2eSIntel 
948d7937e2eSIntel static int
949d7937e2eSIntel check_lcore_params(void)
950d7937e2eSIntel {
951d7937e2eSIntel 	uint8_t queue, lcore;
952d7937e2eSIntel 	uint16_t i;
953d7937e2eSIntel 	int socketid;
954d7937e2eSIntel 
955d7937e2eSIntel 	for (i = 0; i < nb_lcore_params; ++i) {
956d7937e2eSIntel 		queue = lcore_params[i].queue_id;
957d7937e2eSIntel 		if (queue >= MAX_RX_QUEUE_PER_PORT) {
958d7937e2eSIntel 			printf("invalid queue number: %hhu\n", queue);
959d7937e2eSIntel 			return -1;
960d7937e2eSIntel 		}
961d7937e2eSIntel 		lcore = lcore_params[i].lcore_id;
962d7937e2eSIntel 		if (!rte_lcore_is_enabled(lcore)) {
963d7937e2eSIntel 			printf("error: lcore %hhu is not enabled in lcore "
964d7937e2eSIntel 							"mask\n", lcore);
965d7937e2eSIntel 			return -1;
966d7937e2eSIntel 		}
967d7937e2eSIntel 		if ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&
968d7937e2eSIntel 							(numa_on == 0)) {
969d7937e2eSIntel 			printf("warning: lcore %hhu is on socket %d with numa "
970d7937e2eSIntel 						"off\n", lcore, socketid);
971d7937e2eSIntel 		}
972d7937e2eSIntel 	}
973d7937e2eSIntel 	return 0;
974d7937e2eSIntel }
975d7937e2eSIntel 
976d7937e2eSIntel static int
977d7937e2eSIntel check_port_config(const unsigned nb_ports)
978d7937e2eSIntel {
979d7937e2eSIntel 	unsigned portid;
980d7937e2eSIntel 	uint16_t i;
981d7937e2eSIntel 
982d7937e2eSIntel 	for (i = 0; i < nb_lcore_params; ++i) {
983d7937e2eSIntel 		portid = lcore_params[i].port_id;
984d7937e2eSIntel 		if ((enabled_port_mask & (1 << portid)) == 0) {
985d7937e2eSIntel 			printf("port %u is not enabled in port mask\n",
986d7937e2eSIntel 								portid);
987d7937e2eSIntel 			return -1;
988d7937e2eSIntel 		}
989d7937e2eSIntel 		if (portid >= nb_ports) {
990d7937e2eSIntel 			printf("port %u is not present on the board\n",
991d7937e2eSIntel 								portid);
992d7937e2eSIntel 			return -1;
993d7937e2eSIntel 		}
994d7937e2eSIntel 	}
995d7937e2eSIntel 	return 0;
996d7937e2eSIntel }
997d7937e2eSIntel 
998d7937e2eSIntel static uint8_t
999d7937e2eSIntel get_port_n_rx_queues(const uint8_t port)
1000d7937e2eSIntel {
1001d7937e2eSIntel 	int queue = -1;
1002d7937e2eSIntel 	uint16_t i;
1003d7937e2eSIntel 
1004d7937e2eSIntel 	for (i = 0; i < nb_lcore_params; ++i) {
1005d7937e2eSIntel 		if (lcore_params[i].port_id == port &&
1006d7937e2eSIntel 				lcore_params[i].queue_id > queue)
1007d7937e2eSIntel 			queue = lcore_params[i].queue_id;
1008d7937e2eSIntel 	}
1009d7937e2eSIntel 	return (uint8_t)(++queue);
1010d7937e2eSIntel }
1011d7937e2eSIntel 
1012d7937e2eSIntel static int
1013d7937e2eSIntel init_lcore_rx_queues(void)
1014d7937e2eSIntel {
1015d7937e2eSIntel 	uint16_t i, nb_rx_queue;
1016d7937e2eSIntel 	uint8_t lcore;
1017d7937e2eSIntel 
1018d7937e2eSIntel 	for (i = 0; i < nb_lcore_params; ++i) {
1019d7937e2eSIntel 		lcore = lcore_params[i].lcore_id;
1020d7937e2eSIntel 		nb_rx_queue = lcore_conf[lcore].n_rx_queue;
1021d7937e2eSIntel 		if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {
1022d7937e2eSIntel 			printf("error: too many queues (%u) for lcore: %u\n",
1023d7937e2eSIntel 				(unsigned)nb_rx_queue + 1, (unsigned)lcore);
1024d7937e2eSIntel 			return -1;
1025d7937e2eSIntel 		} else {
1026d7937e2eSIntel 			lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =
1027d7937e2eSIntel 				lcore_params[i].port_id;
1028d7937e2eSIntel 			lcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =
1029d7937e2eSIntel 				lcore_params[i].queue_id;
1030d7937e2eSIntel 			lcore_conf[lcore].n_rx_queue++;
1031d7937e2eSIntel 		}
1032d7937e2eSIntel 	}
1033d7937e2eSIntel 	return 0;
1034d7937e2eSIntel }
1035d7937e2eSIntel 
1036d7937e2eSIntel /* display usage */
1037d7937e2eSIntel static void
1038d7937e2eSIntel print_usage(const char *prgname)
1039d7937e2eSIntel {
1040d7937e2eSIntel 	printf ("%s [EAL options] -- -p PORTMASK -P"
1041d7937e2eSIntel 		"  [--config (port,queue,lcore)[,(port,queue,lcore]]"
1042d7937e2eSIntel 		"  [--enable-jumbo [--max-pkt-len PKTLEN]]\n"
1043d7937e2eSIntel 		"  -p PORTMASK: hexadecimal bitmask of ports to configure\n"
1044d7937e2eSIntel 		"  -P : enable promiscuous mode\n"
1045d7937e2eSIntel 		"  --config (port,queue,lcore): rx queues configuration\n"
1046d7937e2eSIntel 		"  --no-numa: optional, disable numa awareness\n"
1047d7937e2eSIntel 		"  --enable-jumbo: enable jumbo frame"
1048d7937e2eSIntel 		" which max packet len is PKTLEN in decimal (64-9600)\n",
1049d7937e2eSIntel 		prgname);
1050d7937e2eSIntel }
1051d7937e2eSIntel 
1052d7937e2eSIntel static int parse_max_pkt_len(const char *pktlen)
1053d7937e2eSIntel {
1054d7937e2eSIntel 	char *end = NULL;
1055d7937e2eSIntel 	unsigned long len;
1056d7937e2eSIntel 
1057d7937e2eSIntel 	/* parse decimal string */
1058d7937e2eSIntel 	len = strtoul(pktlen, &end, 10);
1059d7937e2eSIntel 	if ((pktlen[0] == '\0') || (end == NULL) || (*end != '\0'))
1060d7937e2eSIntel 		return -1;
1061d7937e2eSIntel 
1062d7937e2eSIntel 	if (len == 0)
1063d7937e2eSIntel 		return -1;
1064d7937e2eSIntel 
1065d7937e2eSIntel 	return len;
1066d7937e2eSIntel }
1067d7937e2eSIntel 
1068d7937e2eSIntel static int
1069d7937e2eSIntel parse_portmask(const char *portmask)
1070d7937e2eSIntel {
1071d7937e2eSIntel 	char *end = NULL;
1072d7937e2eSIntel 	unsigned long pm;
1073d7937e2eSIntel 
1074d7937e2eSIntel 	/* parse hexadecimal string */
1075d7937e2eSIntel 	pm = strtoul(portmask, &end, 16);
1076d7937e2eSIntel 	if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
1077d7937e2eSIntel 		return -1;
1078d7937e2eSIntel 
1079d7937e2eSIntel 	if (pm == 0)
1080d7937e2eSIntel 		return -1;
1081d7937e2eSIntel 
1082d7937e2eSIntel 	return pm;
1083d7937e2eSIntel }
1084d7937e2eSIntel 
1085d7937e2eSIntel static int
1086d7937e2eSIntel parse_config(const char *q_arg)
1087d7937e2eSIntel {
1088d7937e2eSIntel 	char s[256];
1089d7937e2eSIntel 	const char *p, *p0 = q_arg;
1090d7937e2eSIntel 	char *end;
1091d7937e2eSIntel 	enum fieldnames {
1092d7937e2eSIntel 		FLD_PORT = 0,
1093d7937e2eSIntel 		FLD_QUEUE,
1094d7937e2eSIntel 		FLD_LCORE,
1095d7937e2eSIntel 		_NUM_FLD
1096d7937e2eSIntel 	};
1097d7937e2eSIntel 	unsigned long int_fld[_NUM_FLD];
1098d7937e2eSIntel 	char *str_fld[_NUM_FLD];
1099d7937e2eSIntel 	int i;
1100d7937e2eSIntel 	unsigned size;
1101d7937e2eSIntel 
1102d7937e2eSIntel 	nb_lcore_params = 0;
1103d7937e2eSIntel 
1104d7937e2eSIntel 	while ((p = strchr(p0,'(')) != NULL) {
1105d7937e2eSIntel 		++p;
1106d7937e2eSIntel 		if((p0 = strchr(p,')')) == NULL)
1107d7937e2eSIntel 			return -1;
1108d7937e2eSIntel 
1109d7937e2eSIntel 		size = p0 - p;
1110d7937e2eSIntel 		if(size >= sizeof(s))
1111d7937e2eSIntel 			return -1;
1112d7937e2eSIntel 
11136f41fe75SStephen Hemminger 		snprintf(s, sizeof(s), "%.*s", size, p);
1114d7937e2eSIntel 		if (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') !=
1115d7937e2eSIntel 								_NUM_FLD)
1116d7937e2eSIntel 			return -1;
1117d7937e2eSIntel 		for (i = 0; i < _NUM_FLD; i++){
1118d7937e2eSIntel 			errno = 0;
1119d7937e2eSIntel 			int_fld[i] = strtoul(str_fld[i], &end, 0);
1120d7937e2eSIntel 			if (errno != 0 || end == str_fld[i] || int_fld[i] >
1121d7937e2eSIntel 									255)
1122d7937e2eSIntel 				return -1;
1123d7937e2eSIntel 		}
1124d7937e2eSIntel 		if (nb_lcore_params >= MAX_LCORE_PARAMS) {
1125d7937e2eSIntel 			printf("exceeded max number of lcore params: %hu\n",
1126d7937e2eSIntel 				nb_lcore_params);
1127d7937e2eSIntel 			return -1;
1128d7937e2eSIntel 		}
1129d7937e2eSIntel 		lcore_params_array[nb_lcore_params].port_id =
1130d7937e2eSIntel 				(uint8_t)int_fld[FLD_PORT];
1131d7937e2eSIntel 		lcore_params_array[nb_lcore_params].queue_id =
1132d7937e2eSIntel 				(uint8_t)int_fld[FLD_QUEUE];
1133d7937e2eSIntel 		lcore_params_array[nb_lcore_params].lcore_id =
1134d7937e2eSIntel 				(uint8_t)int_fld[FLD_LCORE];
1135d7937e2eSIntel 		++nb_lcore_params;
1136d7937e2eSIntel 	}
1137d7937e2eSIntel 	lcore_params = lcore_params_array;
1138d7937e2eSIntel 
1139d7937e2eSIntel 	return 0;
1140d7937e2eSIntel }
1141d7937e2eSIntel 
1142d7937e2eSIntel /* Parse the argument given in the command line of the application */
1143d7937e2eSIntel static int
1144d7937e2eSIntel parse_args(int argc, char **argv)
1145d7937e2eSIntel {
1146d7937e2eSIntel 	int opt, ret;
1147d7937e2eSIntel 	char **argvopt;
1148d7937e2eSIntel 	int option_index;
1149d7937e2eSIntel 	char *prgname = argv[0];
1150d7937e2eSIntel 	static struct option lgopts[] = {
1151d7937e2eSIntel 		{"config", 1, 0, 0},
1152d7937e2eSIntel 		{"no-numa", 0, 0, 0},
1153d7937e2eSIntel 		{"enable-jumbo", 0, 0, 0},
1154d7937e2eSIntel 		{NULL, 0, 0, 0}
1155d7937e2eSIntel 	};
1156d7937e2eSIntel 
1157d7937e2eSIntel 	argvopt = argv;
1158d7937e2eSIntel 
1159d7937e2eSIntel 	while ((opt = getopt_long(argc, argvopt, "p:P",
1160d7937e2eSIntel 				lgopts, &option_index)) != EOF) {
1161d7937e2eSIntel 
1162d7937e2eSIntel 		switch (opt) {
1163d7937e2eSIntel 		/* portmask */
1164d7937e2eSIntel 		case 'p':
1165d7937e2eSIntel 			enabled_port_mask = parse_portmask(optarg);
1166d7937e2eSIntel 			if (enabled_port_mask == 0) {
1167d7937e2eSIntel 				printf("invalid portmask\n");
1168d7937e2eSIntel 				print_usage(prgname);
1169d7937e2eSIntel 				return -1;
1170d7937e2eSIntel 			}
1171d7937e2eSIntel 			break;
1172d7937e2eSIntel 		case 'P':
1173d7937e2eSIntel 			printf("Promiscuous mode selected\n");
1174d7937e2eSIntel 			promiscuous_on = 1;
1175d7937e2eSIntel 			break;
1176d7937e2eSIntel 
1177d7937e2eSIntel 		/* long options */
1178d7937e2eSIntel 		case 0:
1179d7937e2eSIntel 			if (!strncmp(lgopts[option_index].name, "config", 6)) {
1180d7937e2eSIntel 				ret = parse_config(optarg);
1181d7937e2eSIntel 				if (ret) {
1182d7937e2eSIntel 					printf("invalid config\n");
1183d7937e2eSIntel 					print_usage(prgname);
1184d7937e2eSIntel 					return -1;
1185d7937e2eSIntel 				}
1186d7937e2eSIntel 			}
1187d7937e2eSIntel 
1188d7937e2eSIntel 			if (!strncmp(lgopts[option_index].name,
1189d7937e2eSIntel 						"no-numa", 7)) {
1190d7937e2eSIntel 				printf("numa is disabled \n");
1191d7937e2eSIntel 				numa_on = 0;
1192d7937e2eSIntel 			}
1193d7937e2eSIntel 
1194d7937e2eSIntel 			if (!strncmp(lgopts[option_index].name,
1195d7937e2eSIntel 					"enable-jumbo", 12)) {
1196d7937e2eSIntel 				struct option lenopts =
1197d7937e2eSIntel 					{"max-pkt-len", required_argument, \
1198d7937e2eSIntel 									0, 0};
1199d7937e2eSIntel 
1200d7937e2eSIntel 				printf("jumbo frame is enabled \n");
1201d7937e2eSIntel 				port_conf.rxmode.jumbo_frame = 1;
1202d7937e2eSIntel 
1203d7937e2eSIntel 				/**
1204d7937e2eSIntel 				 * if no max-pkt-len set, use the default value
1205d7937e2eSIntel 				 * ETHER_MAX_LEN
1206d7937e2eSIntel 				 */
1207d7937e2eSIntel 				if (0 == getopt_long(argc, argvopt, "",
1208d7937e2eSIntel 						&lenopts, &option_index)) {
1209d7937e2eSIntel 					ret = parse_max_pkt_len(optarg);
1210d7937e2eSIntel 					if ((ret < 64) ||
1211d7937e2eSIntel 						(ret > MAX_JUMBO_PKT_LEN)){
1212d7937e2eSIntel 						printf("invalid packet "
1213d7937e2eSIntel 								"length\n");
1214d7937e2eSIntel 						print_usage(prgname);
1215d7937e2eSIntel 						return -1;
1216d7937e2eSIntel 					}
1217d7937e2eSIntel 					port_conf.rxmode.max_rx_pkt_len = ret;
1218d7937e2eSIntel 				}
1219d7937e2eSIntel 				printf("set jumbo frame "
1220d7937e2eSIntel 					"max packet length to %u\n",
1221d7937e2eSIntel 				(unsigned int)port_conf.rxmode.max_rx_pkt_len);
1222d7937e2eSIntel 			}
1223d7937e2eSIntel 
1224d7937e2eSIntel 			break;
1225d7937e2eSIntel 
1226d7937e2eSIntel 		default:
1227d7937e2eSIntel 			print_usage(prgname);
1228d7937e2eSIntel 			return -1;
1229d7937e2eSIntel 		}
1230d7937e2eSIntel 	}
1231d7937e2eSIntel 
1232d7937e2eSIntel 	if (optind >= 0)
1233d7937e2eSIntel 		argv[optind-1] = prgname;
1234d7937e2eSIntel 
1235d7937e2eSIntel 	ret = optind-1;
1236d7937e2eSIntel 	optind = 0; /* reset getopt lib */
1237d7937e2eSIntel 	return ret;
1238d7937e2eSIntel }
1239d7937e2eSIntel 
1240d7937e2eSIntel static void
1241d7937e2eSIntel print_ethaddr(const char *name, const struct ether_addr *eth_addr)
1242d7937e2eSIntel {
1243*ec3d82dbSCunming Liang 	char buf[ETHER_ADDR_FMT_SIZE];
1244*ec3d82dbSCunming Liang 	ether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);
1245*ec3d82dbSCunming Liang 	printf("%s%s", name, buf);
1246d7937e2eSIntel }
1247d7937e2eSIntel 
1248d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
1249d7937e2eSIntel static void
1250d7937e2eSIntel setup_hash(int socketid)
1251d7937e2eSIntel {
1252d7937e2eSIntel 	struct rte_hash_parameters ipv4_l3fwd_hash_params = {
1253d7937e2eSIntel 		.name = NULL,
1254d7937e2eSIntel 		.entries = L3FWD_HASH_ENTRIES,
1255d7937e2eSIntel 		.bucket_entries = 4,
1256d7937e2eSIntel 		.key_len = sizeof(struct ipv4_5tuple),
1257d7937e2eSIntel 		.hash_func = DEFAULT_HASH_FUNC,
1258d7937e2eSIntel 		.hash_func_init_val = 0,
1259d7937e2eSIntel 	};
1260d7937e2eSIntel 
1261d7937e2eSIntel 	struct rte_hash_parameters ipv6_l3fwd_hash_params = {
1262d7937e2eSIntel 		.name = NULL,
1263d7937e2eSIntel 		.entries = L3FWD_HASH_ENTRIES,
1264d7937e2eSIntel 		.bucket_entries = 4,
1265d7937e2eSIntel 		.key_len = sizeof(struct ipv6_5tuple),
1266d7937e2eSIntel 		.hash_func = DEFAULT_HASH_FUNC,
1267d7937e2eSIntel 		.hash_func_init_val = 0,
1268d7937e2eSIntel 	};
1269d7937e2eSIntel 
1270d7937e2eSIntel 	unsigned i;
1271d7937e2eSIntel 	int ret;
1272d7937e2eSIntel 	char s[64];
1273d7937e2eSIntel 
1274d7937e2eSIntel 	/* create ipv4 hash */
12756f41fe75SStephen Hemminger 	snprintf(s, sizeof(s), "ipv4_l3fwd_hash_%d", socketid);
1276d7937e2eSIntel 	ipv4_l3fwd_hash_params.name = s;
1277d7937e2eSIntel 	ipv4_l3fwd_hash_params.socket_id = socketid;
1278d7937e2eSIntel 	ipv4_l3fwd_lookup_struct[socketid] =
1279d7937e2eSIntel 		rte_hash_create(&ipv4_l3fwd_hash_params);
1280d7937e2eSIntel 	if (ipv4_l3fwd_lookup_struct[socketid] == NULL)
1281d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "Unable to create the l3fwd hash on "
1282d7937e2eSIntel 				"socket %d\n", socketid);
1283d7937e2eSIntel 
1284d7937e2eSIntel 	/* create ipv6 hash */
12856f41fe75SStephen Hemminger 	snprintf(s, sizeof(s), "ipv6_l3fwd_hash_%d", socketid);
1286d7937e2eSIntel 	ipv6_l3fwd_hash_params.name = s;
1287d7937e2eSIntel 	ipv6_l3fwd_hash_params.socket_id = socketid;
1288d7937e2eSIntel 	ipv6_l3fwd_lookup_struct[socketid] =
1289d7937e2eSIntel 		rte_hash_create(&ipv6_l3fwd_hash_params);
1290d7937e2eSIntel 	if (ipv6_l3fwd_lookup_struct[socketid] == NULL)
1291d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "Unable to create the l3fwd hash on "
1292d7937e2eSIntel 				"socket %d\n", socketid);
1293d7937e2eSIntel 
1294d7937e2eSIntel 
1295d7937e2eSIntel 	/* populate the ipv4 hash */
1296d7937e2eSIntel 	for (i = 0; i < IPV4_L3FWD_NUM_ROUTES; i++) {
1297d7937e2eSIntel 		ret = rte_hash_add_key (ipv4_l3fwd_lookup_struct[socketid],
1298d7937e2eSIntel 				(void *) &ipv4_l3fwd_route_array[i].key);
1299d7937e2eSIntel 		if (ret < 0) {
1300d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "Unable to add entry %u to the"
1301d7937e2eSIntel 				"l3fwd hash on socket %d\n", i, socketid);
1302d7937e2eSIntel 		}
1303d7937e2eSIntel 		ipv4_l3fwd_out_if[ret] = ipv4_l3fwd_route_array[i].if_out;
1304d7937e2eSIntel 		printf("Hash: Adding key\n");
1305d7937e2eSIntel 		print_ipv4_key(ipv4_l3fwd_route_array[i].key);
1306d7937e2eSIntel 	}
1307d7937e2eSIntel 
1308d7937e2eSIntel 	/* populate the ipv6 hash */
1309d7937e2eSIntel 	for (i = 0; i < IPV6_L3FWD_NUM_ROUTES; i++) {
1310d7937e2eSIntel 		ret = rte_hash_add_key (ipv6_l3fwd_lookup_struct[socketid],
1311d7937e2eSIntel 				(void *) &ipv6_l3fwd_route_array[i].key);
1312d7937e2eSIntel 		if (ret < 0) {
1313d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "Unable to add entry %u to the"
1314d7937e2eSIntel 				"l3fwd hash on socket %d\n", i, socketid);
1315d7937e2eSIntel 		}
1316d7937e2eSIntel 		ipv6_l3fwd_out_if[ret] = ipv6_l3fwd_route_array[i].if_out;
1317d7937e2eSIntel 		printf("Hash: Adding key\n");
1318d7937e2eSIntel 		print_ipv6_key(ipv6_l3fwd_route_array[i].key);
1319d7937e2eSIntel 	}
1320d7937e2eSIntel }
1321d7937e2eSIntel #endif
1322d7937e2eSIntel 
1323d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)
1324d7937e2eSIntel static void
1325d7937e2eSIntel setup_lpm(int socketid)
1326d7937e2eSIntel {
1327d7937e2eSIntel 	unsigned i;
1328d7937e2eSIntel 	int ret;
1329d7937e2eSIntel 	char s[64];
1330d7937e2eSIntel 
1331d7937e2eSIntel 	/* create the LPM table */
13326f41fe75SStephen Hemminger 	snprintf(s, sizeof(s), "IPV4_L3FWD_LPM_%d", socketid);
1333d7937e2eSIntel 	ipv4_l3fwd_lookup_struct[socketid] = rte_lpm_create(s, socketid,
1334d7937e2eSIntel 				IPV4_L3FWD_LPM_MAX_RULES, 0);
1335d7937e2eSIntel 	if (ipv4_l3fwd_lookup_struct[socketid] == NULL)
1336d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "Unable to create the l3fwd LPM table"
1337d7937e2eSIntel 				" on socket %d\n", socketid);
1338d7937e2eSIntel 
1339d7937e2eSIntel 	/* populate the LPM table */
1340d7937e2eSIntel 	for (i = 0; i < IPV4_L3FWD_NUM_ROUTES; i++) {
1341d7937e2eSIntel 		ret = rte_lpm_add(ipv4_l3fwd_lookup_struct[socketid],
1342d7937e2eSIntel 			ipv4_l3fwd_route_array[i].ip,
1343d7937e2eSIntel 			ipv4_l3fwd_route_array[i].depth,
1344d7937e2eSIntel 			ipv4_l3fwd_route_array[i].if_out);
1345d7937e2eSIntel 
1346d7937e2eSIntel 		if (ret < 0) {
1347d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "Unable to add entry %u to the "
1348d7937e2eSIntel 				"l3fwd LPM table on socket %d\n",
1349d7937e2eSIntel 				i, socketid);
1350d7937e2eSIntel 		}
1351d7937e2eSIntel 
1352d7937e2eSIntel 		printf("LPM: Adding route 0x%08x / %d (%d)\n",
1353d7937e2eSIntel 			(unsigned)ipv4_l3fwd_route_array[i].ip,
1354d7937e2eSIntel 			ipv4_l3fwd_route_array[i].depth,
1355d7937e2eSIntel 			ipv4_l3fwd_route_array[i].if_out);
1356d7937e2eSIntel 	}
1357d7937e2eSIntel }
1358d7937e2eSIntel #endif
1359d7937e2eSIntel 
1360d7937e2eSIntel static int
1361d7937e2eSIntel init_mem(unsigned nb_mbuf)
1362d7937e2eSIntel {
1363d7937e2eSIntel 	struct lcore_conf *qconf;
1364d7937e2eSIntel 	int socketid;
1365d7937e2eSIntel 	unsigned lcore_id;
1366d7937e2eSIntel 	char s[64];
1367d7937e2eSIntel 
1368d7937e2eSIntel 	for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
1369d7937e2eSIntel 		if (rte_lcore_is_enabled(lcore_id) == 0)
1370d7937e2eSIntel 			continue;
1371d7937e2eSIntel 
1372d7937e2eSIntel 		if (numa_on)
1373d7937e2eSIntel 			socketid = rte_lcore_to_socket_id(lcore_id);
1374d7937e2eSIntel 		else
1375d7937e2eSIntel 			socketid = 0;
1376d7937e2eSIntel 
1377d7937e2eSIntel 		if (socketid >= NB_SOCKETS) {
1378d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "Socket %d of lcore %u is "
1379d7937e2eSIntel 					"out of range %d\n", socketid,
1380d7937e2eSIntel 						lcore_id, NB_SOCKETS);
1381d7937e2eSIntel 		}
1382d7937e2eSIntel 		if (pktmbuf_pool[socketid] == NULL) {
13836f41fe75SStephen Hemminger 			snprintf(s, sizeof(s), "mbuf_pool_%d", socketid);
1384d7937e2eSIntel 			pktmbuf_pool[socketid] =
1385d7937e2eSIntel 				rte_mempool_create(s, nb_mbuf,
1386d7937e2eSIntel 					MBUF_SIZE, MEMPOOL_CACHE_SIZE,
1387d7937e2eSIntel 					sizeof(struct rte_pktmbuf_pool_private),
1388d7937e2eSIntel 					rte_pktmbuf_pool_init, NULL,
1389d7937e2eSIntel 					rte_pktmbuf_init, NULL,
1390d7937e2eSIntel 					socketid, 0);
1391d7937e2eSIntel 			if (pktmbuf_pool[socketid] == NULL)
1392d7937e2eSIntel 				rte_exit(EXIT_FAILURE,
1393d7937e2eSIntel 					"Cannot init mbuf pool on socket %d\n",
1394d7937e2eSIntel 								socketid);
1395d7937e2eSIntel 			else
1396d7937e2eSIntel 				printf("Allocated mbuf pool on socket %d\n",
1397d7937e2eSIntel 								socketid);
1398d7937e2eSIntel 
1399d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)
1400d7937e2eSIntel 			setup_lpm(socketid);
1401d7937e2eSIntel #else
1402d7937e2eSIntel 			setup_hash(socketid);
1403d7937e2eSIntel #endif
1404d7937e2eSIntel 		}
1405d7937e2eSIntel 		qconf = &lcore_conf[lcore_id];
1406d7937e2eSIntel 		qconf->ipv4_lookup_struct = ipv4_l3fwd_lookup_struct[socketid];
1407d7937e2eSIntel #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)
1408d7937e2eSIntel 		qconf->ipv6_lookup_struct = ipv6_l3fwd_lookup_struct[socketid];
1409d7937e2eSIntel #endif
1410d7937e2eSIntel 	}
1411d7937e2eSIntel 	return 0;
1412d7937e2eSIntel }
1413d7937e2eSIntel 
1414d7937e2eSIntel /* Check the link status of all ports in up to 9s, and print them finally */
1415d7937e2eSIntel static void
1416d7937e2eSIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask)
1417d7937e2eSIntel {
1418d7937e2eSIntel #define CHECK_INTERVAL 100 /* 100ms */
1419d7937e2eSIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
1420d7937e2eSIntel 	uint8_t portid, count, all_ports_up, print_flag = 0;
1421d7937e2eSIntel 	struct rte_eth_link link;
1422d7937e2eSIntel 
1423d7937e2eSIntel 	printf("\nChecking link status");
1424d7937e2eSIntel 	fflush(stdout);
1425d7937e2eSIntel 	for (count = 0; count <= MAX_CHECK_TIME; count++) {
1426d7937e2eSIntel 		all_ports_up = 1;
1427d7937e2eSIntel 		for (portid = 0; portid < port_num; portid++) {
1428d7937e2eSIntel 			if ((port_mask & (1 << portid)) == 0)
1429d7937e2eSIntel 				continue;
1430d7937e2eSIntel 			memset(&link, 0, sizeof(link));
1431d7937e2eSIntel 			rte_eth_link_get_nowait(portid, &link);
1432d7937e2eSIntel 			/* print link status if flag set */
1433d7937e2eSIntel 			if (print_flag == 1) {
1434d7937e2eSIntel 				if (link.link_status)
1435d7937e2eSIntel 					printf("Port %d Link Up - speed %u "
1436d7937e2eSIntel 						"Mbps - %s\n", (uint8_t)portid,
1437d7937e2eSIntel 						(unsigned)link.link_speed,
1438d7937e2eSIntel 				(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
1439d7937e2eSIntel 					("full-duplex") : ("half-duplex\n"));
1440d7937e2eSIntel 				else
1441d7937e2eSIntel 					printf("Port %d Link Down\n",
1442d7937e2eSIntel 						(uint8_t)portid);
1443d7937e2eSIntel 				continue;
1444d7937e2eSIntel 			}
1445d7937e2eSIntel 			/* clear all_ports_up flag if any link down */
1446d7937e2eSIntel 			if (link.link_status == 0) {
1447d7937e2eSIntel 				all_ports_up = 0;
1448d7937e2eSIntel 				break;
1449d7937e2eSIntel 			}
1450d7937e2eSIntel 		}
1451d7937e2eSIntel 		/* after finally printing all link status, get out */
1452d7937e2eSIntel 		if (print_flag == 1)
1453d7937e2eSIntel 			break;
1454d7937e2eSIntel 
1455d7937e2eSIntel 		if (all_ports_up == 0) {
1456d7937e2eSIntel 			printf(".");
1457d7937e2eSIntel 			fflush(stdout);
1458d7937e2eSIntel 			rte_delay_ms(CHECK_INTERVAL);
1459d7937e2eSIntel 		}
1460d7937e2eSIntel 
1461d7937e2eSIntel 		/* set the print_flag if all ports up or timeout */
1462d7937e2eSIntel 		if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {
1463d7937e2eSIntel 			print_flag = 1;
1464d7937e2eSIntel 			printf("done\n");
1465d7937e2eSIntel 		}
1466d7937e2eSIntel 	}
1467d7937e2eSIntel }
1468d7937e2eSIntel 
1469d7937e2eSIntel int
1470d7937e2eSIntel MAIN(int argc, char **argv)
1471d7937e2eSIntel {
1472d7937e2eSIntel 	struct lcore_conf *qconf;
147381f7ecd9SPablo de Lara 	struct rte_eth_dev_info dev_info;
147481f7ecd9SPablo de Lara 	struct rte_eth_txconf *txconf;
1475d7937e2eSIntel 	int ret;
1476d7937e2eSIntel 	unsigned nb_ports;
1477d7937e2eSIntel 	uint16_t queueid;
1478d7937e2eSIntel 	unsigned lcore_id;
1479d7937e2eSIntel 	uint64_t hz;
1480d7937e2eSIntel 	uint32_t n_tx_queue, nb_lcores;
1481d7937e2eSIntel 	uint8_t portid, nb_rx_queue, queue, socketid;
1482d7937e2eSIntel 
1483d7937e2eSIntel 	/* catch SIGINT and restore cpufreq governor to ondemand */
1484d7937e2eSIntel 	signal(SIGINT, signal_exit_now);
1485d7937e2eSIntel 
1486d7937e2eSIntel 	/* init EAL */
1487d7937e2eSIntel 	ret = rte_eal_init(argc, argv);
1488d7937e2eSIntel 	if (ret < 0)
1489d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n");
1490d7937e2eSIntel 	argc -= ret;
1491d7937e2eSIntel 	argv += ret;
1492d7937e2eSIntel 
1493d7937e2eSIntel 	/* init RTE timer library to be used late */
1494d7937e2eSIntel 	rte_timer_subsystem_init();
1495d7937e2eSIntel 
1496d7937e2eSIntel 	/* parse application arguments (after the EAL ones) */
1497d7937e2eSIntel 	ret = parse_args(argc, argv);
1498d7937e2eSIntel 	if (ret < 0)
1499d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "Invalid L3FWD parameters\n");
1500d7937e2eSIntel 
1501d7937e2eSIntel 	if (check_lcore_params() < 0)
1502d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "check_lcore_params failed\n");
1503d7937e2eSIntel 
1504d7937e2eSIntel 	ret = init_lcore_rx_queues();
1505d7937e2eSIntel 	if (ret < 0)
1506d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "init_lcore_rx_queues failed\n");
1507d7937e2eSIntel 
1508d7937e2eSIntel 
1509d7937e2eSIntel 	nb_ports = rte_eth_dev_count();
1510d7937e2eSIntel 	if (nb_ports > RTE_MAX_ETHPORTS)
1511d7937e2eSIntel 		nb_ports = RTE_MAX_ETHPORTS;
1512d7937e2eSIntel 
1513d7937e2eSIntel 	if (check_port_config(nb_ports) < 0)
1514d7937e2eSIntel 		rte_exit(EXIT_FAILURE, "check_port_config failed\n");
1515d7937e2eSIntel 
1516d7937e2eSIntel 	nb_lcores = rte_lcore_count();
1517d7937e2eSIntel 
1518d7937e2eSIntel 	/* initialize all ports */
1519d7937e2eSIntel 	for (portid = 0; portid < nb_ports; portid++) {
1520d7937e2eSIntel 		/* skip ports that are not enabled */
1521d7937e2eSIntel 		if ((enabled_port_mask & (1 << portid)) == 0) {
1522d7937e2eSIntel 			printf("\nSkipping disabled port %d\n", portid);
1523d7937e2eSIntel 			continue;
1524d7937e2eSIntel 		}
1525d7937e2eSIntel 
1526d7937e2eSIntel 		/* init port */
1527d7937e2eSIntel 		printf("Initializing port %d ... ", portid );
1528d7937e2eSIntel 		fflush(stdout);
1529d7937e2eSIntel 
1530d7937e2eSIntel 		nb_rx_queue = get_port_n_rx_queues(portid);
1531d7937e2eSIntel 		n_tx_queue = nb_lcores;
1532d7937e2eSIntel 		if (n_tx_queue > MAX_TX_QUEUE_PER_PORT)
1533d7937e2eSIntel 			n_tx_queue = MAX_TX_QUEUE_PER_PORT;
1534d7937e2eSIntel 		printf("Creating queues: nb_rxq=%d nb_txq=%u... ",
1535d7937e2eSIntel 			nb_rx_queue, (unsigned)n_tx_queue );
1536d7937e2eSIntel 		ret = rte_eth_dev_configure(portid, nb_rx_queue,
1537d7937e2eSIntel 					(uint16_t)n_tx_queue, &port_conf);
1538d7937e2eSIntel 		if (ret < 0)
1539d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "Cannot configure device: "
1540d7937e2eSIntel 					"err=%d, port=%d\n", ret, portid);
1541d7937e2eSIntel 
1542d7937e2eSIntel 		rte_eth_macaddr_get(portid, &ports_eth_addr[portid]);
1543d7937e2eSIntel 		print_ethaddr(" Address:", &ports_eth_addr[portid]);
1544d7937e2eSIntel 		printf(", ");
1545d7937e2eSIntel 
1546d7937e2eSIntel 		/* init memory */
1547d7937e2eSIntel 		ret = init_mem(NB_MBUF);
1548d7937e2eSIntel 		if (ret < 0)
1549d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "init_mem failed\n");
1550d7937e2eSIntel 
1551d7937e2eSIntel 		/* init one TX queue per couple (lcore,port) */
1552d7937e2eSIntel 		queueid = 0;
1553d7937e2eSIntel 		for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
1554d7937e2eSIntel 			if (rte_lcore_is_enabled(lcore_id) == 0)
1555d7937e2eSIntel 				continue;
1556d7937e2eSIntel 
1557d7937e2eSIntel 			if (numa_on)
1558d7937e2eSIntel 				socketid = \
1559d7937e2eSIntel 				(uint8_t)rte_lcore_to_socket_id(lcore_id);
1560d7937e2eSIntel 			else
1561d7937e2eSIntel 				socketid = 0;
1562d7937e2eSIntel 
1563d7937e2eSIntel 			printf("txq=%u,%d,%d ", lcore_id, queueid, socketid);
1564d7937e2eSIntel 			fflush(stdout);
156581f7ecd9SPablo de Lara 
156681f7ecd9SPablo de Lara 			rte_eth_dev_info_get(portid, &dev_info);
156781f7ecd9SPablo de Lara 			txconf = &dev_info.default_txconf;
156881f7ecd9SPablo de Lara 			if (port_conf.rxmode.jumbo_frame)
156981f7ecd9SPablo de Lara 				txconf->txq_flags = 0;
1570d7937e2eSIntel 			ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,
157181f7ecd9SPablo de Lara 						     socketid, txconf);
1572d7937e2eSIntel 			if (ret < 0)
1573d7937e2eSIntel 				rte_exit(EXIT_FAILURE,
1574d7937e2eSIntel 					"rte_eth_tx_queue_setup: err=%d, "
1575d7937e2eSIntel 						"port=%d\n", ret, portid);
1576d7937e2eSIntel 
1577d7937e2eSIntel 			qconf = &lcore_conf[lcore_id];
1578d7937e2eSIntel 			qconf->tx_queue_id[portid] = queueid;
1579d7937e2eSIntel 			queueid++;
1580d7937e2eSIntel 		}
1581d7937e2eSIntel 		printf("\n");
1582d7937e2eSIntel 	}
1583d7937e2eSIntel 
1584d7937e2eSIntel 	for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
1585d7937e2eSIntel 		if (rte_lcore_is_enabled(lcore_id) == 0)
1586d7937e2eSIntel 			continue;
1587d7937e2eSIntel 
1588d7937e2eSIntel 		/* init power management library */
1589d7937e2eSIntel 		ret = rte_power_init(lcore_id);
1590d7937e2eSIntel 		if (ret)
1591d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "Power management library "
1592d7937e2eSIntel 				"initialization failed on core%u\n", lcore_id);
1593d7937e2eSIntel 
1594d7937e2eSIntel 		/* init timer structures for each enabled lcore */
1595d7937e2eSIntel 		rte_timer_init(&power_timers[lcore_id]);
1596d7937e2eSIntel 		hz = rte_get_timer_hz();
1597d7937e2eSIntel 		rte_timer_reset(&power_timers[lcore_id],
1598d7937e2eSIntel 			hz/TIMER_NUMBER_PER_SECOND, SINGLE, lcore_id,
1599d7937e2eSIntel 						power_timer_cb, NULL);
1600d7937e2eSIntel 
1601d7937e2eSIntel 		qconf = &lcore_conf[lcore_id];
1602d7937e2eSIntel 		printf("\nInitializing rx queues on lcore %u ... ", lcore_id );
1603d7937e2eSIntel 		fflush(stdout);
1604d7937e2eSIntel 		/* init RX queues */
1605d7937e2eSIntel 		for(queue = 0; queue < qconf->n_rx_queue; ++queue) {
1606d7937e2eSIntel 			portid = qconf->rx_queue_list[queue].port_id;
1607d7937e2eSIntel 			queueid = qconf->rx_queue_list[queue].queue_id;
1608d7937e2eSIntel 
1609d7937e2eSIntel 			if (numa_on)
1610d7937e2eSIntel 				socketid = \
1611d7937e2eSIntel 				(uint8_t)rte_lcore_to_socket_id(lcore_id);
1612d7937e2eSIntel 			else
1613d7937e2eSIntel 				socketid = 0;
1614d7937e2eSIntel 
1615d7937e2eSIntel 			printf("rxq=%d,%d,%d ", portid, queueid, socketid);
1616d7937e2eSIntel 			fflush(stdout);
1617d7937e2eSIntel 
1618d7937e2eSIntel 			ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,
161981f7ecd9SPablo de Lara 				socketid, NULL,
162081f7ecd9SPablo de Lara 				pktmbuf_pool[socketid]);
1621d7937e2eSIntel 			if (ret < 0)
1622d7937e2eSIntel 				rte_exit(EXIT_FAILURE,
1623d7937e2eSIntel 					"rte_eth_rx_queue_setup: err=%d, "
1624d7937e2eSIntel 						"port=%d\n", ret, portid);
1625d7937e2eSIntel 		}
1626d7937e2eSIntel 	}
1627d7937e2eSIntel 
1628d7937e2eSIntel 	printf("\n");
1629d7937e2eSIntel 
1630d7937e2eSIntel 	/* start ports */
1631d7937e2eSIntel 	for (portid = 0; portid < nb_ports; portid++) {
1632d7937e2eSIntel 		if ((enabled_port_mask & (1 << portid)) == 0) {
1633d7937e2eSIntel 			continue;
1634d7937e2eSIntel 		}
1635d7937e2eSIntel 		/* Start device */
1636d7937e2eSIntel 		ret = rte_eth_dev_start(portid);
1637d7937e2eSIntel 		if (ret < 0)
1638d7937e2eSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, "
1639d7937e2eSIntel 						"port=%d\n", ret, portid);
1640d7937e2eSIntel 
1641d7937e2eSIntel 		/*
1642d7937e2eSIntel 		 * If enabled, put device in promiscuous mode.
1643d7937e2eSIntel 		 * This allows IO forwarding mode to forward packets
1644d7937e2eSIntel 		 * to itself through 2 cross-connected  ports of the
1645d7937e2eSIntel 		 * target machine.
1646d7937e2eSIntel 		 */
1647d7937e2eSIntel 		if (promiscuous_on)
1648d7937e2eSIntel 			rte_eth_promiscuous_enable(portid);
1649d7937e2eSIntel 	}
1650d7937e2eSIntel 
1651d7937e2eSIntel 	check_all_ports_link_status((uint8_t)nb_ports, enabled_port_mask);
1652d7937e2eSIntel 
1653d7937e2eSIntel 	/* launch per-lcore init on every lcore */
1654d7937e2eSIntel 	rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
1655d7937e2eSIntel 	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
1656d7937e2eSIntel 		if (rte_eal_wait_lcore(lcore_id) < 0)
1657d7937e2eSIntel 			return -1;
1658d7937e2eSIntel 	}
1659d7937e2eSIntel 
1660d7937e2eSIntel 	return 0;
1661d7937e2eSIntel }
1662