1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 4e9d48c00SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel */ 33af75078fSIntel 34af75078fSIntel #include <stdio.h> 35af75078fSIntel #include <stdlib.h> 36af75078fSIntel #include <string.h> 37af75078fSIntel #include <stdint.h> 38af75078fSIntel #include <inttypes.h> 39af75078fSIntel #include <sys/types.h> 40af75078fSIntel #include <sys/queue.h> 41af75078fSIntel #include <netinet/in.h> 42af75078fSIntel #include <setjmp.h> 43af75078fSIntel #include <stdarg.h> 44af75078fSIntel #include <ctype.h> 45af75078fSIntel #include <errno.h> 46af75078fSIntel #include <getopt.h> 47af75078fSIntel 48af75078fSIntel #include <rte_common.h> 49af75078fSIntel #include <rte_log.h> 50af75078fSIntel #include <rte_memory.h> 51af75078fSIntel #include <rte_memcpy.h> 52af75078fSIntel #include <rte_memzone.h> 53af75078fSIntel #include <rte_tailq.h> 54af75078fSIntel #include <rte_eal.h> 55af75078fSIntel #include <rte_per_lcore.h> 56af75078fSIntel #include <rte_launch.h> 57af75078fSIntel #include <rte_atomic.h> 58af75078fSIntel #include <rte_cycles.h> 59af75078fSIntel #include <rte_prefetch.h> 60af75078fSIntel #include <rte_lcore.h> 61af75078fSIntel #include <rte_per_lcore.h> 62af75078fSIntel #include <rte_branch_prediction.h> 63af75078fSIntel #include <rte_interrupts.h> 64af75078fSIntel #include <rte_pci.h> 65af75078fSIntel #include <rte_random.h> 66af75078fSIntel #include <rte_debug.h> 67af75078fSIntel #include <rte_ether.h> 68af75078fSIntel #include <rte_ethdev.h> 69af75078fSIntel #include <rte_ring.h> 70af75078fSIntel #include <rte_mempool.h> 71af75078fSIntel #include <rte_mbuf.h> 72af75078fSIntel 73af75078fSIntel #define RTE_LOGTYPE_L2FWD RTE_LOGTYPE_USER1 74af75078fSIntel 75af75078fSIntel #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM) 76af75078fSIntel #define NB_MBUF 8192 77af75078fSIntel 78af75078fSIntel #define MAX_PKT_BURST 32 795c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */ 80af75078fSIntel 81af75078fSIntel /* 82af75078fSIntel * Configurable number of RX/TX ring descriptors 83af75078fSIntel */ 84af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128 85af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512 86af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; 87af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; 88af75078fSIntel 89af75078fSIntel /* ethernet addresses of ports */ 901c17baf4SIntel static struct ether_addr l2fwd_ports_eth_addr[RTE_MAX_ETHPORTS]; 91af75078fSIntel 92af75078fSIntel /* mask of enabled ports */ 93af75078fSIntel static uint32_t l2fwd_enabled_port_mask = 0; 94af75078fSIntel 95af75078fSIntel /* list of enabled ports */ 961c17baf4SIntel static uint32_t l2fwd_dst_ports[RTE_MAX_ETHPORTS]; 97af75078fSIntel 98af75078fSIntel static unsigned int l2fwd_rx_queue_per_lcore = 1; 99af75078fSIntel 100af75078fSIntel struct mbuf_table { 101af75078fSIntel unsigned len; 102af75078fSIntel struct rte_mbuf *m_table[MAX_PKT_BURST]; 103af75078fSIntel }; 104af75078fSIntel 105af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16 106af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16 107af75078fSIntel struct lcore_queue_conf { 10816ac9cf0SIntel unsigned n_rx_port; 10916ac9cf0SIntel unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE]; 1101c17baf4SIntel struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS]; 111af75078fSIntel 112af75078fSIntel } __rte_cache_aligned; 113af75078fSIntel struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE]; 114af75078fSIntel 115af75078fSIntel static const struct rte_eth_conf port_conf = { 116af75078fSIntel .rxmode = { 117af75078fSIntel .split_hdr_size = 0, 118af75078fSIntel .header_split = 0, /**< Header Split disabled */ 119af75078fSIntel .hw_ip_checksum = 0, /**< IP checksum offload disabled */ 120af75078fSIntel .hw_vlan_filter = 0, /**< VLAN filtering disabled */ 121af75078fSIntel .jumbo_frame = 0, /**< Jumbo Frame Support disabled */ 122af75078fSIntel .hw_strip_crc = 0, /**< CRC stripped by hardware */ 123af75078fSIntel }, 124af75078fSIntel .txmode = { 12532e7aa0bSIntel .mq_mode = ETH_MQ_TX_NONE, 126af75078fSIntel }, 127af75078fSIntel }; 128af75078fSIntel 129af75078fSIntel struct rte_mempool * l2fwd_pktmbuf_pool = NULL; 130af75078fSIntel 131af75078fSIntel /* Per-port statistics struct */ 132af75078fSIntel struct l2fwd_port_statistics { 133af75078fSIntel uint64_t tx; 134af75078fSIntel uint64_t rx; 135af75078fSIntel uint64_t dropped; 136af75078fSIntel } __rte_cache_aligned; 1371c17baf4SIntel struct l2fwd_port_statistics port_statistics[RTE_MAX_ETHPORTS]; 138af75078fSIntel 139af75078fSIntel /* A tsc-based timer responsible for triggering statistics printout */ 140af75078fSIntel #define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */ 141af75078fSIntel #define MAX_TIMER_PERIOD 86400 /* 1 day max */ 142af75078fSIntel static int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */ 143af75078fSIntel 144af75078fSIntel /* Print out statistics on packets dropped */ 145af75078fSIntel static void 146af75078fSIntel print_stats(void) 147af75078fSIntel { 148af75078fSIntel uint64_t total_packets_dropped, total_packets_tx, total_packets_rx; 149af75078fSIntel unsigned portid; 150af75078fSIntel 151af75078fSIntel total_packets_dropped = 0; 152af75078fSIntel total_packets_tx = 0; 153af75078fSIntel total_packets_rx = 0; 154af75078fSIntel 155af75078fSIntel const char clr[] = { 27, '[', '2', 'J', '\0' }; 156af75078fSIntel const char topLeft[] = { 27, '[', '1', ';', '1', 'H','\0' }; 157af75078fSIntel 158af75078fSIntel /* Clear screen and move to top left */ 159af75078fSIntel printf("%s%s", clr, topLeft); 160af75078fSIntel 161af75078fSIntel printf("\nPort statistics ===================================="); 162af75078fSIntel 1631c17baf4SIntel for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) { 164af75078fSIntel /* skip disabled ports */ 165af75078fSIntel if ((l2fwd_enabled_port_mask & (1 << portid)) == 0) 166af75078fSIntel continue; 167af75078fSIntel printf("\nStatistics for port %u ------------------------------" 168af75078fSIntel "\nPackets sent: %24"PRIu64 169af75078fSIntel "\nPackets received: %20"PRIu64 170af75078fSIntel "\nPackets dropped: %21"PRIu64, 171af75078fSIntel portid, 172af75078fSIntel port_statistics[portid].tx, 173af75078fSIntel port_statistics[portid].rx, 174af75078fSIntel port_statistics[portid].dropped); 175af75078fSIntel 176af75078fSIntel total_packets_dropped += port_statistics[portid].dropped; 177af75078fSIntel total_packets_tx += port_statistics[portid].tx; 178af75078fSIntel total_packets_rx += port_statistics[portid].rx; 179af75078fSIntel } 180af75078fSIntel printf("\nAggregate statistics ===============================" 181af75078fSIntel "\nTotal packets sent: %18"PRIu64 182af75078fSIntel "\nTotal packets received: %14"PRIu64 183af75078fSIntel "\nTotal packets dropped: %15"PRIu64, 184af75078fSIntel total_packets_tx, 185af75078fSIntel total_packets_rx, 186af75078fSIntel total_packets_dropped); 187af75078fSIntel printf("\n====================================================\n"); 188af75078fSIntel } 189af75078fSIntel 1909787d22fSIntel /* Send the burst of packets on an output interface */ 191af75078fSIntel static int 192af75078fSIntel l2fwd_send_burst(struct lcore_queue_conf *qconf, unsigned n, uint8_t port) 193af75078fSIntel { 194af75078fSIntel struct rte_mbuf **m_table; 195af75078fSIntel unsigned ret; 19616ac9cf0SIntel unsigned queueid =0; 197af75078fSIntel 198af75078fSIntel m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table; 199af75078fSIntel 200af75078fSIntel ret = rte_eth_tx_burst(port, (uint16_t) queueid, m_table, (uint16_t) n); 201af75078fSIntel port_statistics[port].tx += ret; 202af75078fSIntel if (unlikely(ret < n)) { 203af75078fSIntel port_statistics[port].dropped += (n - ret); 204af75078fSIntel do { 205af75078fSIntel rte_pktmbuf_free(m_table[ret]); 206af75078fSIntel } while (++ret < n); 207af75078fSIntel } 208af75078fSIntel 209af75078fSIntel return 0; 210af75078fSIntel } 211af75078fSIntel 2129787d22fSIntel /* Enqueue packets for TX and prepare them to be sent */ 213af75078fSIntel static int 214af75078fSIntel l2fwd_send_packet(struct rte_mbuf *m, uint8_t port) 215af75078fSIntel { 216af75078fSIntel unsigned lcore_id, len; 217af75078fSIntel struct lcore_queue_conf *qconf; 218af75078fSIntel 219af75078fSIntel lcore_id = rte_lcore_id(); 220af75078fSIntel 221af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 222af75078fSIntel len = qconf->tx_mbufs[port].len; 223af75078fSIntel qconf->tx_mbufs[port].m_table[len] = m; 224af75078fSIntel len++; 225af75078fSIntel 226af75078fSIntel /* enough pkts to be sent */ 227af75078fSIntel if (unlikely(len == MAX_PKT_BURST)) { 228af75078fSIntel l2fwd_send_burst(qconf, MAX_PKT_BURST, port); 229af75078fSIntel len = 0; 230af75078fSIntel } 231af75078fSIntel 232af75078fSIntel qconf->tx_mbufs[port].len = len; 233af75078fSIntel return 0; 234af75078fSIntel } 235af75078fSIntel 236af75078fSIntel static void 237af75078fSIntel l2fwd_simple_forward(struct rte_mbuf *m, unsigned portid) 238af75078fSIntel { 239af75078fSIntel struct ether_hdr *eth; 240af75078fSIntel void *tmp; 241af75078fSIntel unsigned dst_port; 242af75078fSIntel 243af75078fSIntel dst_port = l2fwd_dst_ports[portid]; 244af75078fSIntel eth = rte_pktmbuf_mtod(m, struct ether_hdr *); 245af75078fSIntel 24616ac9cf0SIntel /* 02:00:00:00:00:xx */ 247af75078fSIntel tmp = ð->d_addr.addr_bytes[0]; 24816ac9cf0SIntel *((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40); 249af75078fSIntel 250af75078fSIntel /* src addr */ 251af75078fSIntel ether_addr_copy(&l2fwd_ports_eth_addr[dst_port], ð->s_addr); 252af75078fSIntel 253af75078fSIntel l2fwd_send_packet(m, (uint8_t) dst_port); 254af75078fSIntel } 255af75078fSIntel 256af75078fSIntel /* main processing loop */ 257af75078fSIntel static void 258af75078fSIntel l2fwd_main_loop(void) 259af75078fSIntel { 260af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; 261af75078fSIntel struct rte_mbuf *m; 262af75078fSIntel unsigned lcore_id; 2635c95261dSIntel uint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc; 264af75078fSIntel unsigned i, j, portid, nb_rx; 265af75078fSIntel struct lcore_queue_conf *qconf; 2665c95261dSIntel const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US; 267af75078fSIntel 2685c95261dSIntel prev_tsc = 0; 269af75078fSIntel timer_tsc = 0; 270af75078fSIntel 271af75078fSIntel lcore_id = rte_lcore_id(); 272af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 273af75078fSIntel 27416ac9cf0SIntel if (qconf->n_rx_port == 0) { 275af75078fSIntel RTE_LOG(INFO, L2FWD, "lcore %u has nothing to do\n", lcore_id); 276cdfd5dbbSIntel return; 277af75078fSIntel } 278af75078fSIntel 279af75078fSIntel RTE_LOG(INFO, L2FWD, "entering main loop on lcore %u\n", lcore_id); 280af75078fSIntel 28116ac9cf0SIntel for (i = 0; i < qconf->n_rx_port; i++) { 282af75078fSIntel 28316ac9cf0SIntel portid = qconf->rx_port_list[i]; 284af75078fSIntel RTE_LOG(INFO, L2FWD, " -- lcoreid=%u portid=%u\n", lcore_id, 285af75078fSIntel portid); 286af75078fSIntel } 287af75078fSIntel 288af75078fSIntel while (1) { 289af75078fSIntel 290af75078fSIntel cur_tsc = rte_rdtsc(); 291af75078fSIntel 292af75078fSIntel /* 293af75078fSIntel * TX burst queue drain 294af75078fSIntel */ 295af75078fSIntel diff_tsc = cur_tsc - prev_tsc; 2965c95261dSIntel if (unlikely(diff_tsc > drain_tsc)) { 297af75078fSIntel 2981c17baf4SIntel for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) { 299af75078fSIntel if (qconf->tx_mbufs[portid].len == 0) 300af75078fSIntel continue; 301af75078fSIntel l2fwd_send_burst(&lcore_queue_conf[lcore_id], 302af75078fSIntel qconf->tx_mbufs[portid].len, 303af75078fSIntel (uint8_t) portid); 304af75078fSIntel qconf->tx_mbufs[portid].len = 0; 305af75078fSIntel } 306af75078fSIntel 307af75078fSIntel /* if timer is enabled */ 308af75078fSIntel if (timer_period > 0) { 309af75078fSIntel 310af75078fSIntel /* advance the timer */ 311af75078fSIntel timer_tsc += diff_tsc; 312af75078fSIntel 313af75078fSIntel /* if timer has reached its timeout */ 314af75078fSIntel if (unlikely(timer_tsc >= (uint64_t) timer_period)) { 315af75078fSIntel 316af75078fSIntel /* do this only on master core */ 317af75078fSIntel if (lcore_id == rte_get_master_lcore()) { 318af75078fSIntel print_stats(); 319af75078fSIntel /* reset the timer */ 320af75078fSIntel timer_tsc = 0; 321af75078fSIntel } 322af75078fSIntel } 323af75078fSIntel } 324af75078fSIntel 325af75078fSIntel prev_tsc = cur_tsc; 326af75078fSIntel } 327af75078fSIntel 328af75078fSIntel /* 329af75078fSIntel * Read packet from RX queues 330af75078fSIntel */ 33116ac9cf0SIntel for (i = 0; i < qconf->n_rx_port; i++) { 332af75078fSIntel 33316ac9cf0SIntel portid = qconf->rx_port_list[i]; 334af75078fSIntel nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, 335af75078fSIntel pkts_burst, MAX_PKT_BURST); 336af75078fSIntel 337af75078fSIntel port_statistics[portid].rx += nb_rx; 338af75078fSIntel 339af75078fSIntel for (j = 0; j < nb_rx; j++) { 340af75078fSIntel m = pkts_burst[j]; 341af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod(m, void *)); 342af75078fSIntel l2fwd_simple_forward(m, portid); 343af75078fSIntel } 344af75078fSIntel } 345af75078fSIntel } 346af75078fSIntel } 347af75078fSIntel 348af75078fSIntel static int 349af75078fSIntel l2fwd_launch_one_lcore(__attribute__((unused)) void *dummy) 350af75078fSIntel { 351af75078fSIntel l2fwd_main_loop(); 352af75078fSIntel return 0; 353af75078fSIntel } 354af75078fSIntel 355af75078fSIntel /* display usage */ 356af75078fSIntel static void 357af75078fSIntel l2fwd_usage(const char *prgname) 358af75078fSIntel { 359af75078fSIntel printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n" 360af75078fSIntel " -p PORTMASK: hexadecimal bitmask of ports to configure\n" 361af75078fSIntel " -q NQ: number of queue (=ports) per lcore (default is 1)\n" 362af75078fSIntel " -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\n", 363af75078fSIntel prgname); 364af75078fSIntel } 365af75078fSIntel 366af75078fSIntel static int 367af75078fSIntel l2fwd_parse_portmask(const char *portmask) 368af75078fSIntel { 369af75078fSIntel char *end = NULL; 370af75078fSIntel unsigned long pm; 371af75078fSIntel 372af75078fSIntel /* parse hexadecimal string */ 373af75078fSIntel pm = strtoul(portmask, &end, 16); 374af75078fSIntel if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0')) 375af75078fSIntel return -1; 376af75078fSIntel 377af75078fSIntel if (pm == 0) 378af75078fSIntel return -1; 379af75078fSIntel 380af75078fSIntel return pm; 381af75078fSIntel } 382af75078fSIntel 383af75078fSIntel static unsigned int 384af75078fSIntel l2fwd_parse_nqueue(const char *q_arg) 385af75078fSIntel { 386af75078fSIntel char *end = NULL; 387af75078fSIntel unsigned long n; 388af75078fSIntel 389af75078fSIntel /* parse hexadecimal string */ 390af75078fSIntel n = strtoul(q_arg, &end, 10); 391af75078fSIntel if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0')) 392af75078fSIntel return 0; 393af75078fSIntel if (n == 0) 394af75078fSIntel return 0; 395af75078fSIntel if (n >= MAX_RX_QUEUE_PER_LCORE) 396af75078fSIntel return 0; 397af75078fSIntel 398af75078fSIntel return n; 399af75078fSIntel } 400af75078fSIntel 401af75078fSIntel static int 402af75078fSIntel l2fwd_parse_timer_period(const char *q_arg) 403af75078fSIntel { 404af75078fSIntel char *end = NULL; 405af75078fSIntel int n; 406af75078fSIntel 407af75078fSIntel /* parse number string */ 408af75078fSIntel n = strtol(q_arg, &end, 10); 409af75078fSIntel if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0')) 410af75078fSIntel return -1; 411af75078fSIntel if (n >= MAX_TIMER_PERIOD) 412af75078fSIntel return -1; 413af75078fSIntel 414af75078fSIntel return n; 415af75078fSIntel } 416af75078fSIntel 417af75078fSIntel /* Parse the argument given in the command line of the application */ 418af75078fSIntel static int 419af75078fSIntel l2fwd_parse_args(int argc, char **argv) 420af75078fSIntel { 421af75078fSIntel int opt, ret; 422af75078fSIntel char **argvopt; 423af75078fSIntel int option_index; 424af75078fSIntel char *prgname = argv[0]; 425af75078fSIntel static struct option lgopts[] = { 426af75078fSIntel {NULL, 0, 0, 0} 427af75078fSIntel }; 428af75078fSIntel 429af75078fSIntel argvopt = argv; 430af75078fSIntel 431af75078fSIntel while ((opt = getopt_long(argc, argvopt, "p:q:T:", 432af75078fSIntel lgopts, &option_index)) != EOF) { 433af75078fSIntel 434af75078fSIntel switch (opt) { 435af75078fSIntel /* portmask */ 436af75078fSIntel case 'p': 437af75078fSIntel l2fwd_enabled_port_mask = l2fwd_parse_portmask(optarg); 438af75078fSIntel if (l2fwd_enabled_port_mask == 0) { 439af75078fSIntel printf("invalid portmask\n"); 440af75078fSIntel l2fwd_usage(prgname); 441af75078fSIntel return -1; 442af75078fSIntel } 443af75078fSIntel break; 444af75078fSIntel 445af75078fSIntel /* nqueue */ 446af75078fSIntel case 'q': 447af75078fSIntel l2fwd_rx_queue_per_lcore = l2fwd_parse_nqueue(optarg); 448af75078fSIntel if (l2fwd_rx_queue_per_lcore == 0) { 449af75078fSIntel printf("invalid queue number\n"); 450af75078fSIntel l2fwd_usage(prgname); 451af75078fSIntel return -1; 452af75078fSIntel } 453af75078fSIntel break; 454af75078fSIntel 455af75078fSIntel /* timer period */ 456af75078fSIntel case 'T': 457af75078fSIntel timer_period = l2fwd_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND; 458af75078fSIntel if (timer_period < 0) { 459af75078fSIntel printf("invalid timer period\n"); 460af75078fSIntel l2fwd_usage(prgname); 461af75078fSIntel return -1; 462af75078fSIntel } 463af75078fSIntel break; 464af75078fSIntel 465af75078fSIntel /* long options */ 466af75078fSIntel case 0: 467af75078fSIntel l2fwd_usage(prgname); 468af75078fSIntel return -1; 469af75078fSIntel 470af75078fSIntel default: 471af75078fSIntel l2fwd_usage(prgname); 472af75078fSIntel return -1; 473af75078fSIntel } 474af75078fSIntel } 475af75078fSIntel 476af75078fSIntel if (optind >= 0) 477af75078fSIntel argv[optind-1] = prgname; 478af75078fSIntel 479af75078fSIntel ret = optind-1; 480af75078fSIntel optind = 0; /* reset getopt lib */ 481af75078fSIntel return ret; 482af75078fSIntel } 483af75078fSIntel 484d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */ 485d3641ae8SIntel static void 486d3641ae8SIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask) 487d3641ae8SIntel { 488d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */ 489d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 490d3641ae8SIntel uint8_t portid, count, all_ports_up, print_flag = 0; 491d3641ae8SIntel struct rte_eth_link link; 492d3641ae8SIntel 493d3641ae8SIntel printf("\nChecking link status"); 494d3641ae8SIntel fflush(stdout); 495d3641ae8SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) { 496d3641ae8SIntel all_ports_up = 1; 497d3641ae8SIntel for (portid = 0; portid < port_num; portid++) { 498d3641ae8SIntel if ((port_mask & (1 << portid)) == 0) 499d3641ae8SIntel continue; 500d3641ae8SIntel memset(&link, 0, sizeof(link)); 501d3641ae8SIntel rte_eth_link_get_nowait(portid, &link); 502d3641ae8SIntel /* print link status if flag set */ 503d3641ae8SIntel if (print_flag == 1) { 504d3641ae8SIntel if (link.link_status) 505d3641ae8SIntel printf("Port %d Link Up - speed %u " 506d3641ae8SIntel "Mbps - %s\n", (uint8_t)portid, 507d3641ae8SIntel (unsigned)link.link_speed, 508d3641ae8SIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 509d3641ae8SIntel ("full-duplex") : ("half-duplex\n")); 510d3641ae8SIntel else 511d3641ae8SIntel printf("Port %d Link Down\n", 512d3641ae8SIntel (uint8_t)portid); 513d3641ae8SIntel continue; 514d3641ae8SIntel } 515d3641ae8SIntel /* clear all_ports_up flag if any link down */ 516d3641ae8SIntel if (link.link_status == 0) { 517d3641ae8SIntel all_ports_up = 0; 518d3641ae8SIntel break; 519d3641ae8SIntel } 520d3641ae8SIntel } 521d3641ae8SIntel /* after finally printing all link status, get out */ 522d3641ae8SIntel if (print_flag == 1) 523d3641ae8SIntel break; 524d3641ae8SIntel 525d3641ae8SIntel if (all_ports_up == 0) { 526d3641ae8SIntel printf("."); 527d3641ae8SIntel fflush(stdout); 528d3641ae8SIntel rte_delay_ms(CHECK_INTERVAL); 529d3641ae8SIntel } 530d3641ae8SIntel 531d3641ae8SIntel /* set the print_flag if all ports up or timeout */ 532d3641ae8SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) { 533d3641ae8SIntel print_flag = 1; 534d3641ae8SIntel printf("done\n"); 535d3641ae8SIntel } 536d3641ae8SIntel } 537d3641ae8SIntel } 538d3641ae8SIntel 539af75078fSIntel int 540*98a16481SDavid Marchand main(int argc, char **argv) 541af75078fSIntel { 542af75078fSIntel struct lcore_queue_conf *qconf; 543af75078fSIntel struct rte_eth_dev_info dev_info; 544af75078fSIntel int ret; 545a974564bSIntel uint8_t nb_ports; 546f56d0815SIntel uint8_t nb_ports_available; 547a974564bSIntel uint8_t portid, last_port; 548af75078fSIntel unsigned lcore_id, rx_lcore_id; 549af75078fSIntel unsigned nb_ports_in_mask = 0; 550af75078fSIntel 551af75078fSIntel /* init EAL */ 552af75078fSIntel ret = rte_eal_init(argc, argv); 553af75078fSIntel if (ret < 0) 554af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid EAL arguments\n"); 555af75078fSIntel argc -= ret; 556af75078fSIntel argv += ret; 557af75078fSIntel 558af75078fSIntel /* parse application arguments (after the EAL ones) */ 559af75078fSIntel ret = l2fwd_parse_args(argc, argv); 560af75078fSIntel if (ret < 0) 561af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid L2FWD arguments\n"); 562af75078fSIntel 563af75078fSIntel /* create the mbuf pool */ 564af75078fSIntel l2fwd_pktmbuf_pool = 565af75078fSIntel rte_mempool_create("mbuf_pool", NB_MBUF, 566af75078fSIntel MBUF_SIZE, 32, 567af75078fSIntel sizeof(struct rte_pktmbuf_pool_private), 568af75078fSIntel rte_pktmbuf_pool_init, NULL, 569af75078fSIntel rte_pktmbuf_init, NULL, 570e60f71ebSIntel rte_socket_id(), 0); 571af75078fSIntel if (l2fwd_pktmbuf_pool == NULL) 572af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init mbuf pool\n"); 573af75078fSIntel 574af75078fSIntel nb_ports = rte_eth_dev_count(); 575af75078fSIntel if (nb_ports == 0) 576af75078fSIntel rte_exit(EXIT_FAILURE, "No Ethernet ports - bye\n"); 577af75078fSIntel 5781c17baf4SIntel if (nb_ports > RTE_MAX_ETHPORTS) 5791c17baf4SIntel nb_ports = RTE_MAX_ETHPORTS; 580af75078fSIntel 581af75078fSIntel /* reset l2fwd_dst_ports */ 5821c17baf4SIntel for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) 583af75078fSIntel l2fwd_dst_ports[portid] = 0; 584af75078fSIntel last_port = 0; 585af75078fSIntel 586af75078fSIntel /* 587af75078fSIntel * Each logical core is assigned a dedicated TX queue on each port. 588af75078fSIntel */ 589af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 590af75078fSIntel /* skip ports that are not enabled */ 591af75078fSIntel if ((l2fwd_enabled_port_mask & (1 << portid)) == 0) 592af75078fSIntel continue; 593af75078fSIntel 594af75078fSIntel if (nb_ports_in_mask % 2) { 595af75078fSIntel l2fwd_dst_ports[portid] = last_port; 596af75078fSIntel l2fwd_dst_ports[last_port] = portid; 597af75078fSIntel } 598af75078fSIntel else 599af75078fSIntel last_port = portid; 600af75078fSIntel 601af75078fSIntel nb_ports_in_mask++; 602af75078fSIntel 603a974564bSIntel rte_eth_dev_info_get(portid, &dev_info); 604af75078fSIntel } 605f56d0815SIntel if (nb_ports_in_mask % 2) { 60616ac9cf0SIntel printf("Notice: odd number of ports in portmask.\n"); 60716ac9cf0SIntel l2fwd_dst_ports[last_port] = last_port; 608af75078fSIntel } 609af75078fSIntel 610af75078fSIntel rx_lcore_id = 0; 611af75078fSIntel qconf = NULL; 612af75078fSIntel 613af75078fSIntel /* Initialize the port/queue configuration of each logical core */ 614af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 615af75078fSIntel /* skip ports that are not enabled */ 616af75078fSIntel if ((l2fwd_enabled_port_mask & (1 << portid)) == 0) 617af75078fSIntel continue; 618af75078fSIntel 619af75078fSIntel /* get the lcore_id for this port */ 620af75078fSIntel while (rte_lcore_is_enabled(rx_lcore_id) == 0 || 62116ac9cf0SIntel lcore_queue_conf[rx_lcore_id].n_rx_port == 622af75078fSIntel l2fwd_rx_queue_per_lcore) { 623af75078fSIntel rx_lcore_id++; 624af75078fSIntel if (rx_lcore_id >= RTE_MAX_LCORE) 625af75078fSIntel rte_exit(EXIT_FAILURE, "Not enough cores\n"); 626af75078fSIntel } 62716ac9cf0SIntel 62816ac9cf0SIntel if (qconf != &lcore_queue_conf[rx_lcore_id]) 629af75078fSIntel /* Assigned a new logical core in the loop above. */ 630af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 63116ac9cf0SIntel 63216ac9cf0SIntel qconf->rx_port_list[qconf->n_rx_port] = portid; 63316ac9cf0SIntel qconf->n_rx_port++; 634a974564bSIntel printf("Lcore %u: RX port %u\n", rx_lcore_id, (unsigned) portid); 635af75078fSIntel } 636af75078fSIntel 637f56d0815SIntel nb_ports_available = nb_ports; 638f56d0815SIntel 639af75078fSIntel /* Initialise each port */ 640af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 641af75078fSIntel /* skip ports that are not enabled */ 642af75078fSIntel if ((l2fwd_enabled_port_mask & (1 << portid)) == 0) { 643a974564bSIntel printf("Skipping disabled port %u\n", (unsigned) portid); 644f56d0815SIntel nb_ports_available--; 645af75078fSIntel continue; 646af75078fSIntel } 647af75078fSIntel /* init port */ 648a974564bSIntel printf("Initializing port %u... ", (unsigned) portid); 649af75078fSIntel fflush(stdout); 650a974564bSIntel ret = rte_eth_dev_configure(portid, 1, 1, &port_conf); 651af75078fSIntel if (ret < 0) 65216ac9cf0SIntel rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%u\n", 653a974564bSIntel ret, (unsigned) portid); 654af75078fSIntel 655a974564bSIntel rte_eth_macaddr_get(portid,&l2fwd_ports_eth_addr[portid]); 656af75078fSIntel 657af75078fSIntel /* init one RX queue */ 658af75078fSIntel fflush(stdout); 659a974564bSIntel ret = rte_eth_rx_queue_setup(portid, 0, nb_rxd, 66081f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid), 66181f7ecd9SPablo de Lara NULL, 662af75078fSIntel l2fwd_pktmbuf_pool); 663af75078fSIntel if (ret < 0) 664a974564bSIntel rte_exit(EXIT_FAILURE, "rte_eth_rx_queue_setup:err=%d, port=%u\n", 665a974564bSIntel ret, (unsigned) portid); 666af75078fSIntel 667e60f71ebSIntel /* init one TX queue on each port */ 668af75078fSIntel fflush(stdout); 669a974564bSIntel ret = rte_eth_tx_queue_setup(portid, 0, nb_txd, 67081f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid), 67181f7ecd9SPablo de Lara NULL); 672af75078fSIntel if (ret < 0) 67316ac9cf0SIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup:err=%d, port=%u\n", 674a974564bSIntel ret, (unsigned) portid); 675af75078fSIntel 676af75078fSIntel /* Start device */ 677a974564bSIntel ret = rte_eth_dev_start(portid); 678af75078fSIntel if (ret < 0) 67916ac9cf0SIntel rte_exit(EXIT_FAILURE, "rte_eth_dev_start:err=%d, port=%u\n", 680a974564bSIntel ret, (unsigned) portid); 681af75078fSIntel 682d3641ae8SIntel printf("done: \n"); 683af75078fSIntel 684a974564bSIntel rte_eth_promiscuous_enable(portid); 685af75078fSIntel 686af75078fSIntel printf("Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n\n", 687a974564bSIntel (unsigned) portid, 688af75078fSIntel l2fwd_ports_eth_addr[portid].addr_bytes[0], 689af75078fSIntel l2fwd_ports_eth_addr[portid].addr_bytes[1], 690af75078fSIntel l2fwd_ports_eth_addr[portid].addr_bytes[2], 691af75078fSIntel l2fwd_ports_eth_addr[portid].addr_bytes[3], 692af75078fSIntel l2fwd_ports_eth_addr[portid].addr_bytes[4], 693af75078fSIntel l2fwd_ports_eth_addr[portid].addr_bytes[5]); 694af75078fSIntel 695af75078fSIntel /* initialize port stats */ 696af75078fSIntel memset(&port_statistics, 0, sizeof(port_statistics)); 697af75078fSIntel } 698af75078fSIntel 699f56d0815SIntel if (!nb_ports_available) { 700f56d0815SIntel rte_exit(EXIT_FAILURE, 701f56d0815SIntel "All available ports are disabled. Please set portmask.\n"); 702f56d0815SIntel } 703f56d0815SIntel 704a974564bSIntel check_all_ports_link_status(nb_ports, l2fwd_enabled_port_mask); 705d3641ae8SIntel 706af75078fSIntel /* launch per-lcore init on every lcore */ 707af75078fSIntel rte_eal_mp_remote_launch(l2fwd_launch_one_lcore, NULL, CALL_MASTER); 708af75078fSIntel RTE_LCORE_FOREACH_SLAVE(lcore_id) { 709af75078fSIntel if (rte_eal_wait_lcore(lcore_id) < 0) 710af75078fSIntel return -1; 711af75078fSIntel } 712af75078fSIntel 713af75078fSIntel return 0; 714af75078fSIntel } 715d3641ae8SIntel 716