1*9077d5a4SCristian Dumitrescu; SPDX-License-Identifier: BSD-3-Clause 2*9077d5a4SCristian Dumitrescu; Copyright(c) 2010-2018 Intel Corporation 3*9077d5a4SCristian Dumitrescu 4*9077d5a4SCristian Dumitrescu; This setup demonstrates the usage of NIC Receive Side Scaling (RSS) feature. 5*9077d5a4SCristian Dumitrescu; Each NIC splits the input traffic into 4 RX queues, with each of its RX queues 6*9077d5a4SCristian Dumitrescu; being handled by a different pipeline: 7*9077d5a4SCristian Dumitrescu; 8*9077d5a4SCristian Dumitrescu; +-----------+ +----------+ 9*9077d5a4SCristian Dumitrescu; +--------------------------->| | | | 10*9077d5a4SCristian Dumitrescu; | +------------------->| PIPELINE0 +--->| LINK 0 |---> 11*9077d5a4SCristian Dumitrescu; | | +------------->| (CORE A) | | TX | 12*9077d5a4SCristian Dumitrescu; | | | +------->| | | | 13*9077d5a4SCristian Dumitrescu; | | | | +-----------+ +----------+ 14*9077d5a4SCristian Dumitrescu; +----------+ | | | | 15*9077d5a4SCristian Dumitrescu; | |-------+ | | | 16*9077d5a4SCristian Dumitrescu;--->| LINK 0 |-----------+ | | | 17*9077d5a4SCristian Dumitrescu; | RX |---------+ | | | | 18*9077d5a4SCristian Dumitrescu; | |-------+ | | | | | 19*9077d5a4SCristian Dumitrescu; +----------+ | | | | | | +-----------+ +----------+ 20*9077d5a4SCristian Dumitrescu; | | +---|-----|-----|------->| | | | 21*9077d5a4SCristian Dumitrescu; +----------+ | | | +---|-----|------->| PIPELINE1 +--->| LINK 1 |---> 22*9077d5a4SCristian Dumitrescu; | |-------|-|-----+ | | +---|------->| (CORE B) | | TX | 23*9077d5a4SCristian Dumitrescu;--->| LINK 1 |-------|-|-------+ | | | +----->| | | | 24*9077d5a4SCristian Dumitrescu; | RX |-------|-|-------+ | | | | +-----------+ +----------+ 25*9077d5a4SCristian Dumitrescu; | |-------|-|-----+ | | | | | 26*9077d5a4SCristian Dumitrescu; +----------+ | | | | | | | | 27*9077d5a4SCristian Dumitrescu; | | | | | | | | 28*9077d5a4SCristian Dumitrescu; +----------+ | | | | | | | | 29*9077d5a4SCristian Dumitrescu; | |-------|-|-----|-|---+ | | | 30*9077d5a4SCristian Dumitrescu;--->| LINK 2 |-------|-|-----|-|-----+ | | +-----------+ +----------+ 31*9077d5a4SCristian Dumitrescu; | RX |-----+ | +-----|-|---------|-|----->| | | | 32*9077d5a4SCristian Dumitrescu; | |---+ | | | +---------|-|----->| PIPELINE2 +--->| LINK 2 |---> 33*9077d5a4SCristian Dumitrescu; +----------+ | +-|-------|-----------|-|----->| (CORE C) | | TX | 34*9077d5a4SCristian Dumitrescu; | | | | | +--->| | | | 35*9077d5a4SCristian Dumitrescu; +----------+ | | | | | | +-----------+ +----------+ 36*9077d5a4SCristian Dumitrescu; | |---|---|-------|-----------+ | | 37*9077d5a4SCristian Dumitrescu;--->| LINK 3 |---|---|-------|-------------+ | 38*9077d5a4SCristian Dumitrescu; | RX |---|---|-------|---------------+ 39*9077d5a4SCristian Dumitrescu; | |---|---|-------|-----------+ 40*9077d5a4SCristian Dumitrescu; +----------+ | | | | 41*9077d5a4SCristian Dumitrescu; | | | | +-----------+ +----------+ 42*9077d5a4SCristian Dumitrescu; | +-------|-----------|------->| | | | 43*9077d5a4SCristian Dumitrescu; | +-----------|------->| PIPELINE3 +--->| LINK 3 |---> 44*9077d5a4SCristian Dumitrescu; +-----------------------|------->| (CORE D) | | TX | 45*9077d5a4SCristian Dumitrescu; +------->| | | | 46*9077d5a4SCristian Dumitrescu; +-----------+ +----------+ 47*9077d5a4SCristian Dumitrescu; 48*9077d5a4SCristian Dumitrescu; 49*9077d5a4SCristian Dumitrescu 50*9077d5a4SCristian Dumitrescumempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 51*9077d5a4SCristian Dumitrescu 52*9077d5a4SCristian Dumitresculink LINK0 dev 0000:02:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 53*9077d5a4SCristian Dumitresculink LINK1 dev 0000:02:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 54*9077d5a4SCristian Dumitresculink LINK2 dev 0000:06:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 55*9077d5a4SCristian Dumitresculink LINK3 dev 0000:06:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 56*9077d5a4SCristian Dumitrescu 57*9077d5a4SCristian Dumitrescupipeline PIPELINE0 period 10 offset_port_id 0 cpu 0 58*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0 59*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0 60*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0 61*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0 62*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port out bsz 32 link LINK0 txq 0 63*9077d5a4SCristian Dumitrescupipeline PIPELINE0 table match stub 64*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in 0 table 0 65*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in 1 table 0 66*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in 2 table 0 67*9077d5a4SCristian Dumitrescupipeline PIPELINE0 port in 3 table 0 68*9077d5a4SCristian Dumitrescupipeline PIPELINE0 table 0 rule add match default action fwd port 0 69*9077d5a4SCristian Dumitrescu 70*9077d5a4SCristian Dumitrescupipeline PIPELINE1 period 10 offset_port_id 0 cpu 0 71*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in bsz 32 link LINK0 rxq 1 72*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in bsz 32 link LINK1 rxq 1 73*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in bsz 32 link LINK2 rxq 1 74*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in bsz 32 link LINK3 rxq 1 75*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port out bsz 32 link LINK1 txq 0 76*9077d5a4SCristian Dumitrescupipeline PIPELINE1 table match stub 77*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in 0 table 0 78*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in 1 table 0 79*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in 2 table 0 80*9077d5a4SCristian Dumitrescupipeline PIPELINE1 port in 3 table 0 81*9077d5a4SCristian Dumitrescupipeline PIPELINE1 table 0 rule add match default action fwd port 0 82*9077d5a4SCristian Dumitrescu 83*9077d5a4SCristian Dumitrescupipeline PIPELINE2 period 10 offset_port_id 0 cpu 0 84*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in bsz 32 link LINK0 rxq 2 85*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in bsz 32 link LINK1 rxq 2 86*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in bsz 32 link LINK2 rxq 2 87*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in bsz 32 link LINK3 rxq 2 88*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port out bsz 32 link LINK2 txq 0 89*9077d5a4SCristian Dumitrescupipeline PIPELINE2 table match stub 90*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in 0 table 0 91*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in 1 table 0 92*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in 2 table 0 93*9077d5a4SCristian Dumitrescupipeline PIPELINE2 port in 3 table 0 94*9077d5a4SCristian Dumitrescupipeline PIPELINE2 table 0 rule add match default action fwd port 0 95*9077d5a4SCristian Dumitrescu 96*9077d5a4SCristian Dumitrescupipeline PIPELINE3 period 10 offset_port_id 0 cpu 0 97*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in bsz 32 link LINK0 rxq 3 98*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in bsz 32 link LINK1 rxq 3 99*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in bsz 32 link LINK2 rxq 3 100*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in bsz 32 link LINK3 rxq 3 101*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port out bsz 32 link LINK3 txq 0 102*9077d5a4SCristian Dumitrescupipeline PIPELINE3 table match stub 103*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in 0 table 0 104*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in 1 table 0 105*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in 2 table 0 106*9077d5a4SCristian Dumitrescupipeline PIPELINE3 port in 3 table 0 107*9077d5a4SCristian Dumitrescupipeline PIPELINE3 table 0 rule add match default action fwd port 0 108*9077d5a4SCristian Dumitrescu 109*9077d5a4SCristian Dumitrescuthread 1 pipeline PIPELINE0 enable 110*9077d5a4SCristian Dumitrescuthread 2 pipeline PIPELINE1 enable 111*9077d5a4SCristian Dumitrescuthread 3 pipeline PIPELINE2 enable 112*9077d5a4SCristian Dumitrescuthread 4 pipeline PIPELINE3 enable 113