1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2010-2014 Intel Corporation 4 * Copyright 2017 Cavium, Inc. 5 */ 6 7 #include "pipeline_common.h" 8 9 static __rte_always_inline void 10 worker_fwd_event(struct rte_event *ev, uint8_t sched) 11 { 12 ev->event_type = RTE_EVENT_TYPE_CPU; 13 ev->op = RTE_EVENT_OP_FORWARD; 14 ev->sched_type = sched; 15 } 16 17 static __rte_always_inline void 18 worker_event_enqueue(const uint8_t dev, const uint8_t port, 19 struct rte_event *ev) 20 { 21 while (!rte_event_enqueue_burst(dev, port, ev, 1) && !fdata->done) 22 rte_pause(); 23 } 24 25 static __rte_always_inline uint16_t 26 worker_event_enqueue_burst(const uint8_t dev, const uint8_t port, 27 struct rte_event *ev, const uint16_t nb_rx) 28 { 29 uint16_t enq; 30 31 enq = rte_event_enqueue_burst(dev, port, ev, nb_rx); 32 while (enq < nb_rx && !fdata->done) 33 enq += rte_event_enqueue_burst(dev, port, 34 ev + enq, nb_rx - enq); 35 36 return enq; 37 } 38 39 static __rte_always_inline void 40 worker_tx_pkt(const uint8_t dev, const uint8_t port, struct rte_event *ev) 41 { 42 exchange_mac(ev->mbuf); 43 rte_event_eth_tx_adapter_txq_set(ev->mbuf, 0); 44 while (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1, 0) && 45 !fdata->done) 46 rte_pause(); 47 } 48 49 /* Single stage pipeline workers */ 50 51 static int 52 worker_do_tx_single(void *arg) 53 { 54 struct worker_data *data = (struct worker_data *)arg; 55 const uint8_t dev = data->dev_id; 56 const uint8_t port = data->port_id; 57 size_t fwd = 0, received = 0, tx = 0; 58 struct rte_event ev; 59 60 while (!fdata->done) { 61 62 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) { 63 rte_pause(); 64 continue; 65 } 66 67 received++; 68 69 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 70 worker_tx_pkt(dev, port, &ev); 71 tx++; 72 } else { 73 work(); 74 ev.queue_id++; 75 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 76 worker_event_enqueue(dev, port, &ev); 77 fwd++; 78 } 79 } 80 81 if (ev.u64) { 82 ev.op = RTE_EVENT_OP_RELEASE; 83 rte_event_enqueue_burst(dev, port, &ev, 1); 84 } 85 86 if (!cdata.quiet) 87 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 88 rte_lcore_id(), received, fwd, tx); 89 return 0; 90 } 91 92 static int 93 worker_do_tx_single_atq(void *arg) 94 { 95 struct worker_data *data = (struct worker_data *)arg; 96 const uint8_t dev = data->dev_id; 97 const uint8_t port = data->port_id; 98 size_t fwd = 0, received = 0, tx = 0; 99 struct rte_event ev; 100 101 while (!fdata->done) { 102 103 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) { 104 rte_pause(); 105 continue; 106 } 107 108 received++; 109 110 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 111 worker_tx_pkt(dev, port, &ev); 112 tx++; 113 } else { 114 work(); 115 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 116 worker_event_enqueue(dev, port, &ev); 117 fwd++; 118 } 119 } 120 121 if (ev.u64) { 122 ev.op = RTE_EVENT_OP_RELEASE; 123 rte_event_enqueue_burst(dev, port, &ev, 1); 124 } 125 126 if (!cdata.quiet) 127 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 128 rte_lcore_id(), received, fwd, tx); 129 return 0; 130 } 131 132 static int 133 worker_do_tx_single_burst(void *arg) 134 { 135 struct rte_event ev[BATCH_SIZE + 1]; 136 137 struct worker_data *data = (struct worker_data *)arg; 138 const uint8_t dev = data->dev_id; 139 const uint8_t port = data->port_id; 140 size_t fwd = 0, received = 0, tx = 0; 141 uint16_t nb_tx = 0, nb_rx = 0, i; 142 143 while (!fdata->done) { 144 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0); 145 146 if (!nb_rx) { 147 rte_pause(); 148 continue; 149 } 150 received += nb_rx; 151 152 for (i = 0; i < nb_rx; i++) { 153 rte_prefetch0(ev[i + 1].mbuf); 154 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) { 155 156 worker_tx_pkt(dev, port, &ev[i]); 157 ev[i].op = RTE_EVENT_OP_RELEASE; 158 tx++; 159 160 } else { 161 ev[i].queue_id++; 162 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC); 163 } 164 work(); 165 } 166 167 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx); 168 fwd += nb_tx; 169 } 170 171 worker_cleanup(dev, port, ev, nb_tx, nb_rx); 172 173 if (!cdata.quiet) 174 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 175 rte_lcore_id(), received, fwd, tx); 176 return 0; 177 } 178 179 static int 180 worker_do_tx_single_burst_atq(void *arg) 181 { 182 struct rte_event ev[BATCH_SIZE + 1]; 183 184 struct worker_data *data = (struct worker_data *)arg; 185 const uint8_t dev = data->dev_id; 186 const uint8_t port = data->port_id; 187 size_t fwd = 0, received = 0, tx = 0; 188 uint16_t i, nb_rx = 0, nb_tx = 0; 189 190 while (!fdata->done) { 191 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0); 192 193 if (!nb_rx) { 194 rte_pause(); 195 continue; 196 } 197 198 received += nb_rx; 199 200 for (i = 0; i < nb_rx; i++) { 201 rte_prefetch0(ev[i + 1].mbuf); 202 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) { 203 204 worker_tx_pkt(dev, port, &ev[i]); 205 ev[i].op = RTE_EVENT_OP_RELEASE; 206 tx++; 207 } else 208 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC); 209 work(); 210 } 211 212 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx); 213 fwd += nb_tx; 214 } 215 216 worker_cleanup(dev, port, ev, nb_tx, nb_rx); 217 218 if (!cdata.quiet) 219 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 220 rte_lcore_id(), received, fwd, tx); 221 return 0; 222 } 223 224 /* Multi stage Pipeline Workers */ 225 226 static int 227 worker_do_tx(void *arg) 228 { 229 struct rte_event ev; 230 231 struct worker_data *data = (struct worker_data *)arg; 232 const uint8_t dev = data->dev_id; 233 const uint8_t port = data->port_id; 234 const uint8_t lst_qid = cdata.num_stages - 1; 235 size_t fwd = 0, received = 0, tx = 0; 236 237 238 while (!fdata->done) { 239 240 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) { 241 rte_pause(); 242 continue; 243 } 244 245 received++; 246 const uint8_t cq_id = ev.queue_id % cdata.num_stages; 247 248 if (cq_id >= lst_qid) { 249 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 250 worker_tx_pkt(dev, port, &ev); 251 tx++; 252 continue; 253 } 254 255 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 256 ev.queue_id = (cq_id == lst_qid) ? 257 cdata.next_qid[ev.queue_id] : ev.queue_id; 258 } else { 259 ev.queue_id = cdata.next_qid[ev.queue_id]; 260 worker_fwd_event(&ev, cdata.queue_type); 261 } 262 work(); 263 264 worker_event_enqueue(dev, port, &ev); 265 fwd++; 266 } 267 268 if (ev.u64) { 269 ev.op = RTE_EVENT_OP_RELEASE; 270 rte_event_enqueue_burst(dev, port, &ev, 1); 271 } 272 273 if (!cdata.quiet) 274 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 275 rte_lcore_id(), received, fwd, tx); 276 277 return 0; 278 } 279 280 static int 281 worker_do_tx_atq(void *arg) 282 { 283 struct rte_event ev; 284 285 struct worker_data *data = (struct worker_data *)arg; 286 const uint8_t dev = data->dev_id; 287 const uint8_t port = data->port_id; 288 const uint8_t lst_qid = cdata.num_stages - 1; 289 size_t fwd = 0, received = 0, tx = 0; 290 291 while (!fdata->done) { 292 293 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) { 294 rte_pause(); 295 continue; 296 } 297 298 received++; 299 const uint8_t cq_id = ev.sub_event_type % cdata.num_stages; 300 301 if (cq_id == lst_qid) { 302 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 303 worker_tx_pkt(dev, port, &ev); 304 tx++; 305 continue; 306 } 307 308 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 309 } else { 310 ev.sub_event_type++; 311 worker_fwd_event(&ev, cdata.queue_type); 312 } 313 work(); 314 315 worker_event_enqueue(dev, port, &ev); 316 fwd++; 317 } 318 319 if (ev.u64) { 320 ev.op = RTE_EVENT_OP_RELEASE; 321 rte_event_enqueue_burst(dev, port, &ev, 1); 322 } 323 324 if (!cdata.quiet) 325 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 326 rte_lcore_id(), received, fwd, tx); 327 328 return 0; 329 } 330 331 static int 332 worker_do_tx_burst(void *arg) 333 { 334 struct rte_event ev[BATCH_SIZE]; 335 336 struct worker_data *data = (struct worker_data *)arg; 337 uint8_t dev = data->dev_id; 338 uint8_t port = data->port_id; 339 uint8_t lst_qid = cdata.num_stages - 1; 340 size_t fwd = 0, received = 0, tx = 0; 341 uint16_t i, nb_rx = 0, nb_tx = 0; 342 343 while (!fdata->done) { 344 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0); 345 346 if (nb_rx == 0) { 347 rte_pause(); 348 continue; 349 } 350 received += nb_rx; 351 352 for (i = 0; i < nb_rx; i++) { 353 const uint8_t cq_id = ev[i].queue_id % cdata.num_stages; 354 355 if (cq_id >= lst_qid) { 356 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) { 357 worker_tx_pkt(dev, port, &ev[i]); 358 tx++; 359 ev[i].op = RTE_EVENT_OP_RELEASE; 360 continue; 361 } 362 ev[i].queue_id = (cq_id == lst_qid) ? 363 cdata.next_qid[ev[i].queue_id] : 364 ev[i].queue_id; 365 366 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC); 367 } else { 368 ev[i].queue_id = cdata.next_qid[ev[i].queue_id]; 369 worker_fwd_event(&ev[i], cdata.queue_type); 370 } 371 work(); 372 } 373 374 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx); 375 fwd += nb_tx; 376 } 377 378 worker_cleanup(dev, port, ev, nb_tx, nb_rx); 379 380 if (!cdata.quiet) 381 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 382 rte_lcore_id(), received, fwd, tx); 383 384 return 0; 385 } 386 387 static int 388 worker_do_tx_burst_atq(void *arg) 389 { 390 struct rte_event ev[BATCH_SIZE]; 391 392 struct worker_data *data = (struct worker_data *)arg; 393 uint8_t dev = data->dev_id; 394 uint8_t port = data->port_id; 395 uint8_t lst_qid = cdata.num_stages - 1; 396 size_t fwd = 0, received = 0, tx = 0; 397 uint16_t i, nb_rx = 0, nb_tx = 0; 398 399 while (!fdata->done) { 400 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0); 401 402 if (nb_rx == 0) { 403 rte_pause(); 404 continue; 405 } 406 received += nb_rx; 407 408 for (i = 0; i < nb_rx; i++) { 409 const uint8_t cq_id = ev[i].sub_event_type % 410 cdata.num_stages; 411 412 if (cq_id == lst_qid) { 413 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) { 414 worker_tx_pkt(dev, port, &ev[i]); 415 tx++; 416 ev[i].op = RTE_EVENT_OP_RELEASE; 417 continue; 418 } 419 420 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC); 421 } else { 422 ev[i].sub_event_type++; 423 worker_fwd_event(&ev[i], cdata.queue_type); 424 } 425 work(); 426 } 427 428 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx); 429 fwd += nb_tx; 430 } 431 432 worker_cleanup(dev, port, ev, nb_tx, nb_rx); 433 434 if (!cdata.quiet) 435 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n", 436 rte_lcore_id(), received, fwd, tx); 437 438 return 0; 439 } 440 441 static int 442 setup_eventdev_worker_tx_enq(struct worker_data *worker_data) 443 { 444 uint8_t i; 445 const uint8_t atq = cdata.all_type_queues ? 1 : 0; 446 const uint8_t dev_id = 0; 447 const uint8_t nb_ports = cdata.num_workers; 448 uint8_t nb_slots = 0; 449 uint8_t nb_queues = rte_eth_dev_count_avail(); 450 451 /* 452 * In case where all type queues are not enabled, use queues equal to 453 * number of stages * eth_dev_count and one extra queue per pipeline 454 * for Tx. 455 */ 456 if (!atq) { 457 nb_queues *= cdata.num_stages; 458 nb_queues += rte_eth_dev_count_avail(); 459 } 460 461 struct rte_event_dev_config config = { 462 .nb_event_queues = nb_queues, 463 .nb_event_ports = nb_ports, 464 .nb_single_link_event_port_queues = 0, 465 .nb_events_limit = 4096, 466 .nb_event_queue_flows = 1024, 467 .nb_event_port_dequeue_depth = 128, 468 .nb_event_port_enqueue_depth = 128, 469 }; 470 struct rte_event_port_conf wkr_p_conf = { 471 .dequeue_depth = cdata.worker_cq_depth, 472 .enqueue_depth = 64, 473 .new_event_threshold = 4096, 474 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_WORKER, 475 }; 476 struct rte_event_queue_conf wkr_q_conf = { 477 .schedule_type = cdata.queue_type, 478 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 479 .nb_atomic_flows = 1024, 480 .nb_atomic_order_sequences = 1024, 481 }; 482 483 int ret, ndev = rte_event_dev_count(); 484 485 if (ndev < 1) { 486 printf("%d: No Eventdev Devices Found\n", __LINE__); 487 return -1; 488 } 489 490 491 struct rte_event_dev_info dev_info; 492 ret = rte_event_dev_info_get(dev_id, &dev_info); 493 printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name); 494 495 if (dev_info.max_num_events < config.nb_events_limit) 496 config.nb_events_limit = dev_info.max_num_events; 497 if (dev_info.max_event_port_dequeue_depth < 498 config.nb_event_port_dequeue_depth) 499 config.nb_event_port_dequeue_depth = 500 dev_info.max_event_port_dequeue_depth; 501 if (dev_info.max_event_port_enqueue_depth < 502 config.nb_event_port_enqueue_depth) 503 config.nb_event_port_enqueue_depth = 504 dev_info.max_event_port_enqueue_depth; 505 506 ret = rte_event_dev_configure(dev_id, &config); 507 if (ret < 0) { 508 printf("%d: Error configuring device\n", __LINE__); 509 return -1; 510 } 511 512 printf(" Stages:\n"); 513 for (i = 0; i < nb_queues; i++) { 514 515 if (atq) { 516 517 nb_slots = cdata.num_stages; 518 wkr_q_conf.event_queue_cfg = 519 RTE_EVENT_QUEUE_CFG_ALL_TYPES; 520 } else { 521 uint8_t slot; 522 523 nb_slots = cdata.num_stages + 1; 524 slot = i % nb_slots; 525 wkr_q_conf.schedule_type = slot == cdata.num_stages ? 526 RTE_SCHED_TYPE_ATOMIC : cdata.queue_type; 527 } 528 529 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) { 530 printf("%d: error creating qid %d\n", __LINE__, i); 531 return -1; 532 } 533 cdata.qid[i] = i; 534 cdata.next_qid[i] = i+1; 535 if (cdata.enable_queue_priorities) { 536 const uint32_t prio_delta = 537 (RTE_EVENT_DEV_PRIORITY_LOWEST) / 538 nb_slots; 539 540 /* higher priority for queues closer to tx */ 541 wkr_q_conf.priority = 542 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * 543 (i % nb_slots); 544 } 545 546 const char *type_str = "Atomic"; 547 switch (wkr_q_conf.schedule_type) { 548 case RTE_SCHED_TYPE_ORDERED: 549 type_str = "Ordered"; 550 break; 551 case RTE_SCHED_TYPE_PARALLEL: 552 type_str = "Parallel"; 553 break; 554 } 555 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str, 556 wkr_q_conf.priority); 557 } 558 559 printf("\n"); 560 if (wkr_p_conf.new_event_threshold > config.nb_events_limit) 561 wkr_p_conf.new_event_threshold = config.nb_events_limit; 562 if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth) 563 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth; 564 if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth) 565 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth; 566 567 /* set up one port per worker, linking to all stage queues */ 568 for (i = 0; i < cdata.num_workers; i++) { 569 struct worker_data *w = &worker_data[i]; 570 w->dev_id = dev_id; 571 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) { 572 printf("Error setting up port %d\n", i); 573 return -1; 574 } 575 576 if (rte_event_port_link(dev_id, i, NULL, NULL, 0) 577 != nb_queues) { 578 printf("%d: error creating link for port %d\n", 579 __LINE__, i); 580 return -1; 581 } 582 w->port_id = i; 583 } 584 /* 585 * Reduce the load on ingress event queue by splitting the traffic 586 * across multiple event queues. 587 * for example, nb_stages = 2 and nb_ethdev = 2 then 588 * 589 * nb_queues = (2 * 2) + 2 = 6 (non atq) 590 * rx_stride = 3 591 * 592 * So, traffic is split across queue 0 and queue 3 since queue id for 593 * rx adapter is chosen <ethport_id> * <rx_stride> i.e in the above 594 * case eth port 0, 1 will inject packets into event queue 0, 3 595 * respectively. 596 * 597 * This forms two set of queue pipelines 0->1->2->tx and 3->4->5->tx. 598 */ 599 cdata.rx_stride = atq ? 1 : nb_slots; 600 ret = rte_event_dev_service_id_get(dev_id, 601 &fdata->evdev_service_id); 602 if (ret != -ESRCH && ret != 0) { 603 printf("Error getting the service ID\n"); 604 return -1; 605 } 606 rte_service_runstate_set(fdata->evdev_service_id, 1); 607 rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0); 608 609 if (rte_event_dev_start(dev_id) < 0) 610 rte_exit(EXIT_FAILURE, "Error starting eventdev"); 611 612 return dev_id; 613 } 614 615 616 struct rx_adptr_services { 617 uint16_t nb_rx_adptrs; 618 uint32_t *rx_adpt_arr; 619 }; 620 621 static int32_t 622 service_rx_adapter(void *arg) 623 { 624 int i; 625 struct rx_adptr_services *adptr_services = arg; 626 627 for (i = 0; i < adptr_services->nb_rx_adptrs; i++) 628 rte_service_run_iter_on_app_lcore( 629 adptr_services->rx_adpt_arr[i], 1); 630 return 0; 631 } 632 633 /* 634 * Initializes a given port using global settings and with the RX buffers 635 * coming from the mbuf_pool passed as a parameter. 636 */ 637 static inline int 638 port_init(uint8_t port, struct rte_mempool *mbuf_pool) 639 { 640 struct rte_eth_rxconf rx_conf; 641 static const struct rte_eth_conf port_conf_default = { 642 .rxmode = { 643 .mq_mode = RTE_ETH_MQ_RX_RSS, 644 }, 645 .rx_adv_conf = { 646 .rss_conf = { 647 .rss_hf = RTE_ETH_RSS_IP | 648 RTE_ETH_RSS_TCP | 649 RTE_ETH_RSS_UDP, 650 } 651 } 652 }; 653 const uint16_t rx_rings = 1, tx_rings = 1; 654 const uint16_t rx_ring_size = 512, tx_ring_size = 512; 655 struct rte_eth_conf port_conf = port_conf_default; 656 int retval; 657 uint16_t q; 658 struct rte_eth_dev_info dev_info; 659 struct rte_eth_txconf txconf; 660 661 if (!rte_eth_dev_is_valid_port(port)) 662 return -1; 663 664 retval = rte_eth_dev_info_get(port, &dev_info); 665 if (retval != 0) { 666 printf("Error during getting device (port %u) info: %s\n", 667 port, strerror(-retval)); 668 return retval; 669 } 670 671 if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) 672 port_conf.txmode.offloads |= 673 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 674 rx_conf = dev_info.default_rxconf; 675 rx_conf.offloads = port_conf.rxmode.offloads; 676 677 port_conf.rx_adv_conf.rss_conf.rss_hf &= 678 dev_info.flow_type_rss_offloads; 679 if (port_conf.rx_adv_conf.rss_conf.rss_hf != 680 port_conf_default.rx_adv_conf.rss_conf.rss_hf) { 681 printf("Port %u modified RSS hash function based on hardware support," 682 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 683 port, 684 port_conf_default.rx_adv_conf.rss_conf.rss_hf, 685 port_conf.rx_adv_conf.rss_conf.rss_hf); 686 } 687 688 /* Configure the Ethernet device. */ 689 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf); 690 if (retval != 0) 691 return retval; 692 693 /* Allocate and set up 1 RX queue per Ethernet port. */ 694 for (q = 0; q < rx_rings; q++) { 695 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size, 696 rte_eth_dev_socket_id(port), &rx_conf, 697 mbuf_pool); 698 if (retval < 0) 699 return retval; 700 } 701 702 txconf = dev_info.default_txconf; 703 txconf.offloads = port_conf_default.txmode.offloads; 704 /* Allocate and set up 1 TX queue per Ethernet port. */ 705 for (q = 0; q < tx_rings; q++) { 706 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size, 707 rte_eth_dev_socket_id(port), &txconf); 708 if (retval < 0) 709 return retval; 710 } 711 712 /* Display the port MAC address. */ 713 struct rte_ether_addr addr; 714 retval = rte_eth_macaddr_get(port, &addr); 715 if (retval != 0) { 716 printf("Failed to get MAC address (port %u): %s\n", 717 port, rte_strerror(-retval)); 718 return retval; 719 } 720 721 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8 722 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n", 723 (unsigned int)port, RTE_ETHER_ADDR_BYTES(&addr)); 724 725 /* Enable RX in promiscuous mode for the Ethernet device. */ 726 retval = rte_eth_promiscuous_enable(port); 727 if (retval != 0) 728 return retval; 729 730 return 0; 731 } 732 733 static int 734 init_ports(uint16_t num_ports) 735 { 736 uint16_t portid; 737 738 if (!cdata.num_mbuf) 739 cdata.num_mbuf = 16384 * num_ports; 740 741 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool", 742 /* mbufs */ cdata.num_mbuf, 743 /* cache_size */ 512, 744 /* priv_size*/ 0, 745 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE, 746 rte_socket_id()); 747 748 RTE_ETH_FOREACH_DEV(portid) 749 if (port_init(portid, mp) != 0) 750 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n", 751 portid); 752 753 return 0; 754 } 755 756 static void 757 init_adapters(uint16_t nb_ports) 758 { 759 int i; 760 int ret; 761 uint8_t evdev_id = 0; 762 struct rx_adptr_services *adptr_services = NULL; 763 struct rte_event_dev_info dev_info; 764 765 ret = rte_event_dev_info_get(evdev_id, &dev_info); 766 adptr_services = rte_zmalloc(NULL, sizeof(struct rx_adptr_services), 0); 767 768 struct rte_event_port_conf adptr_p_conf = { 769 .dequeue_depth = cdata.worker_cq_depth, 770 .enqueue_depth = 64, 771 .new_event_threshold = 4096, 772 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_PRODUCER, 773 }; 774 775 init_ports(nb_ports); 776 if (adptr_p_conf.new_event_threshold > dev_info.max_num_events) 777 adptr_p_conf.new_event_threshold = dev_info.max_num_events; 778 if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth) 779 adptr_p_conf.dequeue_depth = 780 dev_info.max_event_port_dequeue_depth; 781 if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth) 782 adptr_p_conf.enqueue_depth = 783 dev_info.max_event_port_enqueue_depth; 784 785 struct rte_event_eth_rx_adapter_queue_conf queue_conf; 786 memset(&queue_conf, 0, sizeof(queue_conf)); 787 queue_conf.ev.sched_type = cdata.queue_type; 788 789 for (i = 0; i < nb_ports; i++) { 790 uint32_t cap; 791 uint32_t service_id; 792 793 ret = rte_event_eth_rx_adapter_create(i, evdev_id, 794 &adptr_p_conf); 795 if (ret) 796 rte_exit(EXIT_FAILURE, 797 "failed to create rx adapter[%d]", i); 798 799 ret = rte_event_eth_rx_adapter_caps_get(evdev_id, i, &cap); 800 if (ret) 801 rte_exit(EXIT_FAILURE, 802 "failed to get event rx adapter " 803 "capabilities"); 804 805 queue_conf.ev.queue_id = cdata.rx_stride ? 806 (i * cdata.rx_stride) 807 : (uint8_t)cdata.qid[0]; 808 809 ret = rte_event_eth_rx_adapter_queue_add(i, i, -1, &queue_conf); 810 if (ret) 811 rte_exit(EXIT_FAILURE, 812 "Failed to add queues to Rx adapter"); 813 814 /* Producer needs to be scheduled. */ 815 if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) { 816 ret = rte_event_eth_rx_adapter_service_id_get(i, 817 &service_id); 818 if (ret != -ESRCH && ret != 0) { 819 rte_exit(EXIT_FAILURE, 820 "Error getting the service ID for rx adptr\n"); 821 } 822 823 rte_service_runstate_set(service_id, 1); 824 rte_service_set_runstate_mapped_check(service_id, 0); 825 826 adptr_services->nb_rx_adptrs++; 827 adptr_services->rx_adpt_arr = rte_realloc( 828 adptr_services->rx_adpt_arr, 829 adptr_services->nb_rx_adptrs * 830 sizeof(uint32_t), 0); 831 adptr_services->rx_adpt_arr[ 832 adptr_services->nb_rx_adptrs - 1] = 833 service_id; 834 } 835 836 ret = rte_event_eth_rx_adapter_start(i); 837 if (ret) 838 rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed", 839 i); 840 } 841 842 /* We already know that Tx adapter has INTERNAL port cap*/ 843 ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id, 844 &adptr_p_conf); 845 if (ret) 846 rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]", 847 cdata.tx_adapter_id); 848 849 for (i = 0; i < nb_ports; i++) { 850 ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i, 851 -1); 852 if (ret) 853 rte_exit(EXIT_FAILURE, 854 "Failed to add queues to Tx adapter"); 855 } 856 857 ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id); 858 if (ret) 859 rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed", 860 cdata.tx_adapter_id); 861 862 if (adptr_services->nb_rx_adptrs) { 863 struct rte_service_spec service; 864 865 memset(&service, 0, sizeof(struct rte_service_spec)); 866 snprintf(service.name, sizeof(service.name), "rx_service"); 867 service.callback = service_rx_adapter; 868 service.callback_userdata = (void *)adptr_services; 869 870 int32_t ret = rte_service_component_register(&service, 871 &fdata->rxadptr_service_id); 872 if (ret) 873 rte_exit(EXIT_FAILURE, 874 "Rx adapter service register failed"); 875 876 rte_service_runstate_set(fdata->rxadptr_service_id, 1); 877 rte_service_component_runstate_set(fdata->rxadptr_service_id, 878 1); 879 rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id, 880 0); 881 } else { 882 memset(fdata->rx_core, 0, sizeof(unsigned int) * MAX_NUM_CORE); 883 rte_free(adptr_services); 884 } 885 886 if (!adptr_services->nb_rx_adptrs && (dev_info.event_dev_cap & 887 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED)) 888 fdata->cap.scheduler = NULL; 889 } 890 891 static void 892 worker_tx_enq_opt_check(void) 893 { 894 int i; 895 int ret; 896 uint32_t cap = 0; 897 uint8_t rx_needed = 0; 898 uint8_t sched_needed = 0; 899 struct rte_event_dev_info eventdev_info; 900 901 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 902 rte_event_dev_info_get(0, &eventdev_info); 903 904 if (cdata.all_type_queues && !(eventdev_info.event_dev_cap & 905 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)) 906 rte_exit(EXIT_FAILURE, 907 "Event dev doesn't support all type queues\n"); 908 sched_needed = !(eventdev_info.event_dev_cap & 909 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED); 910 911 RTE_ETH_FOREACH_DEV(i) { 912 ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap); 913 if (ret) 914 rte_exit(EXIT_FAILURE, 915 "failed to get event rx adapter capabilities"); 916 rx_needed |= 917 !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT); 918 } 919 920 if (cdata.worker_lcore_mask == 0 || 921 (rx_needed && cdata.rx_lcore_mask == 0) || 922 (sched_needed && cdata.sched_lcore_mask == 0)) { 923 printf("Core part of pipeline was not assigned any cores. " 924 "This will stall the pipeline, please check core masks " 925 "(use -h for details on setting core masks):\n" 926 "\trx: %"PRIu64"\n\tsched: %"PRIu64 927 "\n\tworkers: %"PRIu64"\n", cdata.rx_lcore_mask, 928 cdata.sched_lcore_mask, cdata.worker_lcore_mask); 929 rte_exit(-1, "Fix core masks\n"); 930 } 931 932 if (!sched_needed) 933 memset(fdata->sched_core, 0, 934 sizeof(unsigned int) * MAX_NUM_CORE); 935 if (!rx_needed) 936 memset(fdata->rx_core, 0, 937 sizeof(unsigned int) * MAX_NUM_CORE); 938 939 memset(fdata->tx_core, 0, sizeof(unsigned int) * MAX_NUM_CORE); 940 } 941 942 static worker_loop 943 get_worker_loop_single_burst(uint8_t atq) 944 { 945 if (atq) 946 return worker_do_tx_single_burst_atq; 947 948 return worker_do_tx_single_burst; 949 } 950 951 static worker_loop 952 get_worker_loop_single_non_burst(uint8_t atq) 953 { 954 if (atq) 955 return worker_do_tx_single_atq; 956 957 return worker_do_tx_single; 958 } 959 960 static worker_loop 961 get_worker_loop_burst(uint8_t atq) 962 { 963 if (atq) 964 return worker_do_tx_burst_atq; 965 966 return worker_do_tx_burst; 967 } 968 969 static worker_loop 970 get_worker_loop_non_burst(uint8_t atq) 971 { 972 if (atq) 973 return worker_do_tx_atq; 974 975 return worker_do_tx; 976 } 977 978 static worker_loop 979 get_worker_single_stage(bool burst) 980 { 981 uint8_t atq = cdata.all_type_queues ? 1 : 0; 982 983 if (burst) 984 return get_worker_loop_single_burst(atq); 985 986 return get_worker_loop_single_non_burst(atq); 987 } 988 989 static worker_loop 990 get_worker_multi_stage(bool burst) 991 { 992 uint8_t atq = cdata.all_type_queues ? 1 : 0; 993 994 if (burst) 995 return get_worker_loop_burst(atq); 996 997 return get_worker_loop_non_burst(atq); 998 } 999 1000 void 1001 set_worker_tx_enq_setup_data(struct setup_data *caps, bool burst) 1002 { 1003 if (cdata.num_stages == 1) 1004 caps->worker = get_worker_single_stage(burst); 1005 else 1006 caps->worker = get_worker_multi_stage(burst); 1007 1008 caps->check_opt = worker_tx_enq_opt_check; 1009 caps->scheduler = schedule_devices; 1010 caps->evdev_setup = setup_eventdev_worker_tx_enq; 1011 caps->adptr_setup = init_adapters; 1012 } 1013