1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright 2016 Intel Corporation. 4 * Copyright 2017 Cavium, Inc. 5 */ 6 7 #include <stdlib.h> 8 9 #include "pipeline_common.h" 10 11 static __rte_always_inline int 12 worker_generic(void *arg) 13 { 14 struct rte_event ev; 15 16 struct worker_data *data = (struct worker_data *)arg; 17 uint8_t dev_id = data->dev_id; 18 uint8_t port_id = data->port_id; 19 size_t sent = 0, received = 0; 20 unsigned int lcore_id = rte_lcore_id(); 21 uint16_t nb_rx = 0, nb_tx = 0; 22 23 while (!fdata->done) { 24 25 if (fdata->cap.scheduler) 26 fdata->cap.scheduler(lcore_id); 27 28 if (!fdata->worker_core[lcore_id]) { 29 rte_pause(); 30 continue; 31 } 32 33 nb_rx = rte_event_dequeue_burst(dev_id, port_id, &ev, 1, 0); 34 35 if (nb_rx == 0) { 36 rte_pause(); 37 continue; 38 } 39 received++; 40 41 /* The first worker stage does classification */ 42 if (ev.queue_id == cdata.qid[0]) 43 ev.flow_id = ev.mbuf->hash.rss 44 % cdata.num_fids; 45 46 ev.queue_id = cdata.next_qid[ev.queue_id]; 47 ev.op = RTE_EVENT_OP_FORWARD; 48 ev.sched_type = cdata.queue_type; 49 50 work(); 51 52 do { 53 nb_tx = rte_event_enqueue_burst(dev_id, port_id, &ev, 54 1); 55 } while (!nb_tx && !fdata->done); 56 sent++; 57 } 58 59 worker_cleanup(dev_id, port_id, &ev, nb_tx, nb_rx); 60 if (!cdata.quiet) 61 printf(" worker %u thread done. RX=%zu TX=%zu\n", 62 rte_lcore_id(), received, sent); 63 64 return 0; 65 } 66 67 static int 68 worker_generic_burst(void *arg) 69 { 70 struct rte_event events[BATCH_SIZE]; 71 72 struct worker_data *data = (struct worker_data *)arg; 73 uint8_t dev_id = data->dev_id; 74 uint8_t port_id = data->port_id; 75 size_t sent = 0, received = 0; 76 unsigned int lcore_id = rte_lcore_id(); 77 uint16_t i, nb_rx = 0, nb_tx = 0; 78 79 while (!fdata->done) { 80 if (fdata->cap.scheduler) 81 fdata->cap.scheduler(lcore_id); 82 83 if (!fdata->worker_core[lcore_id]) { 84 rte_pause(); 85 continue; 86 } 87 88 nb_rx = rte_event_dequeue_burst(dev_id, port_id, events, 89 RTE_DIM(events), 0); 90 91 if (nb_rx == 0) { 92 rte_pause(); 93 continue; 94 } 95 received += nb_rx; 96 97 for (i = 0; i < nb_rx; i++) { 98 99 /* The first worker stage does classification */ 100 if (events[i].queue_id == cdata.qid[0]) 101 events[i].flow_id = events[i].mbuf->hash.rss 102 % cdata.num_fids; 103 104 events[i].queue_id = cdata.next_qid[events[i].queue_id]; 105 events[i].op = RTE_EVENT_OP_FORWARD; 106 events[i].sched_type = cdata.queue_type; 107 108 work(); 109 } 110 nb_tx = rte_event_enqueue_burst(dev_id, port_id, events, nb_rx); 111 while (nb_tx < nb_rx && !fdata->done) 112 nb_tx += rte_event_enqueue_burst(dev_id, port_id, 113 events + nb_tx, 114 nb_rx - nb_tx); 115 sent += nb_tx; 116 } 117 118 worker_cleanup(dev_id, port_id, events, nb_tx, nb_rx); 119 120 if (!cdata.quiet) 121 printf(" worker %u thread done. RX=%zu TX=%zu\n", 122 rte_lcore_id(), received, sent); 123 124 return 0; 125 } 126 127 static int 128 setup_eventdev_generic(struct worker_data *worker_data) 129 { 130 const uint8_t dev_id = 0; 131 /* +1 stages is for a SINGLE_LINK TX stage */ 132 const uint8_t nb_queues = cdata.num_stages + 1; 133 const uint8_t nb_ports = cdata.num_workers; 134 struct rte_event_dev_config config = { 135 .nb_event_queues = nb_queues, 136 .nb_event_ports = nb_ports, 137 .nb_single_link_event_port_queues = 1, 138 .nb_events_limit = 4096, 139 .nb_event_queue_flows = 1024, 140 .nb_event_port_dequeue_depth = 128, 141 .nb_event_port_enqueue_depth = 128, 142 }; 143 struct rte_event_port_conf wkr_p_conf = { 144 .dequeue_depth = cdata.worker_cq_depth, 145 .enqueue_depth = 64, 146 .new_event_threshold = 4096, 147 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_WORKER, 148 }; 149 struct rte_event_queue_conf wkr_q_conf = { 150 .schedule_type = cdata.queue_type, 151 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 152 .nb_atomic_flows = 1024, 153 .nb_atomic_order_sequences = 1024, 154 }; 155 struct rte_event_queue_conf tx_q_conf = { 156 .priority = RTE_EVENT_DEV_PRIORITY_HIGHEST, 157 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_SINGLE_LINK, 158 }; 159 160 struct port_link worker_queues[MAX_NUM_STAGES]; 161 uint8_t disable_implicit_release; 162 unsigned int i; 163 164 int ret, ndev = rte_event_dev_count(); 165 if (ndev < 1) { 166 printf("%d: No Eventdev Devices Found\n", __LINE__); 167 return -1; 168 } 169 170 struct rte_event_dev_info dev_info; 171 ret = rte_event_dev_info_get(dev_id, &dev_info); 172 printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name); 173 174 disable_implicit_release = (dev_info.event_dev_cap & 175 RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE); 176 177 wkr_p_conf.event_port_cfg = disable_implicit_release ? 178 RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL : 0; 179 180 if (dev_info.max_num_events < config.nb_events_limit) 181 config.nb_events_limit = dev_info.max_num_events; 182 if (dev_info.max_event_port_dequeue_depth < 183 config.nb_event_port_dequeue_depth) 184 config.nb_event_port_dequeue_depth = 185 dev_info.max_event_port_dequeue_depth; 186 if (dev_info.max_event_port_enqueue_depth < 187 config.nb_event_port_enqueue_depth) 188 config.nb_event_port_enqueue_depth = 189 dev_info.max_event_port_enqueue_depth; 190 191 ret = rte_event_dev_configure(dev_id, &config); 192 if (ret < 0) { 193 printf("%d: Error configuring device\n", __LINE__); 194 return -1; 195 } 196 197 /* Q creation - one load balanced per pipeline stage*/ 198 printf(" Stages:\n"); 199 for (i = 0; i < cdata.num_stages; i++) { 200 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) { 201 printf("%d: error creating qid %d\n", __LINE__, i); 202 return -1; 203 } 204 cdata.qid[i] = i; 205 cdata.next_qid[i] = i+1; 206 worker_queues[i].queue_id = i; 207 if (cdata.enable_queue_priorities) { 208 /* calculate priority stepping for each stage, leaving 209 * headroom of 1 for the SINGLE_LINK TX below 210 */ 211 const uint32_t prio_delta = 212 (RTE_EVENT_DEV_PRIORITY_LOWEST-1) / nb_queues; 213 214 /* higher priority for queues closer to tx */ 215 wkr_q_conf.priority = 216 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i; 217 } 218 219 const char *type_str = "Atomic"; 220 switch (wkr_q_conf.schedule_type) { 221 case RTE_SCHED_TYPE_ORDERED: 222 type_str = "Ordered"; 223 break; 224 case RTE_SCHED_TYPE_PARALLEL: 225 type_str = "Parallel"; 226 break; 227 } 228 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str, 229 wkr_q_conf.priority); 230 } 231 printf("\n"); 232 233 /* final queue for sending to TX core */ 234 if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) { 235 printf("%d: error creating qid %d\n", __LINE__, i); 236 return -1; 237 } 238 cdata.tx_queue_id = i; 239 240 if (wkr_p_conf.new_event_threshold > config.nb_events_limit) 241 wkr_p_conf.new_event_threshold = config.nb_events_limit; 242 if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth) 243 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth; 244 if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth) 245 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth; 246 247 /* set up one port per worker, linking to all stage queues */ 248 for (i = 0; i < cdata.num_workers; i++) { 249 struct worker_data *w = &worker_data[i]; 250 w->dev_id = dev_id; 251 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) { 252 printf("Error setting up port %d\n", i); 253 return -1; 254 } 255 256 uint32_t s; 257 for (s = 0; s < cdata.num_stages; s++) { 258 if (rte_event_port_link(dev_id, i, 259 &worker_queues[s].queue_id, 260 &worker_queues[s].priority, 261 1) != 1) { 262 printf("%d: error creating link for port %d\n", 263 __LINE__, i); 264 return -1; 265 } 266 } 267 w->port_id = i; 268 } 269 270 ret = rte_event_dev_service_id_get(dev_id, 271 &fdata->evdev_service_id); 272 if (ret != -ESRCH && ret != 0) { 273 printf("Error getting the service ID for sw eventdev\n"); 274 return -1; 275 } 276 rte_service_runstate_set(fdata->evdev_service_id, 1); 277 rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0); 278 279 return dev_id; 280 } 281 282 /* 283 * Initializes a given port using global settings and with the RX buffers 284 * coming from the mbuf_pool passed as a parameter. 285 */ 286 static inline int 287 port_init(uint8_t port, struct rte_mempool *mbuf_pool) 288 { 289 struct rte_eth_rxconf rx_conf; 290 static const struct rte_eth_conf port_conf_default = { 291 .rxmode = { 292 .mq_mode = RTE_ETH_MQ_RX_RSS, 293 }, 294 .rx_adv_conf = { 295 .rss_conf = { 296 .rss_hf = RTE_ETH_RSS_IP | 297 RTE_ETH_RSS_TCP | 298 RTE_ETH_RSS_UDP, 299 } 300 } 301 }; 302 const uint16_t rx_rings = 1, tx_rings = 1; 303 const uint16_t rx_ring_size = 512, tx_ring_size = 512; 304 struct rte_eth_conf port_conf = port_conf_default; 305 int retval; 306 uint16_t q; 307 struct rte_eth_dev_info dev_info; 308 struct rte_eth_txconf txconf; 309 310 if (!rte_eth_dev_is_valid_port(port)) 311 return -1; 312 313 retval = rte_eth_dev_info_get(port, &dev_info); 314 if (retval != 0) { 315 printf("Error during getting device (port %u) info: %s\n", 316 port, strerror(-retval)); 317 return retval; 318 } 319 320 if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) 321 port_conf.txmode.offloads |= 322 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 323 324 if (dev_info.rx_offload_capa & RTE_ETH_RX_OFFLOAD_RSS_HASH) 325 port_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 326 327 rx_conf = dev_info.default_rxconf; 328 rx_conf.offloads = port_conf.rxmode.offloads; 329 330 port_conf.rx_adv_conf.rss_conf.rss_hf &= 331 dev_info.flow_type_rss_offloads; 332 if (port_conf.rx_adv_conf.rss_conf.rss_hf != 333 port_conf_default.rx_adv_conf.rss_conf.rss_hf) { 334 printf("Port %u modified RSS hash function based on hardware support," 335 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 336 port, 337 port_conf_default.rx_adv_conf.rss_conf.rss_hf, 338 port_conf.rx_adv_conf.rss_conf.rss_hf); 339 } 340 341 /* Configure the Ethernet device. */ 342 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf); 343 if (retval != 0) 344 return retval; 345 346 /* Allocate and set up 1 RX queue per Ethernet port. */ 347 for (q = 0; q < rx_rings; q++) { 348 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size, 349 rte_eth_dev_socket_id(port), &rx_conf, 350 mbuf_pool); 351 if (retval < 0) 352 return retval; 353 } 354 355 txconf = dev_info.default_txconf; 356 txconf.offloads = port_conf_default.txmode.offloads; 357 /* Allocate and set up 1 TX queue per Ethernet port. */ 358 for (q = 0; q < tx_rings; q++) { 359 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size, 360 rte_eth_dev_socket_id(port), &txconf); 361 if (retval < 0) 362 return retval; 363 } 364 365 /* Display the port MAC address. */ 366 struct rte_ether_addr addr; 367 retval = rte_eth_macaddr_get(port, &addr); 368 if (retval != 0) { 369 printf("Failed to get MAC address (port %u): %s\n", 370 port, rte_strerror(-retval)); 371 return retval; 372 } 373 374 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8 375 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n", 376 (unsigned int)port, RTE_ETHER_ADDR_BYTES(&addr)); 377 378 /* Enable RX in promiscuous mode for the Ethernet device. */ 379 retval = rte_eth_promiscuous_enable(port); 380 if (retval != 0) 381 return retval; 382 383 return 0; 384 } 385 386 static int 387 init_ports(uint16_t num_ports) 388 { 389 uint16_t portid; 390 391 if (!cdata.num_mbuf) 392 cdata.num_mbuf = 16384 * num_ports; 393 394 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool", 395 /* mbufs */ cdata.num_mbuf, 396 /* cache_size */ 512, 397 /* priv_size*/ 0, 398 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE, 399 rte_socket_id()); 400 401 RTE_ETH_FOREACH_DEV(portid) 402 if (port_init(portid, mp) != 0) 403 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n", 404 portid); 405 406 return 0; 407 } 408 409 static void 410 init_adapters(uint16_t nb_ports) 411 { 412 int i; 413 int ret; 414 uint8_t tx_port_id = 0; 415 uint8_t evdev_id = 0; 416 struct rte_event_dev_info dev_info; 417 418 ret = rte_event_dev_info_get(evdev_id, &dev_info); 419 420 struct rte_event_port_conf adptr_p_conf = { 421 .dequeue_depth = cdata.worker_cq_depth, 422 .enqueue_depth = 64, 423 .new_event_threshold = 4096, 424 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_PRODUCER, 425 }; 426 427 if (adptr_p_conf.new_event_threshold > dev_info.max_num_events) 428 adptr_p_conf.new_event_threshold = dev_info.max_num_events; 429 if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth) 430 adptr_p_conf.dequeue_depth = 431 dev_info.max_event_port_dequeue_depth; 432 if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth) 433 adptr_p_conf.enqueue_depth = 434 dev_info.max_event_port_enqueue_depth; 435 436 init_ports(nb_ports); 437 /* Create one adapter for all the ethernet ports. */ 438 ret = rte_event_eth_rx_adapter_create(cdata.rx_adapter_id, evdev_id, 439 &adptr_p_conf); 440 if (ret) 441 rte_exit(EXIT_FAILURE, "failed to create rx adapter[%d]", 442 cdata.rx_adapter_id); 443 444 ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id, 445 &adptr_p_conf); 446 if (ret) 447 rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]", 448 cdata.tx_adapter_id); 449 450 struct rte_event_eth_rx_adapter_queue_conf queue_conf; 451 memset(&queue_conf, 0, sizeof(queue_conf)); 452 queue_conf.ev.sched_type = cdata.queue_type; 453 queue_conf.ev.queue_id = cdata.qid[0]; 454 455 for (i = 0; i < nb_ports; i++) { 456 ret = rte_event_eth_rx_adapter_queue_add(cdata.rx_adapter_id, i, 457 -1, &queue_conf); 458 if (ret) 459 rte_exit(EXIT_FAILURE, 460 "Failed to add queues to Rx adapter"); 461 462 ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i, 463 -1); 464 if (ret) 465 rte_exit(EXIT_FAILURE, 466 "Failed to add queues to Tx adapter"); 467 } 468 469 ret = rte_event_eth_tx_adapter_event_port_get(cdata.tx_adapter_id, 470 &tx_port_id); 471 if (ret) 472 rte_exit(EXIT_FAILURE, 473 "Failed to get Tx adapter port id"); 474 ret = rte_event_port_link(evdev_id, tx_port_id, &cdata.tx_queue_id, 475 NULL, 1); 476 if (ret != 1) 477 rte_exit(EXIT_FAILURE, 478 "Unable to link Tx adapter port to Tx queue"); 479 480 ret = rte_event_eth_rx_adapter_service_id_get(cdata.rx_adapter_id, 481 &fdata->rxadptr_service_id); 482 if (ret != -ESRCH && ret != 0) { 483 rte_exit(EXIT_FAILURE, 484 "Error getting the service ID for Rx adapter\n"); 485 } 486 rte_service_runstate_set(fdata->rxadptr_service_id, 1); 487 rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id, 0); 488 489 ret = rte_event_eth_tx_adapter_service_id_get(cdata.tx_adapter_id, 490 &fdata->txadptr_service_id); 491 if (ret != -ESRCH && ret != 0) { 492 rte_exit(EXIT_FAILURE, 493 "Error getting the service ID for Tx adapter\n"); 494 } 495 rte_service_runstate_set(fdata->txadptr_service_id, 1); 496 rte_service_set_runstate_mapped_check(fdata->txadptr_service_id, 0); 497 498 ret = rte_event_eth_rx_adapter_start(cdata.rx_adapter_id); 499 if (ret) 500 rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed", 501 cdata.rx_adapter_id); 502 503 ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id); 504 if (ret) 505 rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed", 506 cdata.tx_adapter_id); 507 508 if (rte_event_dev_start(evdev_id) < 0) 509 rte_exit(EXIT_FAILURE, "Error starting eventdev"); 510 } 511 512 static void 513 generic_opt_check(void) 514 { 515 int i; 516 int ret; 517 uint32_t cap = 0; 518 uint8_t rx_needed = 0; 519 uint8_t sched_needed = 0; 520 struct rte_event_dev_info eventdev_info; 521 522 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 523 rte_event_dev_info_get(0, &eventdev_info); 524 525 if (cdata.all_type_queues && !(eventdev_info.event_dev_cap & 526 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)) 527 rte_exit(EXIT_FAILURE, 528 "Event dev doesn't support all type queues\n"); 529 sched_needed = !(eventdev_info.event_dev_cap & 530 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED); 531 532 RTE_ETH_FOREACH_DEV(i) { 533 ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap); 534 if (ret) 535 rte_exit(EXIT_FAILURE, 536 "failed to get event rx adapter capabilities"); 537 rx_needed |= 538 !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT); 539 } 540 541 if (cdata.worker_lcore_mask == 0 || 542 (rx_needed && cdata.rx_lcore_mask == 0) || 543 (cdata.tx_lcore_mask == 0) || 544 (sched_needed && cdata.sched_lcore_mask == 0)) { 545 printf("Core part of pipeline was not assigned any cores. " 546 "This will stall the pipeline, please check core masks " 547 "(use -h for details on setting core masks):\n" 548 "\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64 549 "\n\tworkers: %"PRIu64"\n", 550 cdata.rx_lcore_mask, cdata.tx_lcore_mask, 551 cdata.sched_lcore_mask, 552 cdata.worker_lcore_mask); 553 rte_exit(-1, "Fix core masks\n"); 554 } 555 556 if (!sched_needed) 557 memset(fdata->sched_core, 0, 558 sizeof(unsigned int) * MAX_NUM_CORE); 559 if (!rx_needed) 560 memset(fdata->rx_core, 0, 561 sizeof(unsigned int) * MAX_NUM_CORE); 562 } 563 564 void 565 set_worker_generic_setup_data(struct setup_data *caps, bool burst) 566 { 567 if (burst) { 568 caps->worker = worker_generic_burst; 569 } else { 570 caps->worker = worker_generic; 571 } 572 573 caps->adptr_setup = init_adapters; 574 caps->scheduler = schedule_devices; 575 caps->evdev_setup = setup_eventdev_generic; 576 caps->check_opt = generic_opt_check; 577 } 578