1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright 2016 Intel Corporation. 4 * Copyright 2017 Cavium, Inc. 5 */ 6 7 #include "pipeline_common.h" 8 9 static __rte_always_inline int 10 worker_generic(void *arg) 11 { 12 struct rte_event ev; 13 14 struct worker_data *data = (struct worker_data *)arg; 15 uint8_t dev_id = data->dev_id; 16 uint8_t port_id = data->port_id; 17 size_t sent = 0, received = 0; 18 unsigned int lcore_id = rte_lcore_id(); 19 uint16_t nb_rx = 0, nb_tx = 0; 20 21 while (!fdata->done) { 22 23 if (fdata->cap.scheduler) 24 fdata->cap.scheduler(lcore_id); 25 26 if (!fdata->worker_core[lcore_id]) { 27 rte_pause(); 28 continue; 29 } 30 31 nb_rx = rte_event_dequeue_burst(dev_id, port_id, &ev, 1, 0); 32 33 if (nb_rx == 0) { 34 rte_pause(); 35 continue; 36 } 37 received++; 38 39 /* The first worker stage does classification */ 40 if (ev.queue_id == cdata.qid[0]) 41 ev.flow_id = ev.mbuf->hash.rss 42 % cdata.num_fids; 43 44 ev.queue_id = cdata.next_qid[ev.queue_id]; 45 ev.op = RTE_EVENT_OP_FORWARD; 46 ev.sched_type = cdata.queue_type; 47 48 work(); 49 50 do { 51 nb_tx = rte_event_enqueue_burst(dev_id, port_id, &ev, 52 1); 53 } while (!nb_tx && !fdata->done); 54 sent++; 55 } 56 57 worker_cleanup(dev_id, port_id, &ev, nb_tx, nb_rx); 58 if (!cdata.quiet) 59 printf(" worker %u thread done. RX=%zu TX=%zu\n", 60 rte_lcore_id(), received, sent); 61 62 return 0; 63 } 64 65 static int 66 worker_generic_burst(void *arg) 67 { 68 struct rte_event events[BATCH_SIZE]; 69 70 struct worker_data *data = (struct worker_data *)arg; 71 uint8_t dev_id = data->dev_id; 72 uint8_t port_id = data->port_id; 73 size_t sent = 0, received = 0; 74 unsigned int lcore_id = rte_lcore_id(); 75 uint16_t i, nb_rx = 0, nb_tx = 0; 76 77 while (!fdata->done) { 78 if (fdata->cap.scheduler) 79 fdata->cap.scheduler(lcore_id); 80 81 if (!fdata->worker_core[lcore_id]) { 82 rte_pause(); 83 continue; 84 } 85 86 nb_rx = rte_event_dequeue_burst(dev_id, port_id, events, 87 RTE_DIM(events), 0); 88 89 if (nb_rx == 0) { 90 rte_pause(); 91 continue; 92 } 93 received += nb_rx; 94 95 for (i = 0; i < nb_rx; i++) { 96 97 /* The first worker stage does classification */ 98 if (events[i].queue_id == cdata.qid[0]) 99 events[i].flow_id = events[i].mbuf->hash.rss 100 % cdata.num_fids; 101 102 events[i].queue_id = cdata.next_qid[events[i].queue_id]; 103 events[i].op = RTE_EVENT_OP_FORWARD; 104 events[i].sched_type = cdata.queue_type; 105 106 work(); 107 } 108 nb_tx = rte_event_enqueue_burst(dev_id, port_id, events, nb_rx); 109 while (nb_tx < nb_rx && !fdata->done) 110 nb_tx += rte_event_enqueue_burst(dev_id, port_id, 111 events + nb_tx, 112 nb_rx - nb_tx); 113 sent += nb_tx; 114 } 115 116 worker_cleanup(dev_id, port_id, events, nb_tx, nb_rx); 117 118 if (!cdata.quiet) 119 printf(" worker %u thread done. RX=%zu TX=%zu\n", 120 rte_lcore_id(), received, sent); 121 122 return 0; 123 } 124 125 static int 126 setup_eventdev_generic(struct worker_data *worker_data) 127 { 128 const uint8_t dev_id = 0; 129 /* +1 stages is for a SINGLE_LINK TX stage */ 130 const uint8_t nb_queues = cdata.num_stages + 1; 131 const uint8_t nb_ports = cdata.num_workers; 132 struct rte_event_dev_config config = { 133 .nb_event_queues = nb_queues, 134 .nb_event_ports = nb_ports, 135 .nb_single_link_event_port_queues = 1, 136 .nb_events_limit = 4096, 137 .nb_event_queue_flows = 1024, 138 .nb_event_port_dequeue_depth = 128, 139 .nb_event_port_enqueue_depth = 128, 140 }; 141 struct rte_event_port_conf wkr_p_conf = { 142 .dequeue_depth = cdata.worker_cq_depth, 143 .enqueue_depth = 64, 144 .new_event_threshold = 4096, 145 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_WORKER, 146 }; 147 struct rte_event_queue_conf wkr_q_conf = { 148 .schedule_type = cdata.queue_type, 149 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 150 .nb_atomic_flows = 1024, 151 .nb_atomic_order_sequences = 1024, 152 }; 153 struct rte_event_queue_conf tx_q_conf = { 154 .priority = RTE_EVENT_DEV_PRIORITY_HIGHEST, 155 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_SINGLE_LINK, 156 }; 157 158 struct port_link worker_queues[MAX_NUM_STAGES]; 159 uint8_t disable_implicit_release; 160 unsigned int i; 161 162 int ret, ndev = rte_event_dev_count(); 163 if (ndev < 1) { 164 printf("%d: No Eventdev Devices Found\n", __LINE__); 165 return -1; 166 } 167 168 struct rte_event_dev_info dev_info; 169 ret = rte_event_dev_info_get(dev_id, &dev_info); 170 printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name); 171 172 disable_implicit_release = (dev_info.event_dev_cap & 173 RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE); 174 175 wkr_p_conf.event_port_cfg = disable_implicit_release ? 176 RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL : 0; 177 178 if (dev_info.max_num_events < config.nb_events_limit) 179 config.nb_events_limit = dev_info.max_num_events; 180 if (dev_info.max_event_port_dequeue_depth < 181 config.nb_event_port_dequeue_depth) 182 config.nb_event_port_dequeue_depth = 183 dev_info.max_event_port_dequeue_depth; 184 if (dev_info.max_event_port_enqueue_depth < 185 config.nb_event_port_enqueue_depth) 186 config.nb_event_port_enqueue_depth = 187 dev_info.max_event_port_enqueue_depth; 188 189 ret = rte_event_dev_configure(dev_id, &config); 190 if (ret < 0) { 191 printf("%d: Error configuring device\n", __LINE__); 192 return -1; 193 } 194 195 /* Q creation - one load balanced per pipeline stage*/ 196 printf(" Stages:\n"); 197 for (i = 0; i < cdata.num_stages; i++) { 198 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) { 199 printf("%d: error creating qid %d\n", __LINE__, i); 200 return -1; 201 } 202 cdata.qid[i] = i; 203 cdata.next_qid[i] = i+1; 204 worker_queues[i].queue_id = i; 205 if (cdata.enable_queue_priorities) { 206 /* calculate priority stepping for each stage, leaving 207 * headroom of 1 for the SINGLE_LINK TX below 208 */ 209 const uint32_t prio_delta = 210 (RTE_EVENT_DEV_PRIORITY_LOWEST-1) / nb_queues; 211 212 /* higher priority for queues closer to tx */ 213 wkr_q_conf.priority = 214 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i; 215 } 216 217 const char *type_str = "Atomic"; 218 switch (wkr_q_conf.schedule_type) { 219 case RTE_SCHED_TYPE_ORDERED: 220 type_str = "Ordered"; 221 break; 222 case RTE_SCHED_TYPE_PARALLEL: 223 type_str = "Parallel"; 224 break; 225 } 226 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str, 227 wkr_q_conf.priority); 228 } 229 printf("\n"); 230 231 /* final queue for sending to TX core */ 232 if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) { 233 printf("%d: error creating qid %d\n", __LINE__, i); 234 return -1; 235 } 236 cdata.tx_queue_id = i; 237 238 if (wkr_p_conf.new_event_threshold > config.nb_events_limit) 239 wkr_p_conf.new_event_threshold = config.nb_events_limit; 240 if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth) 241 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth; 242 if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth) 243 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth; 244 245 /* set up one port per worker, linking to all stage queues */ 246 for (i = 0; i < cdata.num_workers; i++) { 247 struct worker_data *w = &worker_data[i]; 248 w->dev_id = dev_id; 249 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) { 250 printf("Error setting up port %d\n", i); 251 return -1; 252 } 253 254 uint32_t s; 255 for (s = 0; s < cdata.num_stages; s++) { 256 if (rte_event_port_link(dev_id, i, 257 &worker_queues[s].queue_id, 258 &worker_queues[s].priority, 259 1) != 1) { 260 printf("%d: error creating link for port %d\n", 261 __LINE__, i); 262 return -1; 263 } 264 } 265 w->port_id = i; 266 } 267 268 ret = rte_event_dev_service_id_get(dev_id, 269 &fdata->evdev_service_id); 270 if (ret != -ESRCH && ret != 0) { 271 printf("Error getting the service ID for sw eventdev\n"); 272 return -1; 273 } 274 rte_service_runstate_set(fdata->evdev_service_id, 1); 275 rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0); 276 277 return dev_id; 278 } 279 280 /* 281 * Initializes a given port using global settings and with the RX buffers 282 * coming from the mbuf_pool passed as a parameter. 283 */ 284 static inline int 285 port_init(uint8_t port, struct rte_mempool *mbuf_pool) 286 { 287 struct rte_eth_rxconf rx_conf; 288 static const struct rte_eth_conf port_conf_default = { 289 .rxmode = { 290 .mq_mode = RTE_ETH_MQ_RX_RSS, 291 }, 292 .rx_adv_conf = { 293 .rss_conf = { 294 .rss_hf = RTE_ETH_RSS_IP | 295 RTE_ETH_RSS_TCP | 296 RTE_ETH_RSS_UDP, 297 } 298 } 299 }; 300 const uint16_t rx_rings = 1, tx_rings = 1; 301 const uint16_t rx_ring_size = 512, tx_ring_size = 512; 302 struct rte_eth_conf port_conf = port_conf_default; 303 int retval; 304 uint16_t q; 305 struct rte_eth_dev_info dev_info; 306 struct rte_eth_txconf txconf; 307 308 if (!rte_eth_dev_is_valid_port(port)) 309 return -1; 310 311 retval = rte_eth_dev_info_get(port, &dev_info); 312 if (retval != 0) { 313 printf("Error during getting device (port %u) info: %s\n", 314 port, strerror(-retval)); 315 return retval; 316 } 317 318 if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) 319 port_conf.txmode.offloads |= 320 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 321 322 if (dev_info.rx_offload_capa & RTE_ETH_RX_OFFLOAD_RSS_HASH) 323 port_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 324 325 rx_conf = dev_info.default_rxconf; 326 rx_conf.offloads = port_conf.rxmode.offloads; 327 328 port_conf.rx_adv_conf.rss_conf.rss_hf &= 329 dev_info.flow_type_rss_offloads; 330 if (port_conf.rx_adv_conf.rss_conf.rss_hf != 331 port_conf_default.rx_adv_conf.rss_conf.rss_hf) { 332 printf("Port %u modified RSS hash function based on hardware support," 333 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 334 port, 335 port_conf_default.rx_adv_conf.rss_conf.rss_hf, 336 port_conf.rx_adv_conf.rss_conf.rss_hf); 337 } 338 339 /* Configure the Ethernet device. */ 340 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf); 341 if (retval != 0) 342 return retval; 343 344 /* Allocate and set up 1 RX queue per Ethernet port. */ 345 for (q = 0; q < rx_rings; q++) { 346 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size, 347 rte_eth_dev_socket_id(port), &rx_conf, 348 mbuf_pool); 349 if (retval < 0) 350 return retval; 351 } 352 353 txconf = dev_info.default_txconf; 354 txconf.offloads = port_conf_default.txmode.offloads; 355 /* Allocate and set up 1 TX queue per Ethernet port. */ 356 for (q = 0; q < tx_rings; q++) { 357 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size, 358 rte_eth_dev_socket_id(port), &txconf); 359 if (retval < 0) 360 return retval; 361 } 362 363 /* Display the port MAC address. */ 364 struct rte_ether_addr addr; 365 retval = rte_eth_macaddr_get(port, &addr); 366 if (retval != 0) { 367 printf("Failed to get MAC address (port %u): %s\n", 368 port, rte_strerror(-retval)); 369 return retval; 370 } 371 372 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8 373 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n", 374 (unsigned int)port, RTE_ETHER_ADDR_BYTES(&addr)); 375 376 /* Enable RX in promiscuous mode for the Ethernet device. */ 377 retval = rte_eth_promiscuous_enable(port); 378 if (retval != 0) 379 return retval; 380 381 return 0; 382 } 383 384 static int 385 init_ports(uint16_t num_ports) 386 { 387 uint16_t portid; 388 389 if (!cdata.num_mbuf) 390 cdata.num_mbuf = 16384 * num_ports; 391 392 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool", 393 /* mbufs */ cdata.num_mbuf, 394 /* cache_size */ 512, 395 /* priv_size*/ 0, 396 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE, 397 rte_socket_id()); 398 399 RTE_ETH_FOREACH_DEV(portid) 400 if (port_init(portid, mp) != 0) 401 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n", 402 portid); 403 404 return 0; 405 } 406 407 static void 408 init_adapters(uint16_t nb_ports) 409 { 410 int i; 411 int ret; 412 uint8_t tx_port_id = 0; 413 uint8_t evdev_id = 0; 414 struct rte_event_dev_info dev_info; 415 416 ret = rte_event_dev_info_get(evdev_id, &dev_info); 417 418 struct rte_event_port_conf adptr_p_conf = { 419 .dequeue_depth = cdata.worker_cq_depth, 420 .enqueue_depth = 64, 421 .new_event_threshold = 4096, 422 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_PRODUCER, 423 }; 424 425 if (adptr_p_conf.new_event_threshold > dev_info.max_num_events) 426 adptr_p_conf.new_event_threshold = dev_info.max_num_events; 427 if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth) 428 adptr_p_conf.dequeue_depth = 429 dev_info.max_event_port_dequeue_depth; 430 if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth) 431 adptr_p_conf.enqueue_depth = 432 dev_info.max_event_port_enqueue_depth; 433 434 init_ports(nb_ports); 435 /* Create one adapter for all the ethernet ports. */ 436 ret = rte_event_eth_rx_adapter_create(cdata.rx_adapter_id, evdev_id, 437 &adptr_p_conf); 438 if (ret) 439 rte_exit(EXIT_FAILURE, "failed to create rx adapter[%d]", 440 cdata.rx_adapter_id); 441 442 ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id, 443 &adptr_p_conf); 444 if (ret) 445 rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]", 446 cdata.tx_adapter_id); 447 448 struct rte_event_eth_rx_adapter_queue_conf queue_conf; 449 memset(&queue_conf, 0, sizeof(queue_conf)); 450 queue_conf.ev.sched_type = cdata.queue_type; 451 queue_conf.ev.queue_id = cdata.qid[0]; 452 453 for (i = 0; i < nb_ports; i++) { 454 ret = rte_event_eth_rx_adapter_queue_add(cdata.rx_adapter_id, i, 455 -1, &queue_conf); 456 if (ret) 457 rte_exit(EXIT_FAILURE, 458 "Failed to add queues to Rx adapter"); 459 460 ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i, 461 -1); 462 if (ret) 463 rte_exit(EXIT_FAILURE, 464 "Failed to add queues to Tx adapter"); 465 } 466 467 ret = rte_event_eth_tx_adapter_event_port_get(cdata.tx_adapter_id, 468 &tx_port_id); 469 if (ret) 470 rte_exit(EXIT_FAILURE, 471 "Failed to get Tx adapter port id"); 472 ret = rte_event_port_link(evdev_id, tx_port_id, &cdata.tx_queue_id, 473 NULL, 1); 474 if (ret != 1) 475 rte_exit(EXIT_FAILURE, 476 "Unable to link Tx adapter port to Tx queue"); 477 478 ret = rte_event_eth_rx_adapter_service_id_get(cdata.rx_adapter_id, 479 &fdata->rxadptr_service_id); 480 if (ret != -ESRCH && ret != 0) { 481 rte_exit(EXIT_FAILURE, 482 "Error getting the service ID for Rx adapter\n"); 483 } 484 rte_service_runstate_set(fdata->rxadptr_service_id, 1); 485 rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id, 0); 486 487 ret = rte_event_eth_tx_adapter_service_id_get(cdata.tx_adapter_id, 488 &fdata->txadptr_service_id); 489 if (ret != -ESRCH && ret != 0) { 490 rte_exit(EXIT_FAILURE, 491 "Error getting the service ID for Tx adapter\n"); 492 } 493 rte_service_runstate_set(fdata->txadptr_service_id, 1); 494 rte_service_set_runstate_mapped_check(fdata->txadptr_service_id, 0); 495 496 ret = rte_event_eth_rx_adapter_start(cdata.rx_adapter_id); 497 if (ret) 498 rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed", 499 cdata.rx_adapter_id); 500 501 ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id); 502 if (ret) 503 rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed", 504 cdata.tx_adapter_id); 505 506 if (rte_event_dev_start(evdev_id) < 0) 507 rte_exit(EXIT_FAILURE, "Error starting eventdev"); 508 } 509 510 static void 511 generic_opt_check(void) 512 { 513 int i; 514 int ret; 515 uint32_t cap = 0; 516 uint8_t rx_needed = 0; 517 uint8_t sched_needed = 0; 518 struct rte_event_dev_info eventdev_info; 519 520 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 521 rte_event_dev_info_get(0, &eventdev_info); 522 523 if (cdata.all_type_queues && !(eventdev_info.event_dev_cap & 524 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)) 525 rte_exit(EXIT_FAILURE, 526 "Event dev doesn't support all type queues\n"); 527 sched_needed = !(eventdev_info.event_dev_cap & 528 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED); 529 530 RTE_ETH_FOREACH_DEV(i) { 531 ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap); 532 if (ret) 533 rte_exit(EXIT_FAILURE, 534 "failed to get event rx adapter capabilities"); 535 rx_needed |= 536 !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT); 537 } 538 539 if (cdata.worker_lcore_mask == 0 || 540 (rx_needed && cdata.rx_lcore_mask == 0) || 541 (cdata.tx_lcore_mask == 0) || 542 (sched_needed && cdata.sched_lcore_mask == 0)) { 543 printf("Core part of pipeline was not assigned any cores. " 544 "This will stall the pipeline, please check core masks " 545 "(use -h for details on setting core masks):\n" 546 "\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64 547 "\n\tworkers: %"PRIu64"\n", 548 cdata.rx_lcore_mask, cdata.tx_lcore_mask, 549 cdata.sched_lcore_mask, 550 cdata.worker_lcore_mask); 551 rte_exit(-1, "Fix core masks\n"); 552 } 553 554 if (!sched_needed) 555 memset(fdata->sched_core, 0, 556 sizeof(unsigned int) * MAX_NUM_CORE); 557 if (!rx_needed) 558 memset(fdata->rx_core, 0, 559 sizeof(unsigned int) * MAX_NUM_CORE); 560 } 561 562 void 563 set_worker_generic_setup_data(struct setup_data *caps, bool burst) 564 { 565 if (burst) { 566 caps->worker = worker_generic_burst; 567 } else { 568 caps->worker = worker_generic; 569 } 570 571 caps->adptr_setup = init_adapters; 572 caps->scheduler = schedule_devices; 573 caps->evdev_setup = setup_eventdev_generic; 574 caps->check_opt = generic_opt_check; 575 } 576