16d239dd5SPavan Nikhilesh /* 26d239dd5SPavan Nikhilesh * SPDX-License-Identifier: BSD-3-Clause 36d239dd5SPavan Nikhilesh * Copyright 2016 Intel Corporation. 46d239dd5SPavan Nikhilesh * Copyright 2017 Cavium, Inc. 56d239dd5SPavan Nikhilesh */ 66d239dd5SPavan Nikhilesh 76d239dd5SPavan Nikhilesh #include "pipeline_common.h" 86d239dd5SPavan Nikhilesh 96d239dd5SPavan Nikhilesh static __rte_always_inline int 106d239dd5SPavan Nikhilesh worker_generic(void *arg) 116d239dd5SPavan Nikhilesh { 126d239dd5SPavan Nikhilesh struct rte_event ev; 136d239dd5SPavan Nikhilesh 146d239dd5SPavan Nikhilesh struct worker_data *data = (struct worker_data *)arg; 156d239dd5SPavan Nikhilesh uint8_t dev_id = data->dev_id; 166d239dd5SPavan Nikhilesh uint8_t port_id = data->port_id; 176d239dd5SPavan Nikhilesh size_t sent = 0, received = 0; 186d239dd5SPavan Nikhilesh unsigned int lcore_id = rte_lcore_id(); 196d239dd5SPavan Nikhilesh 206d239dd5SPavan Nikhilesh while (!fdata->done) { 216d239dd5SPavan Nikhilesh 226d239dd5SPavan Nikhilesh if (fdata->cap.scheduler) 236d239dd5SPavan Nikhilesh fdata->cap.scheduler(lcore_id); 246d239dd5SPavan Nikhilesh 256d239dd5SPavan Nikhilesh if (!fdata->worker_core[lcore_id]) { 266d239dd5SPavan Nikhilesh rte_pause(); 276d239dd5SPavan Nikhilesh continue; 286d239dd5SPavan Nikhilesh } 296d239dd5SPavan Nikhilesh 306d239dd5SPavan Nikhilesh const uint16_t nb_rx = rte_event_dequeue_burst(dev_id, port_id, 316d239dd5SPavan Nikhilesh &ev, 1, 0); 326d239dd5SPavan Nikhilesh 336d239dd5SPavan Nikhilesh if (nb_rx == 0) { 346d239dd5SPavan Nikhilesh rte_pause(); 356d239dd5SPavan Nikhilesh continue; 366d239dd5SPavan Nikhilesh } 376d239dd5SPavan Nikhilesh received++; 386d239dd5SPavan Nikhilesh 396d239dd5SPavan Nikhilesh /* The first worker stage does classification */ 406d239dd5SPavan Nikhilesh if (ev.queue_id == cdata.qid[0]) 416d239dd5SPavan Nikhilesh ev.flow_id = ev.mbuf->hash.rss 426d239dd5SPavan Nikhilesh % cdata.num_fids; 436d239dd5SPavan Nikhilesh 446d239dd5SPavan Nikhilesh ev.queue_id = cdata.next_qid[ev.queue_id]; 456d239dd5SPavan Nikhilesh ev.op = RTE_EVENT_OP_FORWARD; 466d239dd5SPavan Nikhilesh ev.sched_type = cdata.queue_type; 476d239dd5SPavan Nikhilesh 486d239dd5SPavan Nikhilesh work(); 496d239dd5SPavan Nikhilesh 506d239dd5SPavan Nikhilesh while (rte_event_enqueue_burst(dev_id, port_id, &ev, 1) != 1) 516d239dd5SPavan Nikhilesh rte_pause(); 526d239dd5SPavan Nikhilesh sent++; 536d239dd5SPavan Nikhilesh } 546d239dd5SPavan Nikhilesh 556d239dd5SPavan Nikhilesh if (!cdata.quiet) 566d239dd5SPavan Nikhilesh printf(" worker %u thread done. RX=%zu TX=%zu\n", 576d239dd5SPavan Nikhilesh rte_lcore_id(), received, sent); 586d239dd5SPavan Nikhilesh 596d239dd5SPavan Nikhilesh return 0; 606d239dd5SPavan Nikhilesh } 616d239dd5SPavan Nikhilesh 626d239dd5SPavan Nikhilesh static int 636d239dd5SPavan Nikhilesh worker_generic_burst(void *arg) 646d239dd5SPavan Nikhilesh { 656d239dd5SPavan Nikhilesh struct rte_event events[BATCH_SIZE]; 666d239dd5SPavan Nikhilesh 676d239dd5SPavan Nikhilesh struct worker_data *data = (struct worker_data *)arg; 686d239dd5SPavan Nikhilesh uint8_t dev_id = data->dev_id; 696d239dd5SPavan Nikhilesh uint8_t port_id = data->port_id; 706d239dd5SPavan Nikhilesh size_t sent = 0, received = 0; 716d239dd5SPavan Nikhilesh unsigned int lcore_id = rte_lcore_id(); 726d239dd5SPavan Nikhilesh 736d239dd5SPavan Nikhilesh while (!fdata->done) { 746d239dd5SPavan Nikhilesh uint16_t i; 756d239dd5SPavan Nikhilesh 766d239dd5SPavan Nikhilesh if (fdata->cap.scheduler) 776d239dd5SPavan Nikhilesh fdata->cap.scheduler(lcore_id); 786d239dd5SPavan Nikhilesh 796d239dd5SPavan Nikhilesh if (!fdata->worker_core[lcore_id]) { 806d239dd5SPavan Nikhilesh rte_pause(); 816d239dd5SPavan Nikhilesh continue; 826d239dd5SPavan Nikhilesh } 836d239dd5SPavan Nikhilesh 846d239dd5SPavan Nikhilesh const uint16_t nb_rx = rte_event_dequeue_burst(dev_id, port_id, 856d239dd5SPavan Nikhilesh events, RTE_DIM(events), 0); 866d239dd5SPavan Nikhilesh 876d239dd5SPavan Nikhilesh if (nb_rx == 0) { 886d239dd5SPavan Nikhilesh rte_pause(); 896d239dd5SPavan Nikhilesh continue; 906d239dd5SPavan Nikhilesh } 916d239dd5SPavan Nikhilesh received += nb_rx; 926d239dd5SPavan Nikhilesh 936d239dd5SPavan Nikhilesh for (i = 0; i < nb_rx; i++) { 946d239dd5SPavan Nikhilesh 956d239dd5SPavan Nikhilesh /* The first worker stage does classification */ 966d239dd5SPavan Nikhilesh if (events[i].queue_id == cdata.qid[0]) 976d239dd5SPavan Nikhilesh events[i].flow_id = events[i].mbuf->hash.rss 986d239dd5SPavan Nikhilesh % cdata.num_fids; 996d239dd5SPavan Nikhilesh 1006d239dd5SPavan Nikhilesh events[i].queue_id = cdata.next_qid[events[i].queue_id]; 1016d239dd5SPavan Nikhilesh events[i].op = RTE_EVENT_OP_FORWARD; 1026d239dd5SPavan Nikhilesh events[i].sched_type = cdata.queue_type; 1036d239dd5SPavan Nikhilesh 1046d239dd5SPavan Nikhilesh work(); 1056d239dd5SPavan Nikhilesh } 1066d239dd5SPavan Nikhilesh uint16_t nb_tx = rte_event_enqueue_burst(dev_id, port_id, 1076d239dd5SPavan Nikhilesh events, nb_rx); 1086d239dd5SPavan Nikhilesh while (nb_tx < nb_rx && !fdata->done) 1096d239dd5SPavan Nikhilesh nb_tx += rte_event_enqueue_burst(dev_id, port_id, 1106d239dd5SPavan Nikhilesh events + nb_tx, 1116d239dd5SPavan Nikhilesh nb_rx - nb_tx); 1126d239dd5SPavan Nikhilesh sent += nb_tx; 1136d239dd5SPavan Nikhilesh } 1146d239dd5SPavan Nikhilesh 1156d239dd5SPavan Nikhilesh if (!cdata.quiet) 1166d239dd5SPavan Nikhilesh printf(" worker %u thread done. RX=%zu TX=%zu\n", 1176d239dd5SPavan Nikhilesh rte_lcore_id(), received, sent); 1186d239dd5SPavan Nikhilesh 1196d239dd5SPavan Nikhilesh return 0; 1206d239dd5SPavan Nikhilesh } 1216d239dd5SPavan Nikhilesh 1226d239dd5SPavan Nikhilesh static int 123085edac2SPavan Nikhilesh setup_eventdev_generic(struct worker_data *worker_data) 1246d239dd5SPavan Nikhilesh { 1256d239dd5SPavan Nikhilesh const uint8_t dev_id = 0; 1266d239dd5SPavan Nikhilesh /* +1 stages is for a SINGLE_LINK TX stage */ 1276d239dd5SPavan Nikhilesh const uint8_t nb_queues = cdata.num_stages + 1; 128085edac2SPavan Nikhilesh const uint8_t nb_ports = cdata.num_workers; 1296d239dd5SPavan Nikhilesh struct rte_event_dev_config config = { 1306d239dd5SPavan Nikhilesh .nb_event_queues = nb_queues, 1316d239dd5SPavan Nikhilesh .nb_event_ports = nb_ports, 1326d239dd5SPavan Nikhilesh .nb_events_limit = 4096, 1336d239dd5SPavan Nikhilesh .nb_event_queue_flows = 1024, 1346d239dd5SPavan Nikhilesh .nb_event_port_dequeue_depth = 128, 1356d239dd5SPavan Nikhilesh .nb_event_port_enqueue_depth = 128, 1366d239dd5SPavan Nikhilesh }; 1376d239dd5SPavan Nikhilesh struct rte_event_port_conf wkr_p_conf = { 1386d239dd5SPavan Nikhilesh .dequeue_depth = cdata.worker_cq_depth, 1396d239dd5SPavan Nikhilesh .enqueue_depth = 64, 1406d239dd5SPavan Nikhilesh .new_event_threshold = 4096, 1416d239dd5SPavan Nikhilesh }; 1426d239dd5SPavan Nikhilesh struct rte_event_queue_conf wkr_q_conf = { 1436d239dd5SPavan Nikhilesh .schedule_type = cdata.queue_type, 1446d239dd5SPavan Nikhilesh .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 1456d239dd5SPavan Nikhilesh .nb_atomic_flows = 1024, 1466d239dd5SPavan Nikhilesh .nb_atomic_order_sequences = 1024, 1476d239dd5SPavan Nikhilesh }; 1486d239dd5SPavan Nikhilesh struct rte_event_queue_conf tx_q_conf = { 1496d239dd5SPavan Nikhilesh .priority = RTE_EVENT_DEV_PRIORITY_HIGHEST, 1506d239dd5SPavan Nikhilesh .event_queue_cfg = RTE_EVENT_QUEUE_CFG_SINGLE_LINK, 1516d239dd5SPavan Nikhilesh }; 1526d239dd5SPavan Nikhilesh 1536d239dd5SPavan Nikhilesh struct port_link worker_queues[MAX_NUM_STAGES]; 1546d239dd5SPavan Nikhilesh uint8_t disable_implicit_release; 1556d239dd5SPavan Nikhilesh unsigned int i; 1566d239dd5SPavan Nikhilesh 1576d239dd5SPavan Nikhilesh int ret, ndev = rte_event_dev_count(); 1586d239dd5SPavan Nikhilesh if (ndev < 1) { 1596d239dd5SPavan Nikhilesh printf("%d: No Eventdev Devices Found\n", __LINE__); 1606d239dd5SPavan Nikhilesh return -1; 1616d239dd5SPavan Nikhilesh } 1626d239dd5SPavan Nikhilesh 1636d239dd5SPavan Nikhilesh struct rte_event_dev_info dev_info; 1646d239dd5SPavan Nikhilesh ret = rte_event_dev_info_get(dev_id, &dev_info); 1656d239dd5SPavan Nikhilesh printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name); 1666d239dd5SPavan Nikhilesh 1676d239dd5SPavan Nikhilesh disable_implicit_release = (dev_info.event_dev_cap & 1686d239dd5SPavan Nikhilesh RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE); 1696d239dd5SPavan Nikhilesh 1706d239dd5SPavan Nikhilesh wkr_p_conf.disable_implicit_release = disable_implicit_release; 1716d239dd5SPavan Nikhilesh 172*84f4c73fSPavan Nikhilesh if (dev_info.max_num_events < config.nb_events_limit) 173*84f4c73fSPavan Nikhilesh config.nb_events_limit = dev_info.max_num_events; 1746d239dd5SPavan Nikhilesh if (dev_info.max_event_port_dequeue_depth < 1756d239dd5SPavan Nikhilesh config.nb_event_port_dequeue_depth) 1766d239dd5SPavan Nikhilesh config.nb_event_port_dequeue_depth = 1776d239dd5SPavan Nikhilesh dev_info.max_event_port_dequeue_depth; 1786d239dd5SPavan Nikhilesh if (dev_info.max_event_port_enqueue_depth < 1796d239dd5SPavan Nikhilesh config.nb_event_port_enqueue_depth) 1806d239dd5SPavan Nikhilesh config.nb_event_port_enqueue_depth = 1816d239dd5SPavan Nikhilesh dev_info.max_event_port_enqueue_depth; 1826d239dd5SPavan Nikhilesh 1836d239dd5SPavan Nikhilesh ret = rte_event_dev_configure(dev_id, &config); 1846d239dd5SPavan Nikhilesh if (ret < 0) { 1856d239dd5SPavan Nikhilesh printf("%d: Error configuring device\n", __LINE__); 1866d239dd5SPavan Nikhilesh return -1; 1876d239dd5SPavan Nikhilesh } 1886d239dd5SPavan Nikhilesh 1896d239dd5SPavan Nikhilesh /* Q creation - one load balanced per pipeline stage*/ 1906d239dd5SPavan Nikhilesh printf(" Stages:\n"); 1916d239dd5SPavan Nikhilesh for (i = 0; i < cdata.num_stages; i++) { 1926d239dd5SPavan Nikhilesh if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) { 1936d239dd5SPavan Nikhilesh printf("%d: error creating qid %d\n", __LINE__, i); 1946d239dd5SPavan Nikhilesh return -1; 1956d239dd5SPavan Nikhilesh } 1966d239dd5SPavan Nikhilesh cdata.qid[i] = i; 1976d239dd5SPavan Nikhilesh cdata.next_qid[i] = i+1; 1986d239dd5SPavan Nikhilesh worker_queues[i].queue_id = i; 1996d239dd5SPavan Nikhilesh if (cdata.enable_queue_priorities) { 2006d239dd5SPavan Nikhilesh /* calculate priority stepping for each stage, leaving 2016d239dd5SPavan Nikhilesh * headroom of 1 for the SINGLE_LINK TX below 2026d239dd5SPavan Nikhilesh */ 2036d239dd5SPavan Nikhilesh const uint32_t prio_delta = 2046d239dd5SPavan Nikhilesh (RTE_EVENT_DEV_PRIORITY_LOWEST-1) / nb_queues; 2056d239dd5SPavan Nikhilesh 2066d239dd5SPavan Nikhilesh /* higher priority for queues closer to tx */ 2076d239dd5SPavan Nikhilesh wkr_q_conf.priority = 2086d239dd5SPavan Nikhilesh RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i; 2096d239dd5SPavan Nikhilesh } 2106d239dd5SPavan Nikhilesh 2116d239dd5SPavan Nikhilesh const char *type_str = "Atomic"; 2126d239dd5SPavan Nikhilesh switch (wkr_q_conf.schedule_type) { 2136d239dd5SPavan Nikhilesh case RTE_SCHED_TYPE_ORDERED: 2146d239dd5SPavan Nikhilesh type_str = "Ordered"; 2156d239dd5SPavan Nikhilesh break; 2166d239dd5SPavan Nikhilesh case RTE_SCHED_TYPE_PARALLEL: 2176d239dd5SPavan Nikhilesh type_str = "Parallel"; 2186d239dd5SPavan Nikhilesh break; 2196d239dd5SPavan Nikhilesh } 2206d239dd5SPavan Nikhilesh printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str, 2216d239dd5SPavan Nikhilesh wkr_q_conf.priority); 2226d239dd5SPavan Nikhilesh } 2236d239dd5SPavan Nikhilesh printf("\n"); 2246d239dd5SPavan Nikhilesh 2256d239dd5SPavan Nikhilesh /* final queue for sending to TX core */ 2266d239dd5SPavan Nikhilesh if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) { 2276d239dd5SPavan Nikhilesh printf("%d: error creating qid %d\n", __LINE__, i); 2286d239dd5SPavan Nikhilesh return -1; 2296d239dd5SPavan Nikhilesh } 230085edac2SPavan Nikhilesh cdata.tx_queue_id = i; 2316d239dd5SPavan Nikhilesh 232*84f4c73fSPavan Nikhilesh if (wkr_p_conf.new_event_threshold > config.nb_events_limit) 233*84f4c73fSPavan Nikhilesh wkr_p_conf.new_event_threshold = config.nb_events_limit; 2346d239dd5SPavan Nikhilesh if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth) 2356d239dd5SPavan Nikhilesh wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth; 2366d239dd5SPavan Nikhilesh if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth) 2376d239dd5SPavan Nikhilesh wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth; 2386d239dd5SPavan Nikhilesh 2396d239dd5SPavan Nikhilesh /* set up one port per worker, linking to all stage queues */ 2406d239dd5SPavan Nikhilesh for (i = 0; i < cdata.num_workers; i++) { 2416d239dd5SPavan Nikhilesh struct worker_data *w = &worker_data[i]; 2426d239dd5SPavan Nikhilesh w->dev_id = dev_id; 2436d239dd5SPavan Nikhilesh if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) { 2446d239dd5SPavan Nikhilesh printf("Error setting up port %d\n", i); 2456d239dd5SPavan Nikhilesh return -1; 2466d239dd5SPavan Nikhilesh } 2476d239dd5SPavan Nikhilesh 2486d239dd5SPavan Nikhilesh uint32_t s; 2496d239dd5SPavan Nikhilesh for (s = 0; s < cdata.num_stages; s++) { 2506d239dd5SPavan Nikhilesh if (rte_event_port_link(dev_id, i, 2516d239dd5SPavan Nikhilesh &worker_queues[s].queue_id, 2526d239dd5SPavan Nikhilesh &worker_queues[s].priority, 2536d239dd5SPavan Nikhilesh 1) != 1) { 2546d239dd5SPavan Nikhilesh printf("%d: error creating link for port %d\n", 2556d239dd5SPavan Nikhilesh __LINE__, i); 2566d239dd5SPavan Nikhilesh return -1; 2576d239dd5SPavan Nikhilesh } 2586d239dd5SPavan Nikhilesh } 2596d239dd5SPavan Nikhilesh w->port_id = i; 2606d239dd5SPavan Nikhilesh } 2616d239dd5SPavan Nikhilesh 2626d239dd5SPavan Nikhilesh ret = rte_event_dev_service_id_get(dev_id, 2636d239dd5SPavan Nikhilesh &fdata->evdev_service_id); 2646d239dd5SPavan Nikhilesh if (ret != -ESRCH && ret != 0) { 2656d239dd5SPavan Nikhilesh printf("Error getting the service ID for sw eventdev\n"); 2666d239dd5SPavan Nikhilesh return -1; 2676d239dd5SPavan Nikhilesh } 2686d239dd5SPavan Nikhilesh rte_service_runstate_set(fdata->evdev_service_id, 1); 2696d239dd5SPavan Nikhilesh rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0); 2706d239dd5SPavan Nikhilesh 2716d239dd5SPavan Nikhilesh return dev_id; 2726d239dd5SPavan Nikhilesh } 2736d239dd5SPavan Nikhilesh 2746d239dd5SPavan Nikhilesh static void 275085edac2SPavan Nikhilesh init_adapters(uint16_t nb_ports) 2766d239dd5SPavan Nikhilesh { 2776d239dd5SPavan Nikhilesh int i; 2786d239dd5SPavan Nikhilesh int ret; 279085edac2SPavan Nikhilesh uint8_t tx_port_id = 0; 2806d239dd5SPavan Nikhilesh uint8_t evdev_id = 0; 2816d239dd5SPavan Nikhilesh struct rte_event_dev_info dev_info; 2826d239dd5SPavan Nikhilesh 2836d239dd5SPavan Nikhilesh ret = rte_event_dev_info_get(evdev_id, &dev_info); 2846d239dd5SPavan Nikhilesh 285085edac2SPavan Nikhilesh struct rte_event_port_conf adptr_p_conf = { 286085edac2SPavan Nikhilesh .dequeue_depth = cdata.worker_cq_depth, 287085edac2SPavan Nikhilesh .enqueue_depth = 64, 288085edac2SPavan Nikhilesh .new_event_threshold = 4096, 2896d239dd5SPavan Nikhilesh }; 2906d239dd5SPavan Nikhilesh 291*84f4c73fSPavan Nikhilesh if (adptr_p_conf.new_event_threshold > dev_info.max_num_events) 292*84f4c73fSPavan Nikhilesh adptr_p_conf.new_event_threshold = dev_info.max_num_events; 293085edac2SPavan Nikhilesh if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth) 294085edac2SPavan Nikhilesh adptr_p_conf.dequeue_depth = 295085edac2SPavan Nikhilesh dev_info.max_event_port_dequeue_depth; 296085edac2SPavan Nikhilesh if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth) 297085edac2SPavan Nikhilesh adptr_p_conf.enqueue_depth = 298085edac2SPavan Nikhilesh dev_info.max_event_port_enqueue_depth; 2996d239dd5SPavan Nikhilesh 3006d239dd5SPavan Nikhilesh /* Create one adapter for all the ethernet ports. */ 3016d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_create(cdata.rx_adapter_id, evdev_id, 302085edac2SPavan Nikhilesh &adptr_p_conf); 3036d239dd5SPavan Nikhilesh if (ret) 3046d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, "failed to create rx adapter[%d]", 3056d239dd5SPavan Nikhilesh cdata.rx_adapter_id); 3066d239dd5SPavan Nikhilesh 307085edac2SPavan Nikhilesh ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id, 308085edac2SPavan Nikhilesh &adptr_p_conf); 309085edac2SPavan Nikhilesh if (ret) 310085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]", 311085edac2SPavan Nikhilesh cdata.tx_adapter_id); 312085edac2SPavan Nikhilesh 31378548220SThomas Monjalon struct rte_event_eth_rx_adapter_queue_conf queue_conf; 31478548220SThomas Monjalon memset(&queue_conf, 0, sizeof(queue_conf)); 31578548220SThomas Monjalon queue_conf.ev.sched_type = cdata.queue_type; 31678548220SThomas Monjalon queue_conf.ev.queue_id = cdata.qid[0]; 3176d239dd5SPavan Nikhilesh 3186d239dd5SPavan Nikhilesh for (i = 0; i < nb_ports; i++) { 3196d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_queue_add(cdata.rx_adapter_id, i, 3206d239dd5SPavan Nikhilesh -1, &queue_conf); 3216d239dd5SPavan Nikhilesh if (ret) 3226d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 3236d239dd5SPavan Nikhilesh "Failed to add queues to Rx adapter"); 324085edac2SPavan Nikhilesh 325085edac2SPavan Nikhilesh ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i, 326085edac2SPavan Nikhilesh -1); 327085edac2SPavan Nikhilesh if (ret) 328085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, 329085edac2SPavan Nikhilesh "Failed to add queues to Tx adapter"); 3306d239dd5SPavan Nikhilesh } 3316d239dd5SPavan Nikhilesh 332085edac2SPavan Nikhilesh ret = rte_event_eth_tx_adapter_event_port_get(cdata.tx_adapter_id, 333085edac2SPavan Nikhilesh &tx_port_id); 334085edac2SPavan Nikhilesh if (ret) 335085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, 336085edac2SPavan Nikhilesh "Failed to get Tx adapter port id"); 337085edac2SPavan Nikhilesh ret = rte_event_port_link(evdev_id, tx_port_id, &cdata.tx_queue_id, 338085edac2SPavan Nikhilesh NULL, 1); 339085edac2SPavan Nikhilesh if (ret != 1) 340085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, 341085edac2SPavan Nikhilesh "Unable to link Tx adapter port to Tx queue"); 342085edac2SPavan Nikhilesh 3436d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_service_id_get(cdata.rx_adapter_id, 3446d239dd5SPavan Nikhilesh &fdata->rxadptr_service_id); 3456d239dd5SPavan Nikhilesh if (ret != -ESRCH && ret != 0) { 3466d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 347085edac2SPavan Nikhilesh "Error getting the service ID for Rx adapter\n"); 3486d239dd5SPavan Nikhilesh } 3496d239dd5SPavan Nikhilesh rte_service_runstate_set(fdata->rxadptr_service_id, 1); 3506d239dd5SPavan Nikhilesh rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id, 0); 3516d239dd5SPavan Nikhilesh 352085edac2SPavan Nikhilesh ret = rte_event_eth_tx_adapter_service_id_get(cdata.tx_adapter_id, 353085edac2SPavan Nikhilesh &fdata->txadptr_service_id); 354085edac2SPavan Nikhilesh if (ret != -ESRCH && ret != 0) { 355085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, 356085edac2SPavan Nikhilesh "Error getting the service ID for Tx adapter\n"); 357085edac2SPavan Nikhilesh } 358085edac2SPavan Nikhilesh rte_service_runstate_set(fdata->txadptr_service_id, 1); 359085edac2SPavan Nikhilesh rte_service_set_runstate_mapped_check(fdata->txadptr_service_id, 0); 360085edac2SPavan Nikhilesh 3616d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_start(cdata.rx_adapter_id); 3626d239dd5SPavan Nikhilesh if (ret) 3636d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed", 3646d239dd5SPavan Nikhilesh cdata.rx_adapter_id); 365085edac2SPavan Nikhilesh 366085edac2SPavan Nikhilesh ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id); 367085edac2SPavan Nikhilesh if (ret) 368085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed", 369085edac2SPavan Nikhilesh cdata.tx_adapter_id); 370085edac2SPavan Nikhilesh 371085edac2SPavan Nikhilesh if (rte_event_dev_start(evdev_id) < 0) 372085edac2SPavan Nikhilesh rte_exit(EXIT_FAILURE, "Error starting eventdev"); 3736d239dd5SPavan Nikhilesh } 3746d239dd5SPavan Nikhilesh 3756d239dd5SPavan Nikhilesh static void 3766d239dd5SPavan Nikhilesh generic_opt_check(void) 3776d239dd5SPavan Nikhilesh { 3786d239dd5SPavan Nikhilesh int i; 3796d239dd5SPavan Nikhilesh int ret; 3806d239dd5SPavan Nikhilesh uint32_t cap = 0; 3816d239dd5SPavan Nikhilesh uint8_t rx_needed = 0; 382085edac2SPavan Nikhilesh uint8_t sched_needed = 0; 3836d239dd5SPavan Nikhilesh struct rte_event_dev_info eventdev_info; 3846d239dd5SPavan Nikhilesh 3856d239dd5SPavan Nikhilesh memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 3866d239dd5SPavan Nikhilesh rte_event_dev_info_get(0, &eventdev_info); 3876d239dd5SPavan Nikhilesh 3886d239dd5SPavan Nikhilesh if (cdata.all_type_queues && !(eventdev_info.event_dev_cap & 3896d239dd5SPavan Nikhilesh RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)) 3906d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 3916d239dd5SPavan Nikhilesh "Event dev doesn't support all type queues\n"); 392085edac2SPavan Nikhilesh sched_needed = !(eventdev_info.event_dev_cap & 393085edac2SPavan Nikhilesh RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED); 3946d239dd5SPavan Nikhilesh 3958728ccf3SThomas Monjalon RTE_ETH_FOREACH_DEV(i) { 3966d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap); 3976d239dd5SPavan Nikhilesh if (ret) 3986d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 3996d239dd5SPavan Nikhilesh "failed to get event rx adapter capabilities"); 4006d239dd5SPavan Nikhilesh rx_needed |= 4016d239dd5SPavan Nikhilesh !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT); 4026d239dd5SPavan Nikhilesh } 4036d239dd5SPavan Nikhilesh 4046d239dd5SPavan Nikhilesh if (cdata.worker_lcore_mask == 0 || 4056d239dd5SPavan Nikhilesh (rx_needed && cdata.rx_lcore_mask == 0) || 406085edac2SPavan Nikhilesh (cdata.tx_lcore_mask == 0) || 407085edac2SPavan Nikhilesh (sched_needed && cdata.sched_lcore_mask == 0)) { 4086d239dd5SPavan Nikhilesh printf("Core part of pipeline was not assigned any cores. " 4096d239dd5SPavan Nikhilesh "This will stall the pipeline, please check core masks " 4106d239dd5SPavan Nikhilesh "(use -h for details on setting core masks):\n" 4116d239dd5SPavan Nikhilesh "\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64 4126d239dd5SPavan Nikhilesh "\n\tworkers: %"PRIu64"\n", 4136d239dd5SPavan Nikhilesh cdata.rx_lcore_mask, cdata.tx_lcore_mask, 4146d239dd5SPavan Nikhilesh cdata.sched_lcore_mask, 4156d239dd5SPavan Nikhilesh cdata.worker_lcore_mask); 4166d239dd5SPavan Nikhilesh rte_exit(-1, "Fix core masks\n"); 4176d239dd5SPavan Nikhilesh } 4186d239dd5SPavan Nikhilesh 419085edac2SPavan Nikhilesh if (!sched_needed) 4206d239dd5SPavan Nikhilesh memset(fdata->sched_core, 0, 4216d239dd5SPavan Nikhilesh sizeof(unsigned int) * MAX_NUM_CORE); 422085edac2SPavan Nikhilesh if (!rx_needed) 423085edac2SPavan Nikhilesh memset(fdata->rx_core, 0, 424085edac2SPavan Nikhilesh sizeof(unsigned int) * MAX_NUM_CORE); 4256d239dd5SPavan Nikhilesh } 4266d239dd5SPavan Nikhilesh 4276d239dd5SPavan Nikhilesh void 4286d239dd5SPavan Nikhilesh set_worker_generic_setup_data(struct setup_data *caps, bool burst) 4296d239dd5SPavan Nikhilesh { 4306d239dd5SPavan Nikhilesh if (burst) { 4316d239dd5SPavan Nikhilesh caps->worker = worker_generic_burst; 4326d239dd5SPavan Nikhilesh } else { 4336d239dd5SPavan Nikhilesh caps->worker = worker_generic; 4346d239dd5SPavan Nikhilesh } 4356d239dd5SPavan Nikhilesh 436085edac2SPavan Nikhilesh caps->adptr_setup = init_adapters; 4376d239dd5SPavan Nikhilesh caps->scheduler = schedule_devices; 4386d239dd5SPavan Nikhilesh caps->evdev_setup = setup_eventdev_generic; 4396d239dd5SPavan Nikhilesh caps->check_opt = generic_opt_check; 4406d239dd5SPavan Nikhilesh } 441