16d239dd5SPavan Nikhilesh /* 26d239dd5SPavan Nikhilesh * SPDX-License-Identifier: BSD-3-Clause 36d239dd5SPavan Nikhilesh * Copyright 2016 Intel Corporation. 46d239dd5SPavan Nikhilesh * Copyright 2017 Cavium, Inc. 56d239dd5SPavan Nikhilesh */ 66d239dd5SPavan Nikhilesh 76d239dd5SPavan Nikhilesh #include "pipeline_common.h" 86d239dd5SPavan Nikhilesh 96d239dd5SPavan Nikhilesh static __rte_always_inline int 106d239dd5SPavan Nikhilesh worker_generic(void *arg) 116d239dd5SPavan Nikhilesh { 126d239dd5SPavan Nikhilesh struct rte_event ev; 136d239dd5SPavan Nikhilesh 146d239dd5SPavan Nikhilesh struct worker_data *data = (struct worker_data *)arg; 156d239dd5SPavan Nikhilesh uint8_t dev_id = data->dev_id; 166d239dd5SPavan Nikhilesh uint8_t port_id = data->port_id; 176d239dd5SPavan Nikhilesh size_t sent = 0, received = 0; 186d239dd5SPavan Nikhilesh unsigned int lcore_id = rte_lcore_id(); 196d239dd5SPavan Nikhilesh 206d239dd5SPavan Nikhilesh while (!fdata->done) { 216d239dd5SPavan Nikhilesh 226d239dd5SPavan Nikhilesh if (fdata->cap.scheduler) 236d239dd5SPavan Nikhilesh fdata->cap.scheduler(lcore_id); 246d239dd5SPavan Nikhilesh 256d239dd5SPavan Nikhilesh if (!fdata->worker_core[lcore_id]) { 266d239dd5SPavan Nikhilesh rte_pause(); 276d239dd5SPavan Nikhilesh continue; 286d239dd5SPavan Nikhilesh } 296d239dd5SPavan Nikhilesh 306d239dd5SPavan Nikhilesh const uint16_t nb_rx = rte_event_dequeue_burst(dev_id, port_id, 316d239dd5SPavan Nikhilesh &ev, 1, 0); 326d239dd5SPavan Nikhilesh 336d239dd5SPavan Nikhilesh if (nb_rx == 0) { 346d239dd5SPavan Nikhilesh rte_pause(); 356d239dd5SPavan Nikhilesh continue; 366d239dd5SPavan Nikhilesh } 376d239dd5SPavan Nikhilesh received++; 386d239dd5SPavan Nikhilesh 396d239dd5SPavan Nikhilesh /* The first worker stage does classification */ 406d239dd5SPavan Nikhilesh if (ev.queue_id == cdata.qid[0]) 416d239dd5SPavan Nikhilesh ev.flow_id = ev.mbuf->hash.rss 426d239dd5SPavan Nikhilesh % cdata.num_fids; 436d239dd5SPavan Nikhilesh 446d239dd5SPavan Nikhilesh ev.queue_id = cdata.next_qid[ev.queue_id]; 456d239dd5SPavan Nikhilesh ev.op = RTE_EVENT_OP_FORWARD; 466d239dd5SPavan Nikhilesh ev.sched_type = cdata.queue_type; 476d239dd5SPavan Nikhilesh 486d239dd5SPavan Nikhilesh work(); 496d239dd5SPavan Nikhilesh 506d239dd5SPavan Nikhilesh while (rte_event_enqueue_burst(dev_id, port_id, &ev, 1) != 1) 516d239dd5SPavan Nikhilesh rte_pause(); 526d239dd5SPavan Nikhilesh sent++; 536d239dd5SPavan Nikhilesh } 546d239dd5SPavan Nikhilesh 556d239dd5SPavan Nikhilesh if (!cdata.quiet) 566d239dd5SPavan Nikhilesh printf(" worker %u thread done. RX=%zu TX=%zu\n", 576d239dd5SPavan Nikhilesh rte_lcore_id(), received, sent); 586d239dd5SPavan Nikhilesh 596d239dd5SPavan Nikhilesh return 0; 606d239dd5SPavan Nikhilesh } 616d239dd5SPavan Nikhilesh 626d239dd5SPavan Nikhilesh static int 636d239dd5SPavan Nikhilesh worker_generic_burst(void *arg) 646d239dd5SPavan Nikhilesh { 656d239dd5SPavan Nikhilesh struct rte_event events[BATCH_SIZE]; 666d239dd5SPavan Nikhilesh 676d239dd5SPavan Nikhilesh struct worker_data *data = (struct worker_data *)arg; 686d239dd5SPavan Nikhilesh uint8_t dev_id = data->dev_id; 696d239dd5SPavan Nikhilesh uint8_t port_id = data->port_id; 706d239dd5SPavan Nikhilesh size_t sent = 0, received = 0; 716d239dd5SPavan Nikhilesh unsigned int lcore_id = rte_lcore_id(); 726d239dd5SPavan Nikhilesh 736d239dd5SPavan Nikhilesh while (!fdata->done) { 746d239dd5SPavan Nikhilesh uint16_t i; 756d239dd5SPavan Nikhilesh 766d239dd5SPavan Nikhilesh if (fdata->cap.scheduler) 776d239dd5SPavan Nikhilesh fdata->cap.scheduler(lcore_id); 786d239dd5SPavan Nikhilesh 796d239dd5SPavan Nikhilesh if (!fdata->worker_core[lcore_id]) { 806d239dd5SPavan Nikhilesh rte_pause(); 816d239dd5SPavan Nikhilesh continue; 826d239dd5SPavan Nikhilesh } 836d239dd5SPavan Nikhilesh 846d239dd5SPavan Nikhilesh const uint16_t nb_rx = rte_event_dequeue_burst(dev_id, port_id, 856d239dd5SPavan Nikhilesh events, RTE_DIM(events), 0); 866d239dd5SPavan Nikhilesh 876d239dd5SPavan Nikhilesh if (nb_rx == 0) { 886d239dd5SPavan Nikhilesh rte_pause(); 896d239dd5SPavan Nikhilesh continue; 906d239dd5SPavan Nikhilesh } 916d239dd5SPavan Nikhilesh received += nb_rx; 926d239dd5SPavan Nikhilesh 936d239dd5SPavan Nikhilesh for (i = 0; i < nb_rx; i++) { 946d239dd5SPavan Nikhilesh 956d239dd5SPavan Nikhilesh /* The first worker stage does classification */ 966d239dd5SPavan Nikhilesh if (events[i].queue_id == cdata.qid[0]) 976d239dd5SPavan Nikhilesh events[i].flow_id = events[i].mbuf->hash.rss 986d239dd5SPavan Nikhilesh % cdata.num_fids; 996d239dd5SPavan Nikhilesh 1006d239dd5SPavan Nikhilesh events[i].queue_id = cdata.next_qid[events[i].queue_id]; 1016d239dd5SPavan Nikhilesh events[i].op = RTE_EVENT_OP_FORWARD; 1026d239dd5SPavan Nikhilesh events[i].sched_type = cdata.queue_type; 1036d239dd5SPavan Nikhilesh 1046d239dd5SPavan Nikhilesh work(); 1056d239dd5SPavan Nikhilesh } 1066d239dd5SPavan Nikhilesh uint16_t nb_tx = rte_event_enqueue_burst(dev_id, port_id, 1076d239dd5SPavan Nikhilesh events, nb_rx); 1086d239dd5SPavan Nikhilesh while (nb_tx < nb_rx && !fdata->done) 1096d239dd5SPavan Nikhilesh nb_tx += rte_event_enqueue_burst(dev_id, port_id, 1106d239dd5SPavan Nikhilesh events + nb_tx, 1116d239dd5SPavan Nikhilesh nb_rx - nb_tx); 1126d239dd5SPavan Nikhilesh sent += nb_tx; 1136d239dd5SPavan Nikhilesh } 1146d239dd5SPavan Nikhilesh 1156d239dd5SPavan Nikhilesh if (!cdata.quiet) 1166d239dd5SPavan Nikhilesh printf(" worker %u thread done. RX=%zu TX=%zu\n", 1176d239dd5SPavan Nikhilesh rte_lcore_id(), received, sent); 1186d239dd5SPavan Nikhilesh 1196d239dd5SPavan Nikhilesh return 0; 1206d239dd5SPavan Nikhilesh } 1216d239dd5SPavan Nikhilesh 1226d239dd5SPavan Nikhilesh static __rte_always_inline int 1236d239dd5SPavan Nikhilesh consumer(void) 1246d239dd5SPavan Nikhilesh { 1256d239dd5SPavan Nikhilesh const uint64_t freq_khz = rte_get_timer_hz() / 1000; 1266d239dd5SPavan Nikhilesh struct rte_event packet; 1276d239dd5SPavan Nikhilesh 1286d239dd5SPavan Nikhilesh static uint64_t received; 1296d239dd5SPavan Nikhilesh static uint64_t last_pkts; 1306d239dd5SPavan Nikhilesh static uint64_t last_time; 1316d239dd5SPavan Nikhilesh static uint64_t start_time; 1326d239dd5SPavan Nikhilesh int i; 1336d239dd5SPavan Nikhilesh uint8_t dev_id = cons_data.dev_id; 1346d239dd5SPavan Nikhilesh uint8_t port_id = cons_data.port_id; 1356d239dd5SPavan Nikhilesh 1366d239dd5SPavan Nikhilesh do { 1376d239dd5SPavan Nikhilesh uint16_t n = rte_event_dequeue_burst(dev_id, port_id, 1386d239dd5SPavan Nikhilesh &packet, 1, 0); 1396d239dd5SPavan Nikhilesh 1406d239dd5SPavan Nikhilesh if (n == 0) { 1416d239dd5SPavan Nikhilesh for (i = 0; i < rte_eth_dev_count(); i++) 1426d239dd5SPavan Nikhilesh rte_eth_tx_buffer_flush(i, 0, fdata->tx_buf[i]); 1436d239dd5SPavan Nikhilesh return 0; 1446d239dd5SPavan Nikhilesh } 1456d239dd5SPavan Nikhilesh if (start_time == 0) 1466d239dd5SPavan Nikhilesh last_time = start_time = rte_get_timer_cycles(); 1476d239dd5SPavan Nikhilesh 1486d239dd5SPavan Nikhilesh received++; 1496d239dd5SPavan Nikhilesh uint8_t outport = packet.mbuf->port; 1506d239dd5SPavan Nikhilesh 1516d239dd5SPavan Nikhilesh exchange_mac(packet.mbuf); 1526d239dd5SPavan Nikhilesh rte_eth_tx_buffer(outport, 0, fdata->tx_buf[outport], 1536d239dd5SPavan Nikhilesh packet.mbuf); 1546d239dd5SPavan Nikhilesh 1556d239dd5SPavan Nikhilesh if (cons_data.release) 1566d239dd5SPavan Nikhilesh rte_event_enqueue_burst(dev_id, port_id, 1576d239dd5SPavan Nikhilesh &packet, n); 1586d239dd5SPavan Nikhilesh 1596d239dd5SPavan Nikhilesh /* Print out mpps every 1<22 packets */ 1606d239dd5SPavan Nikhilesh if (!cdata.quiet && received >= last_pkts + (1<<22)) { 1616d239dd5SPavan Nikhilesh const uint64_t now = rte_get_timer_cycles(); 1626d239dd5SPavan Nikhilesh const uint64_t total_ms = (now - start_time) / freq_khz; 1636d239dd5SPavan Nikhilesh const uint64_t delta_ms = (now - last_time) / freq_khz; 1646d239dd5SPavan Nikhilesh uint64_t delta_pkts = received - last_pkts; 1656d239dd5SPavan Nikhilesh 1666d239dd5SPavan Nikhilesh printf("# %s RX=%"PRIu64", time %"PRIu64 "ms, " 1676d239dd5SPavan Nikhilesh "avg %.3f mpps [current %.3f mpps]\n", 1686d239dd5SPavan Nikhilesh __func__, 1696d239dd5SPavan Nikhilesh received, 1706d239dd5SPavan Nikhilesh total_ms, 1716d239dd5SPavan Nikhilesh received / (total_ms * 1000.0), 1726d239dd5SPavan Nikhilesh delta_pkts / (delta_ms * 1000.0)); 1736d239dd5SPavan Nikhilesh last_pkts = received; 1746d239dd5SPavan Nikhilesh last_time = now; 1756d239dd5SPavan Nikhilesh } 1766d239dd5SPavan Nikhilesh 1776d239dd5SPavan Nikhilesh cdata.num_packets--; 1786d239dd5SPavan Nikhilesh if (cdata.num_packets <= 0) 1796d239dd5SPavan Nikhilesh fdata->done = 1; 1806d239dd5SPavan Nikhilesh /* Be stuck in this loop if single. */ 1816d239dd5SPavan Nikhilesh } while (!fdata->done && fdata->tx_single); 1826d239dd5SPavan Nikhilesh 1836d239dd5SPavan Nikhilesh return 0; 1846d239dd5SPavan Nikhilesh } 1856d239dd5SPavan Nikhilesh 1866d239dd5SPavan Nikhilesh static __rte_always_inline int 1876d239dd5SPavan Nikhilesh consumer_burst(void) 1886d239dd5SPavan Nikhilesh { 1896d239dd5SPavan Nikhilesh const uint64_t freq_khz = rte_get_timer_hz() / 1000; 1906d239dd5SPavan Nikhilesh struct rte_event packets[BATCH_SIZE]; 1916d239dd5SPavan Nikhilesh 1926d239dd5SPavan Nikhilesh static uint64_t received; 1936d239dd5SPavan Nikhilesh static uint64_t last_pkts; 1946d239dd5SPavan Nikhilesh static uint64_t last_time; 1956d239dd5SPavan Nikhilesh static uint64_t start_time; 1966d239dd5SPavan Nikhilesh unsigned int i, j; 1976d239dd5SPavan Nikhilesh uint8_t dev_id = cons_data.dev_id; 1986d239dd5SPavan Nikhilesh uint8_t port_id = cons_data.port_id; 1996d239dd5SPavan Nikhilesh uint16_t nb_ports = rte_eth_dev_count(); 2006d239dd5SPavan Nikhilesh 2016d239dd5SPavan Nikhilesh do { 2026d239dd5SPavan Nikhilesh uint16_t n = rte_event_dequeue_burst(dev_id, port_id, 2036d239dd5SPavan Nikhilesh packets, RTE_DIM(packets), 0); 2046d239dd5SPavan Nikhilesh 2056d239dd5SPavan Nikhilesh if (n == 0) { 2066d239dd5SPavan Nikhilesh for (j = 0; j < nb_ports; j++) 2076d239dd5SPavan Nikhilesh rte_eth_tx_buffer_flush(j, 0, fdata->tx_buf[j]); 2086d239dd5SPavan Nikhilesh return 0; 2096d239dd5SPavan Nikhilesh } 2106d239dd5SPavan Nikhilesh if (start_time == 0) 2116d239dd5SPavan Nikhilesh last_time = start_time = rte_get_timer_cycles(); 2126d239dd5SPavan Nikhilesh 2136d239dd5SPavan Nikhilesh received += n; 2146d239dd5SPavan Nikhilesh for (i = 0; i < n; i++) { 2156d239dd5SPavan Nikhilesh uint8_t outport = packets[i].mbuf->port; 2166d239dd5SPavan Nikhilesh 2176d239dd5SPavan Nikhilesh exchange_mac(packets[i].mbuf); 2186d239dd5SPavan Nikhilesh rte_eth_tx_buffer(outport, 0, fdata->tx_buf[outport], 2196d239dd5SPavan Nikhilesh packets[i].mbuf); 2206d239dd5SPavan Nikhilesh 2216d239dd5SPavan Nikhilesh packets[i].op = RTE_EVENT_OP_RELEASE; 2226d239dd5SPavan Nikhilesh } 2236d239dd5SPavan Nikhilesh 2246d239dd5SPavan Nikhilesh if (cons_data.release) { 2256d239dd5SPavan Nikhilesh uint16_t nb_tx; 2266d239dd5SPavan Nikhilesh 2276d239dd5SPavan Nikhilesh nb_tx = rte_event_enqueue_burst(dev_id, port_id, 2286d239dd5SPavan Nikhilesh packets, n); 2296d239dd5SPavan Nikhilesh while (nb_tx < n) 2306d239dd5SPavan Nikhilesh nb_tx += rte_event_enqueue_burst(dev_id, 2316d239dd5SPavan Nikhilesh port_id, packets + nb_tx, 2326d239dd5SPavan Nikhilesh n - nb_tx); 2336d239dd5SPavan Nikhilesh } 2346d239dd5SPavan Nikhilesh 2356d239dd5SPavan Nikhilesh /* Print out mpps every 1<22 packets */ 2366d239dd5SPavan Nikhilesh if (!cdata.quiet && received >= last_pkts + (1<<22)) { 2376d239dd5SPavan Nikhilesh const uint64_t now = rte_get_timer_cycles(); 2386d239dd5SPavan Nikhilesh const uint64_t total_ms = (now - start_time) / freq_khz; 2396d239dd5SPavan Nikhilesh const uint64_t delta_ms = (now - last_time) / freq_khz; 2406d239dd5SPavan Nikhilesh uint64_t delta_pkts = received - last_pkts; 2416d239dd5SPavan Nikhilesh 2426d239dd5SPavan Nikhilesh printf("# consumer RX=%"PRIu64", time %"PRIu64 "ms, " 2436d239dd5SPavan Nikhilesh "avg %.3f mpps [current %.3f mpps]\n", 2446d239dd5SPavan Nikhilesh received, 2456d239dd5SPavan Nikhilesh total_ms, 2466d239dd5SPavan Nikhilesh received / (total_ms * 1000.0), 2476d239dd5SPavan Nikhilesh delta_pkts / (delta_ms * 1000.0)); 2486d239dd5SPavan Nikhilesh last_pkts = received; 2496d239dd5SPavan Nikhilesh last_time = now; 2506d239dd5SPavan Nikhilesh } 2516d239dd5SPavan Nikhilesh 2526d239dd5SPavan Nikhilesh cdata.num_packets -= n; 2536d239dd5SPavan Nikhilesh if (cdata.num_packets <= 0) 2546d239dd5SPavan Nikhilesh fdata->done = 1; 2556d239dd5SPavan Nikhilesh /* Be stuck in this loop if single. */ 2566d239dd5SPavan Nikhilesh } while (!fdata->done && fdata->tx_single); 2576d239dd5SPavan Nikhilesh 2586d239dd5SPavan Nikhilesh return 0; 2596d239dd5SPavan Nikhilesh } 2606d239dd5SPavan Nikhilesh 2616d239dd5SPavan Nikhilesh static int 2626d239dd5SPavan Nikhilesh setup_eventdev_generic(struct cons_data *cons_data, 2636d239dd5SPavan Nikhilesh struct worker_data *worker_data) 2646d239dd5SPavan Nikhilesh { 2656d239dd5SPavan Nikhilesh const uint8_t dev_id = 0; 2666d239dd5SPavan Nikhilesh /* +1 stages is for a SINGLE_LINK TX stage */ 2676d239dd5SPavan Nikhilesh const uint8_t nb_queues = cdata.num_stages + 1; 2686d239dd5SPavan Nikhilesh /* + 1 is one port for consumer */ 2696d239dd5SPavan Nikhilesh const uint8_t nb_ports = cdata.num_workers + 1; 2706d239dd5SPavan Nikhilesh struct rte_event_dev_config config = { 2716d239dd5SPavan Nikhilesh .nb_event_queues = nb_queues, 2726d239dd5SPavan Nikhilesh .nb_event_ports = nb_ports, 2736d239dd5SPavan Nikhilesh .nb_events_limit = 4096, 2746d239dd5SPavan Nikhilesh .nb_event_queue_flows = 1024, 2756d239dd5SPavan Nikhilesh .nb_event_port_dequeue_depth = 128, 2766d239dd5SPavan Nikhilesh .nb_event_port_enqueue_depth = 128, 2776d239dd5SPavan Nikhilesh }; 2786d239dd5SPavan Nikhilesh struct rte_event_port_conf wkr_p_conf = { 2796d239dd5SPavan Nikhilesh .dequeue_depth = cdata.worker_cq_depth, 2806d239dd5SPavan Nikhilesh .enqueue_depth = 64, 2816d239dd5SPavan Nikhilesh .new_event_threshold = 4096, 2826d239dd5SPavan Nikhilesh }; 2836d239dd5SPavan Nikhilesh struct rte_event_queue_conf wkr_q_conf = { 2846d239dd5SPavan Nikhilesh .schedule_type = cdata.queue_type, 2856d239dd5SPavan Nikhilesh .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 2866d239dd5SPavan Nikhilesh .nb_atomic_flows = 1024, 2876d239dd5SPavan Nikhilesh .nb_atomic_order_sequences = 1024, 2886d239dd5SPavan Nikhilesh }; 2896d239dd5SPavan Nikhilesh struct rte_event_port_conf tx_p_conf = { 2906d239dd5SPavan Nikhilesh .dequeue_depth = 128, 2916d239dd5SPavan Nikhilesh .enqueue_depth = 128, 2926d239dd5SPavan Nikhilesh .new_event_threshold = 4096, 2936d239dd5SPavan Nikhilesh }; 2946d239dd5SPavan Nikhilesh struct rte_event_queue_conf tx_q_conf = { 2956d239dd5SPavan Nikhilesh .priority = RTE_EVENT_DEV_PRIORITY_HIGHEST, 2966d239dd5SPavan Nikhilesh .event_queue_cfg = RTE_EVENT_QUEUE_CFG_SINGLE_LINK, 2976d239dd5SPavan Nikhilesh }; 2986d239dd5SPavan Nikhilesh 2996d239dd5SPavan Nikhilesh struct port_link worker_queues[MAX_NUM_STAGES]; 3006d239dd5SPavan Nikhilesh uint8_t disable_implicit_release; 3016d239dd5SPavan Nikhilesh struct port_link tx_queue; 3026d239dd5SPavan Nikhilesh unsigned int i; 3036d239dd5SPavan Nikhilesh 3046d239dd5SPavan Nikhilesh int ret, ndev = rte_event_dev_count(); 3056d239dd5SPavan Nikhilesh if (ndev < 1) { 3066d239dd5SPavan Nikhilesh printf("%d: No Eventdev Devices Found\n", __LINE__); 3076d239dd5SPavan Nikhilesh return -1; 3086d239dd5SPavan Nikhilesh } 3096d239dd5SPavan Nikhilesh 3106d239dd5SPavan Nikhilesh struct rte_event_dev_info dev_info; 3116d239dd5SPavan Nikhilesh ret = rte_event_dev_info_get(dev_id, &dev_info); 3126d239dd5SPavan Nikhilesh printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name); 3136d239dd5SPavan Nikhilesh 3146d239dd5SPavan Nikhilesh disable_implicit_release = (dev_info.event_dev_cap & 3156d239dd5SPavan Nikhilesh RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE); 3166d239dd5SPavan Nikhilesh 3176d239dd5SPavan Nikhilesh wkr_p_conf.disable_implicit_release = disable_implicit_release; 3186d239dd5SPavan Nikhilesh tx_p_conf.disable_implicit_release = disable_implicit_release; 3196d239dd5SPavan Nikhilesh 3206d239dd5SPavan Nikhilesh if (dev_info.max_event_port_dequeue_depth < 3216d239dd5SPavan Nikhilesh config.nb_event_port_dequeue_depth) 3226d239dd5SPavan Nikhilesh config.nb_event_port_dequeue_depth = 3236d239dd5SPavan Nikhilesh dev_info.max_event_port_dequeue_depth; 3246d239dd5SPavan Nikhilesh if (dev_info.max_event_port_enqueue_depth < 3256d239dd5SPavan Nikhilesh config.nb_event_port_enqueue_depth) 3266d239dd5SPavan Nikhilesh config.nb_event_port_enqueue_depth = 3276d239dd5SPavan Nikhilesh dev_info.max_event_port_enqueue_depth; 3286d239dd5SPavan Nikhilesh 3296d239dd5SPavan Nikhilesh ret = rte_event_dev_configure(dev_id, &config); 3306d239dd5SPavan Nikhilesh if (ret < 0) { 3316d239dd5SPavan Nikhilesh printf("%d: Error configuring device\n", __LINE__); 3326d239dd5SPavan Nikhilesh return -1; 3336d239dd5SPavan Nikhilesh } 3346d239dd5SPavan Nikhilesh 3356d239dd5SPavan Nikhilesh /* Q creation - one load balanced per pipeline stage*/ 3366d239dd5SPavan Nikhilesh printf(" Stages:\n"); 3376d239dd5SPavan Nikhilesh for (i = 0; i < cdata.num_stages; i++) { 3386d239dd5SPavan Nikhilesh if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) { 3396d239dd5SPavan Nikhilesh printf("%d: error creating qid %d\n", __LINE__, i); 3406d239dd5SPavan Nikhilesh return -1; 3416d239dd5SPavan Nikhilesh } 3426d239dd5SPavan Nikhilesh cdata.qid[i] = i; 3436d239dd5SPavan Nikhilesh cdata.next_qid[i] = i+1; 3446d239dd5SPavan Nikhilesh worker_queues[i].queue_id = i; 3456d239dd5SPavan Nikhilesh if (cdata.enable_queue_priorities) { 3466d239dd5SPavan Nikhilesh /* calculate priority stepping for each stage, leaving 3476d239dd5SPavan Nikhilesh * headroom of 1 for the SINGLE_LINK TX below 3486d239dd5SPavan Nikhilesh */ 3496d239dd5SPavan Nikhilesh const uint32_t prio_delta = 3506d239dd5SPavan Nikhilesh (RTE_EVENT_DEV_PRIORITY_LOWEST-1) / nb_queues; 3516d239dd5SPavan Nikhilesh 3526d239dd5SPavan Nikhilesh /* higher priority for queues closer to tx */ 3536d239dd5SPavan Nikhilesh wkr_q_conf.priority = 3546d239dd5SPavan Nikhilesh RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i; 3556d239dd5SPavan Nikhilesh } 3566d239dd5SPavan Nikhilesh 3576d239dd5SPavan Nikhilesh const char *type_str = "Atomic"; 3586d239dd5SPavan Nikhilesh switch (wkr_q_conf.schedule_type) { 3596d239dd5SPavan Nikhilesh case RTE_SCHED_TYPE_ORDERED: 3606d239dd5SPavan Nikhilesh type_str = "Ordered"; 3616d239dd5SPavan Nikhilesh break; 3626d239dd5SPavan Nikhilesh case RTE_SCHED_TYPE_PARALLEL: 3636d239dd5SPavan Nikhilesh type_str = "Parallel"; 3646d239dd5SPavan Nikhilesh break; 3656d239dd5SPavan Nikhilesh } 3666d239dd5SPavan Nikhilesh printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str, 3676d239dd5SPavan Nikhilesh wkr_q_conf.priority); 3686d239dd5SPavan Nikhilesh } 3696d239dd5SPavan Nikhilesh printf("\n"); 3706d239dd5SPavan Nikhilesh 3716d239dd5SPavan Nikhilesh /* final queue for sending to TX core */ 3726d239dd5SPavan Nikhilesh if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) { 3736d239dd5SPavan Nikhilesh printf("%d: error creating qid %d\n", __LINE__, i); 3746d239dd5SPavan Nikhilesh return -1; 3756d239dd5SPavan Nikhilesh } 3766d239dd5SPavan Nikhilesh tx_queue.queue_id = i; 3776d239dd5SPavan Nikhilesh tx_queue.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST; 3786d239dd5SPavan Nikhilesh 3796d239dd5SPavan Nikhilesh if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth) 3806d239dd5SPavan Nikhilesh wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth; 3816d239dd5SPavan Nikhilesh if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth) 3826d239dd5SPavan Nikhilesh wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth; 3836d239dd5SPavan Nikhilesh 3846d239dd5SPavan Nikhilesh /* set up one port per worker, linking to all stage queues */ 3856d239dd5SPavan Nikhilesh for (i = 0; i < cdata.num_workers; i++) { 3866d239dd5SPavan Nikhilesh struct worker_data *w = &worker_data[i]; 3876d239dd5SPavan Nikhilesh w->dev_id = dev_id; 3886d239dd5SPavan Nikhilesh if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) { 3896d239dd5SPavan Nikhilesh printf("Error setting up port %d\n", i); 3906d239dd5SPavan Nikhilesh return -1; 3916d239dd5SPavan Nikhilesh } 3926d239dd5SPavan Nikhilesh 3936d239dd5SPavan Nikhilesh uint32_t s; 3946d239dd5SPavan Nikhilesh for (s = 0; s < cdata.num_stages; s++) { 3956d239dd5SPavan Nikhilesh if (rte_event_port_link(dev_id, i, 3966d239dd5SPavan Nikhilesh &worker_queues[s].queue_id, 3976d239dd5SPavan Nikhilesh &worker_queues[s].priority, 3986d239dd5SPavan Nikhilesh 1) != 1) { 3996d239dd5SPavan Nikhilesh printf("%d: error creating link for port %d\n", 4006d239dd5SPavan Nikhilesh __LINE__, i); 4016d239dd5SPavan Nikhilesh return -1; 4026d239dd5SPavan Nikhilesh } 4036d239dd5SPavan Nikhilesh } 4046d239dd5SPavan Nikhilesh w->port_id = i; 4056d239dd5SPavan Nikhilesh } 4066d239dd5SPavan Nikhilesh 4076d239dd5SPavan Nikhilesh if (tx_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth) 4086d239dd5SPavan Nikhilesh tx_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth; 4096d239dd5SPavan Nikhilesh if (tx_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth) 4106d239dd5SPavan Nikhilesh tx_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth; 4116d239dd5SPavan Nikhilesh 4126d239dd5SPavan Nikhilesh /* port for consumer, linked to TX queue */ 4136d239dd5SPavan Nikhilesh if (rte_event_port_setup(dev_id, i, &tx_p_conf) < 0) { 4146d239dd5SPavan Nikhilesh printf("Error setting up port %d\n", i); 4156d239dd5SPavan Nikhilesh return -1; 4166d239dd5SPavan Nikhilesh } 4176d239dd5SPavan Nikhilesh if (rte_event_port_link(dev_id, i, &tx_queue.queue_id, 4186d239dd5SPavan Nikhilesh &tx_queue.priority, 1) != 1) { 4196d239dd5SPavan Nikhilesh printf("%d: error creating link for port %d\n", 4206d239dd5SPavan Nikhilesh __LINE__, i); 4216d239dd5SPavan Nikhilesh return -1; 4226d239dd5SPavan Nikhilesh } 4236d239dd5SPavan Nikhilesh *cons_data = (struct cons_data){.dev_id = dev_id, 4246d239dd5SPavan Nikhilesh .port_id = i, 4256d239dd5SPavan Nikhilesh .release = disable_implicit_release }; 4266d239dd5SPavan Nikhilesh 4276d239dd5SPavan Nikhilesh ret = rte_event_dev_service_id_get(dev_id, 4286d239dd5SPavan Nikhilesh &fdata->evdev_service_id); 4296d239dd5SPavan Nikhilesh if (ret != -ESRCH && ret != 0) { 4306d239dd5SPavan Nikhilesh printf("Error getting the service ID for sw eventdev\n"); 4316d239dd5SPavan Nikhilesh return -1; 4326d239dd5SPavan Nikhilesh } 4336d239dd5SPavan Nikhilesh rte_service_runstate_set(fdata->evdev_service_id, 1); 4346d239dd5SPavan Nikhilesh rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0); 4356d239dd5SPavan Nikhilesh if (rte_event_dev_start(dev_id) < 0) { 4366d239dd5SPavan Nikhilesh printf("Error starting eventdev\n"); 4376d239dd5SPavan Nikhilesh return -1; 4386d239dd5SPavan Nikhilesh } 4396d239dd5SPavan Nikhilesh 4406d239dd5SPavan Nikhilesh return dev_id; 4416d239dd5SPavan Nikhilesh } 4426d239dd5SPavan Nikhilesh 4436d239dd5SPavan Nikhilesh static void 4446d239dd5SPavan Nikhilesh init_rx_adapter(uint16_t nb_ports) 4456d239dd5SPavan Nikhilesh { 4466d239dd5SPavan Nikhilesh int i; 4476d239dd5SPavan Nikhilesh int ret; 4486d239dd5SPavan Nikhilesh uint8_t evdev_id = 0; 4496d239dd5SPavan Nikhilesh struct rte_event_dev_info dev_info; 4506d239dd5SPavan Nikhilesh 4516d239dd5SPavan Nikhilesh ret = rte_event_dev_info_get(evdev_id, &dev_info); 4526d239dd5SPavan Nikhilesh 4536d239dd5SPavan Nikhilesh struct rte_event_port_conf rx_p_conf = { 4546d239dd5SPavan Nikhilesh .dequeue_depth = 8, 4556d239dd5SPavan Nikhilesh .enqueue_depth = 8, 4566d239dd5SPavan Nikhilesh .new_event_threshold = 1200, 4576d239dd5SPavan Nikhilesh }; 4586d239dd5SPavan Nikhilesh 4596d239dd5SPavan Nikhilesh if (rx_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth) 4606d239dd5SPavan Nikhilesh rx_p_conf.dequeue_depth = dev_info.max_event_port_dequeue_depth; 4616d239dd5SPavan Nikhilesh if (rx_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth) 4626d239dd5SPavan Nikhilesh rx_p_conf.enqueue_depth = dev_info.max_event_port_enqueue_depth; 4636d239dd5SPavan Nikhilesh 4646d239dd5SPavan Nikhilesh /* Create one adapter for all the ethernet ports. */ 4656d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_create(cdata.rx_adapter_id, evdev_id, 4666d239dd5SPavan Nikhilesh &rx_p_conf); 4676d239dd5SPavan Nikhilesh if (ret) 4686d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, "failed to create rx adapter[%d]", 4696d239dd5SPavan Nikhilesh cdata.rx_adapter_id); 4706d239dd5SPavan Nikhilesh 471*78548220SThomas Monjalon struct rte_event_eth_rx_adapter_queue_conf queue_conf; 472*78548220SThomas Monjalon memset(&queue_conf, 0, sizeof(queue_conf)); 473*78548220SThomas Monjalon queue_conf.ev.sched_type = cdata.queue_type; 474*78548220SThomas Monjalon queue_conf.ev.queue_id = cdata.qid[0]; 4756d239dd5SPavan Nikhilesh 4766d239dd5SPavan Nikhilesh for (i = 0; i < nb_ports; i++) { 4776d239dd5SPavan Nikhilesh uint32_t cap; 4786d239dd5SPavan Nikhilesh 4796d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_caps_get(evdev_id, i, &cap); 4806d239dd5SPavan Nikhilesh if (ret) 4816d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 4826d239dd5SPavan Nikhilesh "failed to get event rx adapter " 4836d239dd5SPavan Nikhilesh "capabilities"); 4846d239dd5SPavan Nikhilesh 4856d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_queue_add(cdata.rx_adapter_id, i, 4866d239dd5SPavan Nikhilesh -1, &queue_conf); 4876d239dd5SPavan Nikhilesh if (ret) 4886d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 4896d239dd5SPavan Nikhilesh "Failed to add queues to Rx adapter"); 4906d239dd5SPavan Nikhilesh } 4916d239dd5SPavan Nikhilesh 4926d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_service_id_get(cdata.rx_adapter_id, 4936d239dd5SPavan Nikhilesh &fdata->rxadptr_service_id); 4946d239dd5SPavan Nikhilesh if (ret != -ESRCH && ret != 0) { 4956d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 4966d239dd5SPavan Nikhilesh "Error getting the service ID for sw eventdev\n"); 4976d239dd5SPavan Nikhilesh } 4986d239dd5SPavan Nikhilesh rte_service_runstate_set(fdata->rxadptr_service_id, 1); 4996d239dd5SPavan Nikhilesh rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id, 0); 5006d239dd5SPavan Nikhilesh 5016d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_start(cdata.rx_adapter_id); 5026d239dd5SPavan Nikhilesh if (ret) 5036d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed", 5046d239dd5SPavan Nikhilesh cdata.rx_adapter_id); 5056d239dd5SPavan Nikhilesh } 5066d239dd5SPavan Nikhilesh 5076d239dd5SPavan Nikhilesh static void 5086d239dd5SPavan Nikhilesh generic_opt_check(void) 5096d239dd5SPavan Nikhilesh { 5106d239dd5SPavan Nikhilesh int i; 5116d239dd5SPavan Nikhilesh int ret; 5126d239dd5SPavan Nikhilesh uint32_t cap = 0; 5136d239dd5SPavan Nikhilesh uint8_t rx_needed = 0; 5146d239dd5SPavan Nikhilesh struct rte_event_dev_info eventdev_info; 5156d239dd5SPavan Nikhilesh 5166d239dd5SPavan Nikhilesh memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 5176d239dd5SPavan Nikhilesh rte_event_dev_info_get(0, &eventdev_info); 5186d239dd5SPavan Nikhilesh 5196d239dd5SPavan Nikhilesh if (cdata.all_type_queues && !(eventdev_info.event_dev_cap & 5206d239dd5SPavan Nikhilesh RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)) 5216d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 5226d239dd5SPavan Nikhilesh "Event dev doesn't support all type queues\n"); 5236d239dd5SPavan Nikhilesh 5246d239dd5SPavan Nikhilesh for (i = 0; i < rte_eth_dev_count(); i++) { 5256d239dd5SPavan Nikhilesh ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap); 5266d239dd5SPavan Nikhilesh if (ret) 5276d239dd5SPavan Nikhilesh rte_exit(EXIT_FAILURE, 5286d239dd5SPavan Nikhilesh "failed to get event rx adapter capabilities"); 5296d239dd5SPavan Nikhilesh rx_needed |= 5306d239dd5SPavan Nikhilesh !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT); 5316d239dd5SPavan Nikhilesh } 5326d239dd5SPavan Nikhilesh 5336d239dd5SPavan Nikhilesh if (cdata.worker_lcore_mask == 0 || 5346d239dd5SPavan Nikhilesh (rx_needed && cdata.rx_lcore_mask == 0) || 5356d239dd5SPavan Nikhilesh cdata.tx_lcore_mask == 0 || (cdata.sched_lcore_mask == 0 5366d239dd5SPavan Nikhilesh && !(eventdev_info.event_dev_cap & 5376d239dd5SPavan Nikhilesh RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED))) { 5386d239dd5SPavan Nikhilesh printf("Core part of pipeline was not assigned any cores. " 5396d239dd5SPavan Nikhilesh "This will stall the pipeline, please check core masks " 5406d239dd5SPavan Nikhilesh "(use -h for details on setting core masks):\n" 5416d239dd5SPavan Nikhilesh "\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64 5426d239dd5SPavan Nikhilesh "\n\tworkers: %"PRIu64"\n", 5436d239dd5SPavan Nikhilesh cdata.rx_lcore_mask, cdata.tx_lcore_mask, 5446d239dd5SPavan Nikhilesh cdata.sched_lcore_mask, 5456d239dd5SPavan Nikhilesh cdata.worker_lcore_mask); 5466d239dd5SPavan Nikhilesh rte_exit(-1, "Fix core masks\n"); 5476d239dd5SPavan Nikhilesh } 5486d239dd5SPavan Nikhilesh 5496d239dd5SPavan Nikhilesh if (eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED) 5506d239dd5SPavan Nikhilesh memset(fdata->sched_core, 0, 5516d239dd5SPavan Nikhilesh sizeof(unsigned int) * MAX_NUM_CORE); 5526d239dd5SPavan Nikhilesh } 5536d239dd5SPavan Nikhilesh 5546d239dd5SPavan Nikhilesh void 5556d239dd5SPavan Nikhilesh set_worker_generic_setup_data(struct setup_data *caps, bool burst) 5566d239dd5SPavan Nikhilesh { 5576d239dd5SPavan Nikhilesh if (burst) { 5586d239dd5SPavan Nikhilesh caps->consumer = consumer_burst; 5596d239dd5SPavan Nikhilesh caps->worker = worker_generic_burst; 5606d239dd5SPavan Nikhilesh } else { 5616d239dd5SPavan Nikhilesh caps->consumer = consumer; 5626d239dd5SPavan Nikhilesh caps->worker = worker_generic; 5636d239dd5SPavan Nikhilesh } 5646d239dd5SPavan Nikhilesh 5656d239dd5SPavan Nikhilesh caps->adptr_setup = init_rx_adapter; 5666d239dd5SPavan Nikhilesh caps->scheduler = schedule_devices; 5676d239dd5SPavan Nikhilesh caps->evdev_setup = setup_eventdev_generic; 5686d239dd5SPavan Nikhilesh caps->check_opt = generic_opt_check; 5696d239dd5SPavan Nikhilesh } 570