1*fc0f7dc4SLuca Vizzarro# SPDX-License-Identifier: BSD-3-Clause 2*fc0f7dc4SLuca Vizzarro# Copyright(c) 2024 Arm Limited 3*fc0f7dc4SLuca Vizzarro 4*fc0f7dc4SLuca Vizzarro"""Module containing all the TestPmd-related parameter classes.""" 5*fc0f7dc4SLuca Vizzarro 6*fc0f7dc4SLuca Vizzarrofrom dataclasses import dataclass, field 7*fc0f7dc4SLuca Vizzarrofrom enum import EnumMeta, Flag, auto, unique 8*fc0f7dc4SLuca Vizzarrofrom pathlib import PurePath 9*fc0f7dc4SLuca Vizzarrofrom typing import Literal, NamedTuple 10*fc0f7dc4SLuca Vizzarro 11*fc0f7dc4SLuca Vizzarrofrom framework.params import ( 12*fc0f7dc4SLuca Vizzarro Params, 13*fc0f7dc4SLuca Vizzarro Switch, 14*fc0f7dc4SLuca Vizzarro YesNoSwitch, 15*fc0f7dc4SLuca Vizzarro bracketed, 16*fc0f7dc4SLuca Vizzarro comma_separated, 17*fc0f7dc4SLuca Vizzarro hex_from_flag_value, 18*fc0f7dc4SLuca Vizzarro modify_str, 19*fc0f7dc4SLuca Vizzarro str_from_flag_value, 20*fc0f7dc4SLuca Vizzarro) 21*fc0f7dc4SLuca Vizzarrofrom framework.params.eal import EalParams 22*fc0f7dc4SLuca Vizzarrofrom framework.utils import StrEnum 23*fc0f7dc4SLuca Vizzarro 24*fc0f7dc4SLuca Vizzarro 25*fc0f7dc4SLuca Vizzarroclass PortTopology(StrEnum): 26*fc0f7dc4SLuca Vizzarro """Enum representing the port topology.""" 27*fc0f7dc4SLuca Vizzarro 28*fc0f7dc4SLuca Vizzarro #: In paired mode, the forwarding is between pairs of ports, e.g.: (0,1), (2,3), (4,5). 29*fc0f7dc4SLuca Vizzarro paired = auto() 30*fc0f7dc4SLuca Vizzarro 31*fc0f7dc4SLuca Vizzarro #: In chained mode, the forwarding is to the next available port in the port mask, e.g.: 32*fc0f7dc4SLuca Vizzarro #: (0,1), (1,2), (2,0). 33*fc0f7dc4SLuca Vizzarro #: 34*fc0f7dc4SLuca Vizzarro #: The ordering of the ports can be changed using the portlist testpmd runtime function. 35*fc0f7dc4SLuca Vizzarro chained = auto() 36*fc0f7dc4SLuca Vizzarro 37*fc0f7dc4SLuca Vizzarro #: In loop mode, ingress traffic is simply transmitted back on the same interface. 38*fc0f7dc4SLuca Vizzarro loop = auto() 39*fc0f7dc4SLuca Vizzarro 40*fc0f7dc4SLuca Vizzarro 41*fc0f7dc4SLuca Vizzarro@modify_str(comma_separated, bracketed) 42*fc0f7dc4SLuca Vizzarroclass PortNUMAConfig(NamedTuple): 43*fc0f7dc4SLuca Vizzarro """DPDK port to NUMA socket association tuple.""" 44*fc0f7dc4SLuca Vizzarro 45*fc0f7dc4SLuca Vizzarro #: 46*fc0f7dc4SLuca Vizzarro port: int 47*fc0f7dc4SLuca Vizzarro #: 48*fc0f7dc4SLuca Vizzarro socket: int 49*fc0f7dc4SLuca Vizzarro 50*fc0f7dc4SLuca Vizzarro 51*fc0f7dc4SLuca Vizzarro@modify_str(str_from_flag_value) 52*fc0f7dc4SLuca Vizzarro@unique 53*fc0f7dc4SLuca Vizzarroclass FlowDirection(Flag): 54*fc0f7dc4SLuca Vizzarro """Flag indicating the direction of the flow. 55*fc0f7dc4SLuca Vizzarro 56*fc0f7dc4SLuca Vizzarro A bi-directional flow can be specified with the pipe: 57*fc0f7dc4SLuca Vizzarro 58*fc0f7dc4SLuca Vizzarro >>> TestPmdFlowDirection.RX | TestPmdFlowDirection.TX 59*fc0f7dc4SLuca Vizzarro <TestPmdFlowDirection.TX|RX: 3> 60*fc0f7dc4SLuca Vizzarro """ 61*fc0f7dc4SLuca Vizzarro 62*fc0f7dc4SLuca Vizzarro #: 63*fc0f7dc4SLuca Vizzarro RX = 1 << 0 64*fc0f7dc4SLuca Vizzarro #: 65*fc0f7dc4SLuca Vizzarro TX = 1 << 1 66*fc0f7dc4SLuca Vizzarro 67*fc0f7dc4SLuca Vizzarro 68*fc0f7dc4SLuca Vizzarro@modify_str(comma_separated, bracketed) 69*fc0f7dc4SLuca Vizzarroclass RingNUMAConfig(NamedTuple): 70*fc0f7dc4SLuca Vizzarro """Tuple associating DPDK port, direction of the flow and NUMA socket.""" 71*fc0f7dc4SLuca Vizzarro 72*fc0f7dc4SLuca Vizzarro #: 73*fc0f7dc4SLuca Vizzarro port: int 74*fc0f7dc4SLuca Vizzarro #: 75*fc0f7dc4SLuca Vizzarro direction: FlowDirection 76*fc0f7dc4SLuca Vizzarro #: 77*fc0f7dc4SLuca Vizzarro socket: int 78*fc0f7dc4SLuca Vizzarro 79*fc0f7dc4SLuca Vizzarro 80*fc0f7dc4SLuca Vizzarro@modify_str(comma_separated) 81*fc0f7dc4SLuca Vizzarroclass EthPeer(NamedTuple): 82*fc0f7dc4SLuca Vizzarro """Tuple associating a MAC address to the specified DPDK port.""" 83*fc0f7dc4SLuca Vizzarro 84*fc0f7dc4SLuca Vizzarro #: 85*fc0f7dc4SLuca Vizzarro port_no: int 86*fc0f7dc4SLuca Vizzarro #: 87*fc0f7dc4SLuca Vizzarro mac_address: str 88*fc0f7dc4SLuca Vizzarro 89*fc0f7dc4SLuca Vizzarro 90*fc0f7dc4SLuca Vizzarro@modify_str(comma_separated) 91*fc0f7dc4SLuca Vizzarroclass TxIPAddrPair(NamedTuple): 92*fc0f7dc4SLuca Vizzarro """Tuple specifying the source and destination IPs for the packets.""" 93*fc0f7dc4SLuca Vizzarro 94*fc0f7dc4SLuca Vizzarro #: 95*fc0f7dc4SLuca Vizzarro source_ip: str 96*fc0f7dc4SLuca Vizzarro #: 97*fc0f7dc4SLuca Vizzarro dest_ip: str 98*fc0f7dc4SLuca Vizzarro 99*fc0f7dc4SLuca Vizzarro 100*fc0f7dc4SLuca Vizzarro@modify_str(comma_separated) 101*fc0f7dc4SLuca Vizzarroclass TxUDPPortPair(NamedTuple): 102*fc0f7dc4SLuca Vizzarro """Tuple specifying the UDP source and destination ports for the packets. 103*fc0f7dc4SLuca Vizzarro 104*fc0f7dc4SLuca Vizzarro If leaving ``dest_port`` unspecified, ``source_port`` will be used for 105*fc0f7dc4SLuca Vizzarro the destination port as well. 106*fc0f7dc4SLuca Vizzarro """ 107*fc0f7dc4SLuca Vizzarro 108*fc0f7dc4SLuca Vizzarro #: 109*fc0f7dc4SLuca Vizzarro source_port: int 110*fc0f7dc4SLuca Vizzarro #: 111*fc0f7dc4SLuca Vizzarro dest_port: int | None = None 112*fc0f7dc4SLuca Vizzarro 113*fc0f7dc4SLuca Vizzarro 114*fc0f7dc4SLuca Vizzarro@dataclass 115*fc0f7dc4SLuca Vizzarroclass DisableRSS(Params): 116*fc0f7dc4SLuca Vizzarro """Disables RSS (Receive Side Scaling).""" 117*fc0f7dc4SLuca Vizzarro 118*fc0f7dc4SLuca Vizzarro _disable_rss: Literal[True] = field( 119*fc0f7dc4SLuca Vizzarro default=True, init=False, metadata=Params.long("disable-rss") 120*fc0f7dc4SLuca Vizzarro ) 121*fc0f7dc4SLuca Vizzarro 122*fc0f7dc4SLuca Vizzarro 123*fc0f7dc4SLuca Vizzarro@dataclass 124*fc0f7dc4SLuca Vizzarroclass SetRSSIPOnly(Params): 125*fc0f7dc4SLuca Vizzarro """Sets RSS (Receive Side Scaling) functions for IPv4/IPv6 only.""" 126*fc0f7dc4SLuca Vizzarro 127*fc0f7dc4SLuca Vizzarro _rss_ip: Literal[True] = field(default=True, init=False, metadata=Params.long("rss-ip")) 128*fc0f7dc4SLuca Vizzarro 129*fc0f7dc4SLuca Vizzarro 130*fc0f7dc4SLuca Vizzarro@dataclass 131*fc0f7dc4SLuca Vizzarroclass SetRSSUDP(Params): 132*fc0f7dc4SLuca Vizzarro """Sets RSS (Receive Side Scaling) functions for IPv4/IPv6 and UDP.""" 133*fc0f7dc4SLuca Vizzarro 134*fc0f7dc4SLuca Vizzarro _rss_udp: Literal[True] = field(default=True, init=False, metadata=Params.long("rss-udp")) 135*fc0f7dc4SLuca Vizzarro 136*fc0f7dc4SLuca Vizzarro 137*fc0f7dc4SLuca Vizzarroclass RSSSetting(EnumMeta): 138*fc0f7dc4SLuca Vizzarro """Enum representing a RSS setting. Each property is a class that needs to be initialised.""" 139*fc0f7dc4SLuca Vizzarro 140*fc0f7dc4SLuca Vizzarro #: 141*fc0f7dc4SLuca Vizzarro Disabled = DisableRSS 142*fc0f7dc4SLuca Vizzarro #: 143*fc0f7dc4SLuca Vizzarro SetIPOnly = SetRSSIPOnly 144*fc0f7dc4SLuca Vizzarro #: 145*fc0f7dc4SLuca Vizzarro SetUDP = SetRSSUDP 146*fc0f7dc4SLuca Vizzarro 147*fc0f7dc4SLuca Vizzarro 148*fc0f7dc4SLuca Vizzarroclass SimpleForwardingModes(StrEnum): 149*fc0f7dc4SLuca Vizzarro r"""The supported packet forwarding modes for :class:`~TestPmdShell`\s.""" 150*fc0f7dc4SLuca Vizzarro 151*fc0f7dc4SLuca Vizzarro #: 152*fc0f7dc4SLuca Vizzarro io = auto() 153*fc0f7dc4SLuca Vizzarro #: 154*fc0f7dc4SLuca Vizzarro mac = auto() 155*fc0f7dc4SLuca Vizzarro #: 156*fc0f7dc4SLuca Vizzarro macswap = auto() 157*fc0f7dc4SLuca Vizzarro #: 158*fc0f7dc4SLuca Vizzarro rxonly = auto() 159*fc0f7dc4SLuca Vizzarro #: 160*fc0f7dc4SLuca Vizzarro csum = auto() 161*fc0f7dc4SLuca Vizzarro #: 162*fc0f7dc4SLuca Vizzarro icmpecho = auto() 163*fc0f7dc4SLuca Vizzarro #: 164*fc0f7dc4SLuca Vizzarro ieee1588 = auto() 165*fc0f7dc4SLuca Vizzarro #: 166*fc0f7dc4SLuca Vizzarro fivetswap = "5tswap" 167*fc0f7dc4SLuca Vizzarro #: 168*fc0f7dc4SLuca Vizzarro shared_rxq = "shared-rxq" 169*fc0f7dc4SLuca Vizzarro #: 170*fc0f7dc4SLuca Vizzarro recycle_mbufs = auto() 171*fc0f7dc4SLuca Vizzarro 172*fc0f7dc4SLuca Vizzarro 173*fc0f7dc4SLuca Vizzarro@dataclass(kw_only=True) 174*fc0f7dc4SLuca Vizzarroclass TXOnlyForwardingMode(Params): 175*fc0f7dc4SLuca Vizzarro """Sets a TX-Only forwarding mode. 176*fc0f7dc4SLuca Vizzarro 177*fc0f7dc4SLuca Vizzarro Attributes: 178*fc0f7dc4SLuca Vizzarro multi_flow: Generates multiple flows if set to True. 179*fc0f7dc4SLuca Vizzarro segments_length: Sets TX segment sizes or total packet length. 180*fc0f7dc4SLuca Vizzarro """ 181*fc0f7dc4SLuca Vizzarro 182*fc0f7dc4SLuca Vizzarro _forward_mode: Literal["txonly"] = field( 183*fc0f7dc4SLuca Vizzarro default="txonly", init=False, metadata=Params.long("forward-mode") 184*fc0f7dc4SLuca Vizzarro ) 185*fc0f7dc4SLuca Vizzarro multi_flow: Switch = field(default=None, metadata=Params.long("txonly-multi-flow")) 186*fc0f7dc4SLuca Vizzarro segments_length: list[int] | None = field( 187*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("txpkts") | Params.convert_value(comma_separated) 188*fc0f7dc4SLuca Vizzarro ) 189*fc0f7dc4SLuca Vizzarro 190*fc0f7dc4SLuca Vizzarro 191*fc0f7dc4SLuca Vizzarro@dataclass(kw_only=True) 192*fc0f7dc4SLuca Vizzarroclass FlowGenForwardingMode(Params): 193*fc0f7dc4SLuca Vizzarro """Sets a flowgen forwarding mode. 194*fc0f7dc4SLuca Vizzarro 195*fc0f7dc4SLuca Vizzarro Attributes: 196*fc0f7dc4SLuca Vizzarro clones: Set the number of each packet clones to be sent. Sending clones reduces host CPU 197*fc0f7dc4SLuca Vizzarro load on creating packets and may help in testing extreme speeds or maxing out 198*fc0f7dc4SLuca Vizzarro Tx packet performance. N should be not zero, but less than ‘burst’ parameter. 199*fc0f7dc4SLuca Vizzarro flows: Set the number of flows to be generated, where 1 <= N <= INT32_MAX. 200*fc0f7dc4SLuca Vizzarro segments_length: Set TX segment sizes or total packet length. 201*fc0f7dc4SLuca Vizzarro """ 202*fc0f7dc4SLuca Vizzarro 203*fc0f7dc4SLuca Vizzarro _forward_mode: Literal["flowgen"] = field( 204*fc0f7dc4SLuca Vizzarro default="flowgen", init=False, metadata=Params.long("forward-mode") 205*fc0f7dc4SLuca Vizzarro ) 206*fc0f7dc4SLuca Vizzarro clones: int | None = field(default=None, metadata=Params.long("flowgen-clones")) 207*fc0f7dc4SLuca Vizzarro flows: int | None = field(default=None, metadata=Params.long("flowgen-flows")) 208*fc0f7dc4SLuca Vizzarro segments_length: list[int] | None = field( 209*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("txpkts") | Params.convert_value(comma_separated) 210*fc0f7dc4SLuca Vizzarro ) 211*fc0f7dc4SLuca Vizzarro 212*fc0f7dc4SLuca Vizzarro 213*fc0f7dc4SLuca Vizzarro@dataclass(kw_only=True) 214*fc0f7dc4SLuca Vizzarroclass NoisyForwardingMode(Params): 215*fc0f7dc4SLuca Vizzarro """Sets a noisy forwarding mode. 216*fc0f7dc4SLuca Vizzarro 217*fc0f7dc4SLuca Vizzarro Attributes: 218*fc0f7dc4SLuca Vizzarro forward_mode: Set the noisy VNF forwarding mode. 219*fc0f7dc4SLuca Vizzarro tx_sw_buffer_size: Set the maximum number of elements of the FIFO queue to be created for 220*fc0f7dc4SLuca Vizzarro buffering packets. 221*fc0f7dc4SLuca Vizzarro tx_sw_buffer_flushtime: Set the time before packets in the FIFO queue are flushed. 222*fc0f7dc4SLuca Vizzarro lkup_memory: Set the size of the noisy neighbor simulation memory buffer in MB to N. 223*fc0f7dc4SLuca Vizzarro lkup_num_reads: Set the size of the noisy neighbor simulation memory buffer in MB to N. 224*fc0f7dc4SLuca Vizzarro lkup_num_writes: Set the number of writes to be done in noisy neighbor simulation 225*fc0f7dc4SLuca Vizzarro memory buffer to N. 226*fc0f7dc4SLuca Vizzarro lkup_num_reads_writes: Set the number of r/w accesses to be done in noisy neighbor 227*fc0f7dc4SLuca Vizzarro simulation memory buffer to N. 228*fc0f7dc4SLuca Vizzarro """ 229*fc0f7dc4SLuca Vizzarro 230*fc0f7dc4SLuca Vizzarro _forward_mode: Literal["noisy"] = field( 231*fc0f7dc4SLuca Vizzarro default="noisy", init=False, metadata=Params.long("forward-mode") 232*fc0f7dc4SLuca Vizzarro ) 233*fc0f7dc4SLuca Vizzarro forward_mode: ( 234*fc0f7dc4SLuca Vizzarro Literal[ 235*fc0f7dc4SLuca Vizzarro SimpleForwardingModes.io, 236*fc0f7dc4SLuca Vizzarro SimpleForwardingModes.mac, 237*fc0f7dc4SLuca Vizzarro SimpleForwardingModes.macswap, 238*fc0f7dc4SLuca Vizzarro SimpleForwardingModes.fivetswap, 239*fc0f7dc4SLuca Vizzarro ] 240*fc0f7dc4SLuca Vizzarro | None 241*fc0f7dc4SLuca Vizzarro ) = field(default=SimpleForwardingModes.io, metadata=Params.long("noisy-forward-mode")) 242*fc0f7dc4SLuca Vizzarro tx_sw_buffer_size: int | None = field( 243*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("noisy-tx-sw-buffer-size") 244*fc0f7dc4SLuca Vizzarro ) 245*fc0f7dc4SLuca Vizzarro tx_sw_buffer_flushtime: int | None = field( 246*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("noisy-tx-sw-buffer-flushtime") 247*fc0f7dc4SLuca Vizzarro ) 248*fc0f7dc4SLuca Vizzarro lkup_memory: int | None = field(default=None, metadata=Params.long("noisy-lkup-memory")) 249*fc0f7dc4SLuca Vizzarro lkup_num_reads: int | None = field(default=None, metadata=Params.long("noisy-lkup-num-reads")) 250*fc0f7dc4SLuca Vizzarro lkup_num_writes: int | None = field(default=None, metadata=Params.long("noisy-lkup-num-writes")) 251*fc0f7dc4SLuca Vizzarro lkup_num_reads_writes: int | None = field( 252*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("noisy-lkup-num-reads-writes") 253*fc0f7dc4SLuca Vizzarro ) 254*fc0f7dc4SLuca Vizzarro 255*fc0f7dc4SLuca Vizzarro 256*fc0f7dc4SLuca Vizzarro@modify_str(hex_from_flag_value) 257*fc0f7dc4SLuca Vizzarro@unique 258*fc0f7dc4SLuca Vizzarroclass HairpinMode(Flag): 259*fc0f7dc4SLuca Vizzarro """Flag representing the hairpin mode.""" 260*fc0f7dc4SLuca Vizzarro 261*fc0f7dc4SLuca Vizzarro #: Two hairpin ports loop. 262*fc0f7dc4SLuca Vizzarro TWO_PORTS_LOOP = 1 << 0 263*fc0f7dc4SLuca Vizzarro #: Two hairpin ports paired. 264*fc0f7dc4SLuca Vizzarro TWO_PORTS_PAIRED = 1 << 1 265*fc0f7dc4SLuca Vizzarro #: Explicit Tx flow rule. 266*fc0f7dc4SLuca Vizzarro EXPLICIT_TX_FLOW = 1 << 4 267*fc0f7dc4SLuca Vizzarro #: Force memory settings of hairpin RX queue. 268*fc0f7dc4SLuca Vizzarro FORCE_RX_QUEUE_MEM_SETTINGS = 1 << 8 269*fc0f7dc4SLuca Vizzarro #: Force memory settings of hairpin TX queue. 270*fc0f7dc4SLuca Vizzarro FORCE_TX_QUEUE_MEM_SETTINGS = 1 << 9 271*fc0f7dc4SLuca Vizzarro #: Hairpin RX queues will use locked device memory. 272*fc0f7dc4SLuca Vizzarro RX_QUEUE_USE_LOCKED_DEVICE_MEMORY = 1 << 12 273*fc0f7dc4SLuca Vizzarro #: Hairpin RX queues will use RTE memory. 274*fc0f7dc4SLuca Vizzarro RX_QUEUE_USE_RTE_MEMORY = 1 << 13 275*fc0f7dc4SLuca Vizzarro #: Hairpin TX queues will use locked device memory. 276*fc0f7dc4SLuca Vizzarro TX_QUEUE_USE_LOCKED_DEVICE_MEMORY = 1 << 16 277*fc0f7dc4SLuca Vizzarro #: Hairpin TX queues will use RTE memory. 278*fc0f7dc4SLuca Vizzarro TX_QUEUE_USE_RTE_MEMORY = 1 << 18 279*fc0f7dc4SLuca Vizzarro 280*fc0f7dc4SLuca Vizzarro 281*fc0f7dc4SLuca Vizzarro@dataclass(kw_only=True) 282*fc0f7dc4SLuca Vizzarroclass RXRingParams(Params): 283*fc0f7dc4SLuca Vizzarro """Sets the RX ring parameters. 284*fc0f7dc4SLuca Vizzarro 285*fc0f7dc4SLuca Vizzarro Attributes: 286*fc0f7dc4SLuca Vizzarro descriptors: Set the number of descriptors in the RX rings to N, where N > 0. 287*fc0f7dc4SLuca Vizzarro prefetch_threshold: Set the prefetch threshold register of RX rings to N, where N >= 0. 288*fc0f7dc4SLuca Vizzarro host_threshold: Set the host threshold register of RX rings to N, where N >= 0. 289*fc0f7dc4SLuca Vizzarro write_back_threshold: Set the write-back threshold register of RX rings to N, where N >= 0. 290*fc0f7dc4SLuca Vizzarro free_threshold: Set the free threshold of RX descriptors to N, 291*fc0f7dc4SLuca Vizzarro where 0 <= N < value of ``-–rxd``. 292*fc0f7dc4SLuca Vizzarro """ 293*fc0f7dc4SLuca Vizzarro 294*fc0f7dc4SLuca Vizzarro descriptors: int | None = field(default=None, metadata=Params.long("rxd")) 295*fc0f7dc4SLuca Vizzarro prefetch_threshold: int | None = field(default=None, metadata=Params.long("rxpt")) 296*fc0f7dc4SLuca Vizzarro host_threshold: int | None = field(default=None, metadata=Params.long("rxht")) 297*fc0f7dc4SLuca Vizzarro write_back_threshold: int | None = field(default=None, metadata=Params.long("rxwt")) 298*fc0f7dc4SLuca Vizzarro free_threshold: int | None = field(default=None, metadata=Params.long("rxfreet")) 299*fc0f7dc4SLuca Vizzarro 300*fc0f7dc4SLuca Vizzarro 301*fc0f7dc4SLuca Vizzarro@modify_str(hex_from_flag_value) 302*fc0f7dc4SLuca Vizzarro@unique 303*fc0f7dc4SLuca Vizzarroclass RXMultiQueueMode(Flag): 304*fc0f7dc4SLuca Vizzarro """Flag representing the RX multi-queue mode.""" 305*fc0f7dc4SLuca Vizzarro 306*fc0f7dc4SLuca Vizzarro #: 307*fc0f7dc4SLuca Vizzarro RSS = 1 << 0 308*fc0f7dc4SLuca Vizzarro #: 309*fc0f7dc4SLuca Vizzarro DCB = 1 << 1 310*fc0f7dc4SLuca Vizzarro #: 311*fc0f7dc4SLuca Vizzarro VMDQ = 1 << 2 312*fc0f7dc4SLuca Vizzarro 313*fc0f7dc4SLuca Vizzarro 314*fc0f7dc4SLuca Vizzarro@dataclass(kw_only=True) 315*fc0f7dc4SLuca Vizzarroclass TXRingParams(Params): 316*fc0f7dc4SLuca Vizzarro """Sets the TX ring parameters. 317*fc0f7dc4SLuca Vizzarro 318*fc0f7dc4SLuca Vizzarro Attributes: 319*fc0f7dc4SLuca Vizzarro descriptors: Set the number of descriptors in the TX rings to N, where N > 0. 320*fc0f7dc4SLuca Vizzarro rs_bit_threshold: Set the transmit RS bit threshold of TX rings to N, 321*fc0f7dc4SLuca Vizzarro where 0 <= N <= value of ``--txd``. 322*fc0f7dc4SLuca Vizzarro prefetch_threshold: Set the prefetch threshold register of TX rings to N, where N >= 0. 323*fc0f7dc4SLuca Vizzarro host_threshold: Set the host threshold register of TX rings to N, where N >= 0. 324*fc0f7dc4SLuca Vizzarro write_back_threshold: Set the write-back threshold register of TX rings to N, where N >= 0. 325*fc0f7dc4SLuca Vizzarro free_threshold: Set the transmit free threshold of TX rings to N, 326*fc0f7dc4SLuca Vizzarro where 0 <= N <= value of ``--txd``. 327*fc0f7dc4SLuca Vizzarro """ 328*fc0f7dc4SLuca Vizzarro 329*fc0f7dc4SLuca Vizzarro descriptors: int | None = field(default=None, metadata=Params.long("txd")) 330*fc0f7dc4SLuca Vizzarro rs_bit_threshold: int | None = field(default=None, metadata=Params.long("txrst")) 331*fc0f7dc4SLuca Vizzarro prefetch_threshold: int | None = field(default=None, metadata=Params.long("txpt")) 332*fc0f7dc4SLuca Vizzarro host_threshold: int | None = field(default=None, metadata=Params.long("txht")) 333*fc0f7dc4SLuca Vizzarro write_back_threshold: int | None = field(default=None, metadata=Params.long("txwt")) 334*fc0f7dc4SLuca Vizzarro free_threshold: int | None = field(default=None, metadata=Params.long("txfreet")) 335*fc0f7dc4SLuca Vizzarro 336*fc0f7dc4SLuca Vizzarro 337*fc0f7dc4SLuca Vizzarroclass Event(StrEnum): 338*fc0f7dc4SLuca Vizzarro """Enum representing a testpmd event.""" 339*fc0f7dc4SLuca Vizzarro 340*fc0f7dc4SLuca Vizzarro #: 341*fc0f7dc4SLuca Vizzarro unknown = auto() 342*fc0f7dc4SLuca Vizzarro #: 343*fc0f7dc4SLuca Vizzarro queue_state = auto() 344*fc0f7dc4SLuca Vizzarro #: 345*fc0f7dc4SLuca Vizzarro vf_mbox = auto() 346*fc0f7dc4SLuca Vizzarro #: 347*fc0f7dc4SLuca Vizzarro macsec = auto() 348*fc0f7dc4SLuca Vizzarro #: 349*fc0f7dc4SLuca Vizzarro intr_lsc = auto() 350*fc0f7dc4SLuca Vizzarro #: 351*fc0f7dc4SLuca Vizzarro intr_rmv = auto() 352*fc0f7dc4SLuca Vizzarro #: 353*fc0f7dc4SLuca Vizzarro intr_reset = auto() 354*fc0f7dc4SLuca Vizzarro #: 355*fc0f7dc4SLuca Vizzarro dev_probed = auto() 356*fc0f7dc4SLuca Vizzarro #: 357*fc0f7dc4SLuca Vizzarro dev_released = auto() 358*fc0f7dc4SLuca Vizzarro #: 359*fc0f7dc4SLuca Vizzarro flow_aged = auto() 360*fc0f7dc4SLuca Vizzarro #: 361*fc0f7dc4SLuca Vizzarro err_recovering = auto() 362*fc0f7dc4SLuca Vizzarro #: 363*fc0f7dc4SLuca Vizzarro recovery_success = auto() 364*fc0f7dc4SLuca Vizzarro #: 365*fc0f7dc4SLuca Vizzarro recovery_failed = auto() 366*fc0f7dc4SLuca Vizzarro #: 367*fc0f7dc4SLuca Vizzarro all = auto() 368*fc0f7dc4SLuca Vizzarro 369*fc0f7dc4SLuca Vizzarro 370*fc0f7dc4SLuca Vizzarroclass SimpleMempoolAllocationMode(StrEnum): 371*fc0f7dc4SLuca Vizzarro """Enum representing simple mempool allocation modes.""" 372*fc0f7dc4SLuca Vizzarro 373*fc0f7dc4SLuca Vizzarro #: Create and populate mempool using native DPDK memory. 374*fc0f7dc4SLuca Vizzarro native = auto() 375*fc0f7dc4SLuca Vizzarro #: Create and populate mempool using externally and anonymously allocated area. 376*fc0f7dc4SLuca Vizzarro xmem = auto() 377*fc0f7dc4SLuca Vizzarro #: Create and populate mempool using externally and anonymously allocated hugepage area. 378*fc0f7dc4SLuca Vizzarro xmemhuge = auto() 379*fc0f7dc4SLuca Vizzarro 380*fc0f7dc4SLuca Vizzarro 381*fc0f7dc4SLuca Vizzarro@dataclass(kw_only=True) 382*fc0f7dc4SLuca Vizzarroclass AnonMempoolAllocationMode(Params): 383*fc0f7dc4SLuca Vizzarro """Create mempool using native DPDK memory, but populate using anonymous memory. 384*fc0f7dc4SLuca Vizzarro 385*fc0f7dc4SLuca Vizzarro Attributes: 386*fc0f7dc4SLuca Vizzarro no_iova_contig: Enables to create mempool which is not IOVA contiguous. 387*fc0f7dc4SLuca Vizzarro """ 388*fc0f7dc4SLuca Vizzarro 389*fc0f7dc4SLuca Vizzarro _mp_alloc: Literal["anon"] = field(default="anon", init=False, metadata=Params.long("mp-alloc")) 390*fc0f7dc4SLuca Vizzarro no_iova_contig: Switch = None 391*fc0f7dc4SLuca Vizzarro 392*fc0f7dc4SLuca Vizzarro 393*fc0f7dc4SLuca Vizzarro@dataclass(slots=True, kw_only=True) 394*fc0f7dc4SLuca Vizzarroclass TestPmdParams(EalParams): 395*fc0f7dc4SLuca Vizzarro """The testpmd shell parameters. 396*fc0f7dc4SLuca Vizzarro 397*fc0f7dc4SLuca Vizzarro Attributes: 398*fc0f7dc4SLuca Vizzarro interactive_mode: Run testpmd in interactive mode. 399*fc0f7dc4SLuca Vizzarro auto_start: Start forwarding on initialization. 400*fc0f7dc4SLuca Vizzarro tx_first: Start forwarding, after sending a burst of packets first. 401*fc0f7dc4SLuca Vizzarro stats_period: Display statistics every ``PERIOD`` seconds, if interactive mode is disabled. 402*fc0f7dc4SLuca Vizzarro The default value is 0, which means that the statistics will not be displayed. 403*fc0f7dc4SLuca Vizzarro 404*fc0f7dc4SLuca Vizzarro .. note:: This flag should be used only in non-interactive mode. 405*fc0f7dc4SLuca Vizzarro display_xstats: Display comma-separated list of extended statistics every ``PERIOD`` seconds 406*fc0f7dc4SLuca Vizzarro as specified in ``--stats-period`` or when used with interactive commands 407*fc0f7dc4SLuca Vizzarro that show Rx/Tx statistics (i.e. ‘show port stats’). 408*fc0f7dc4SLuca Vizzarro nb_cores: Set the number of forwarding cores, where 1 <= N <= “number of cores” or 409*fc0f7dc4SLuca Vizzarro ``RTE_MAX_LCORE`` from the configuration file. 410*fc0f7dc4SLuca Vizzarro coremask: Set the bitmask of the cores running the packet forwarding test. The main 411*fc0f7dc4SLuca Vizzarro lcore is reserved for command line parsing only and cannot be masked on for packet 412*fc0f7dc4SLuca Vizzarro forwarding. 413*fc0f7dc4SLuca Vizzarro nb_ports: Set the number of forwarding ports, where 1 <= N <= “number of ports” on the board 414*fc0f7dc4SLuca Vizzarro or ``RTE_MAX_ETHPORTS`` from the configuration file. The default value is the 415*fc0f7dc4SLuca Vizzarro number of ports on the board. 416*fc0f7dc4SLuca Vizzarro port_topology: Set port topology, where mode is paired (the default), chained or loop. 417*fc0f7dc4SLuca Vizzarro portmask: Set the bitmask of the ports used by the packet forwarding test. 418*fc0f7dc4SLuca Vizzarro portlist: Set the forwarding ports based on the user input used by the packet forwarding 419*fc0f7dc4SLuca Vizzarro test. ‘-‘ denotes a range of ports to set including the two specified port IDs ‘,’ 420*fc0f7dc4SLuca Vizzarro separates multiple port values. Possible examples like –portlist=0,1 or 421*fc0f7dc4SLuca Vizzarro –portlist=0-2 or –portlist=0,1-2 etc. 422*fc0f7dc4SLuca Vizzarro numa: Enable/disable NUMA-aware allocation of RX/TX rings and of RX memory buffers (mbufs). 423*fc0f7dc4SLuca Vizzarro socket_num: Set the socket from which all memory is allocated in NUMA mode, where 424*fc0f7dc4SLuca Vizzarro 0 <= N < number of sockets on the board. 425*fc0f7dc4SLuca Vizzarro port_numa_config: Specify the socket on which the memory pool to be used by the port will be 426*fc0f7dc4SLuca Vizzarro allocated. 427*fc0f7dc4SLuca Vizzarro ring_numa_config: Specify the socket on which the TX/RX rings for the port will be 428*fc0f7dc4SLuca Vizzarro allocated. Where flag is 1 for RX, 2 for TX, and 3 for RX and TX. 429*fc0f7dc4SLuca Vizzarro total_num_mbufs: Set the number of mbufs to be allocated in the mbuf pools, where N > 1024. 430*fc0f7dc4SLuca Vizzarro mbuf_size: Set the data size of the mbufs used to N bytes, where N < 65536. 431*fc0f7dc4SLuca Vizzarro If multiple mbuf-size values are specified the extra memory pools will be created 432*fc0f7dc4SLuca Vizzarro for allocating mbufs to receive packets with buffer splitting features. 433*fc0f7dc4SLuca Vizzarro mbcache: Set the cache of mbuf memory pools to N, where 0 <= N <= 512. 434*fc0f7dc4SLuca Vizzarro max_pkt_len: Set the maximum packet size to N bytes, where N >= 64. 435*fc0f7dc4SLuca Vizzarro eth_peers_configfile: Use a configuration file containing the Ethernet addresses of 436*fc0f7dc4SLuca Vizzarro the peer ports. 437*fc0f7dc4SLuca Vizzarro eth_peer: Set the MAC address XX:XX:XX:XX:XX:XX of the peer port N, 438*fc0f7dc4SLuca Vizzarro where 0 <= N < RTE_MAX_ETHPORTS. 439*fc0f7dc4SLuca Vizzarro tx_ip: Set the source and destination IP address used when doing transmit only test. 440*fc0f7dc4SLuca Vizzarro The defaults address values are source 198.18.0.1 and destination 198.18.0.2. 441*fc0f7dc4SLuca Vizzarro These are special purpose addresses reserved for benchmarking (RFC 5735). 442*fc0f7dc4SLuca Vizzarro tx_udp: Set the source and destination UDP port number for transmit test only test. 443*fc0f7dc4SLuca Vizzarro The default port is the port 9 which is defined for the discard protocol (RFC 863). 444*fc0f7dc4SLuca Vizzarro enable_lro: Enable large receive offload. 445*fc0f7dc4SLuca Vizzarro max_lro_pkt_size: Set the maximum LRO aggregated packet size to N bytes, where N >= 64. 446*fc0f7dc4SLuca Vizzarro disable_crc_strip: Disable hardware CRC stripping. 447*fc0f7dc4SLuca Vizzarro enable_scatter: Enable scatter (multi-segment) RX. 448*fc0f7dc4SLuca Vizzarro enable_hw_vlan: Enable hardware VLAN. 449*fc0f7dc4SLuca Vizzarro enable_hw_vlan_filter: Enable hardware VLAN filter. 450*fc0f7dc4SLuca Vizzarro enable_hw_vlan_strip: Enable hardware VLAN strip. 451*fc0f7dc4SLuca Vizzarro enable_hw_vlan_extend: Enable hardware VLAN extend. 452*fc0f7dc4SLuca Vizzarro enable_hw_qinq_strip: Enable hardware QINQ strip. 453*fc0f7dc4SLuca Vizzarro pkt_drop_enabled: Enable per-queue packet drop for packets with no descriptors. 454*fc0f7dc4SLuca Vizzarro rss: Receive Side Scaling setting. 455*fc0f7dc4SLuca Vizzarro forward_mode: Set the forwarding mode. 456*fc0f7dc4SLuca Vizzarro hairpin_mode: Set the hairpin port configuration. 457*fc0f7dc4SLuca Vizzarro hairpin_queues: Set the number of hairpin queues per port to N, where 1 <= N <= 65535. 458*fc0f7dc4SLuca Vizzarro burst: Set the number of packets per burst to N, where 1 <= N <= 512. 459*fc0f7dc4SLuca Vizzarro enable_rx_cksum: Enable hardware RX checksum offload. 460*fc0f7dc4SLuca Vizzarro rx_queues: Set the number of RX queues per port to N, where 1 <= N <= 65535. 461*fc0f7dc4SLuca Vizzarro rx_ring: Set the RX rings parameters. 462*fc0f7dc4SLuca Vizzarro no_flush_rx: Don’t flush the RX streams before starting forwarding. Used mainly with 463*fc0f7dc4SLuca Vizzarro the PCAP PMD. 464*fc0f7dc4SLuca Vizzarro rx_segments_offsets: Set the offsets of packet segments on receiving 465*fc0f7dc4SLuca Vizzarro if split feature is engaged. 466*fc0f7dc4SLuca Vizzarro rx_segments_length: Set the length of segments to scatter packets on receiving 467*fc0f7dc4SLuca Vizzarro if split feature is engaged. 468*fc0f7dc4SLuca Vizzarro multi_rx_mempool: Enable multiple mbuf pools per Rx queue. 469*fc0f7dc4SLuca Vizzarro rx_shared_queue: Create queues in shared Rx queue mode if device supports. Shared Rx queues 470*fc0f7dc4SLuca Vizzarro are grouped per X ports. X defaults to UINT32_MAX, implies all ports join 471*fc0f7dc4SLuca Vizzarro share group 1. Forwarding engine “shared-rxq” should be used for shared Rx 472*fc0f7dc4SLuca Vizzarro queues. This engine does Rx only and update stream statistics accordingly. 473*fc0f7dc4SLuca Vizzarro rx_offloads: Set the bitmask of RX queue offloads. 474*fc0f7dc4SLuca Vizzarro rx_mq_mode: Set the RX multi queue mode which can be enabled. 475*fc0f7dc4SLuca Vizzarro tx_queues: Set the number of TX queues per port to N, where 1 <= N <= 65535. 476*fc0f7dc4SLuca Vizzarro tx_ring: Set the TX rings params. 477*fc0f7dc4SLuca Vizzarro tx_offloads: Set the hexadecimal bitmask of TX queue offloads. 478*fc0f7dc4SLuca Vizzarro eth_link_speed: Set a forced link speed to the ethernet port. E.g. 1000 for 1Gbps. 479*fc0f7dc4SLuca Vizzarro disable_link_check: Disable check on link status when starting/stopping ports. 480*fc0f7dc4SLuca Vizzarro disable_device_start: Do not automatically start all ports. This allows testing 481*fc0f7dc4SLuca Vizzarro configuration of rx and tx queues before device is started 482*fc0f7dc4SLuca Vizzarro for the first time. 483*fc0f7dc4SLuca Vizzarro no_lsc_interrupt: Disable LSC interrupts for all ports, even those supporting it. 484*fc0f7dc4SLuca Vizzarro no_rmv_interrupt: Disable RMV interrupts for all ports, even those supporting it. 485*fc0f7dc4SLuca Vizzarro bitrate_stats: Set the logical core N to perform bitrate calculation. 486*fc0f7dc4SLuca Vizzarro latencystats: Set the logical core N to perform latency and jitter calculations. 487*fc0f7dc4SLuca Vizzarro print_events: Enable printing the occurrence of the designated events. 488*fc0f7dc4SLuca Vizzarro Using :attr:`TestPmdEvent.ALL` will enable all of them. 489*fc0f7dc4SLuca Vizzarro mask_events: Disable printing the occurrence of the designated events. 490*fc0f7dc4SLuca Vizzarro Using :attr:`TestPmdEvent.ALL` will disable all of them. 491*fc0f7dc4SLuca Vizzarro flow_isolate_all: Providing this parameter requests flow API isolated mode on all ports at 492*fc0f7dc4SLuca Vizzarro initialization time. It ensures all traffic is received through the 493*fc0f7dc4SLuca Vizzarro configured flow rules only (see flow command). Ports that do not support 494*fc0f7dc4SLuca Vizzarro this mode are automatically discarded. 495*fc0f7dc4SLuca Vizzarro disable_flow_flush: Disable port flow flush when stopping port. 496*fc0f7dc4SLuca Vizzarro This allows testing keep flow rules or shared flow objects across 497*fc0f7dc4SLuca Vizzarro restart. 498*fc0f7dc4SLuca Vizzarro hot_plug: Enable device event monitor mechanism for hotplug. 499*fc0f7dc4SLuca Vizzarro vxlan_gpe_port: Set the UDP port number of tunnel VXLAN-GPE to N. 500*fc0f7dc4SLuca Vizzarro geneve_parsed_port: Set the UDP port number that is used for parsing the GENEVE protocol 501*fc0f7dc4SLuca Vizzarro to N. HW may be configured with another tunnel Geneve port. 502*fc0f7dc4SLuca Vizzarro lock_all_memory: Enable/disable locking all memory. Disabled by default. 503*fc0f7dc4SLuca Vizzarro mempool_allocation_mode: Set mempool allocation mode. 504*fc0f7dc4SLuca Vizzarro record_core_cycles: Enable measurement of CPU cycles per packet. 505*fc0f7dc4SLuca Vizzarro record_burst_status: Enable display of RX and TX burst stats. 506*fc0f7dc4SLuca Vizzarro """ 507*fc0f7dc4SLuca Vizzarro 508*fc0f7dc4SLuca Vizzarro interactive_mode: Switch = field(default=True, metadata=Params.short("i")) 509*fc0f7dc4SLuca Vizzarro auto_start: Switch = field(default=None, metadata=Params.short("a")) 510*fc0f7dc4SLuca Vizzarro tx_first: Switch = None 511*fc0f7dc4SLuca Vizzarro stats_period: int | None = None 512*fc0f7dc4SLuca Vizzarro display_xstats: list[str] | None = field( 513*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.convert_value(comma_separated) 514*fc0f7dc4SLuca Vizzarro ) 515*fc0f7dc4SLuca Vizzarro nb_cores: int | None = None 516*fc0f7dc4SLuca Vizzarro coremask: int | None = field(default=None, metadata=Params.convert_value(hex)) 517*fc0f7dc4SLuca Vizzarro nb_ports: int | None = None 518*fc0f7dc4SLuca Vizzarro port_topology: PortTopology | None = PortTopology.paired 519*fc0f7dc4SLuca Vizzarro portmask: int | None = field(default=None, metadata=Params.convert_value(hex)) 520*fc0f7dc4SLuca Vizzarro portlist: str | None = None # TODO: can be ranges 0,1-3 521*fc0f7dc4SLuca Vizzarro 522*fc0f7dc4SLuca Vizzarro numa: YesNoSwitch = None 523*fc0f7dc4SLuca Vizzarro socket_num: int | None = None 524*fc0f7dc4SLuca Vizzarro port_numa_config: list[PortNUMAConfig] | None = field( 525*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.convert_value(comma_separated) 526*fc0f7dc4SLuca Vizzarro ) 527*fc0f7dc4SLuca Vizzarro ring_numa_config: list[RingNUMAConfig] | None = field( 528*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.convert_value(comma_separated) 529*fc0f7dc4SLuca Vizzarro ) 530*fc0f7dc4SLuca Vizzarro total_num_mbufs: int | None = None 531*fc0f7dc4SLuca Vizzarro mbuf_size: list[int] | None = field( 532*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.convert_value(comma_separated) 533*fc0f7dc4SLuca Vizzarro ) 534*fc0f7dc4SLuca Vizzarro mbcache: int | None = None 535*fc0f7dc4SLuca Vizzarro max_pkt_len: int | None = None 536*fc0f7dc4SLuca Vizzarro eth_peers_configfile: PurePath | None = None 537*fc0f7dc4SLuca Vizzarro eth_peer: list[EthPeer] | None = field(default=None, metadata=Params.multiple()) 538*fc0f7dc4SLuca Vizzarro tx_ip: TxIPAddrPair | None = None 539*fc0f7dc4SLuca Vizzarro tx_udp: TxUDPPortPair | None = None 540*fc0f7dc4SLuca Vizzarro enable_lro: Switch = None 541*fc0f7dc4SLuca Vizzarro max_lro_pkt_size: int | None = None 542*fc0f7dc4SLuca Vizzarro disable_crc_strip: Switch = None 543*fc0f7dc4SLuca Vizzarro enable_scatter: Switch = None 544*fc0f7dc4SLuca Vizzarro enable_hw_vlan: Switch = None 545*fc0f7dc4SLuca Vizzarro enable_hw_vlan_filter: Switch = None 546*fc0f7dc4SLuca Vizzarro enable_hw_vlan_strip: Switch = None 547*fc0f7dc4SLuca Vizzarro enable_hw_vlan_extend: Switch = None 548*fc0f7dc4SLuca Vizzarro enable_hw_qinq_strip: Switch = None 549*fc0f7dc4SLuca Vizzarro pkt_drop_enabled: Switch = field(default=None, metadata=Params.long("enable-drop-en")) 550*fc0f7dc4SLuca Vizzarro rss: RSSSetting | None = None 551*fc0f7dc4SLuca Vizzarro forward_mode: ( 552*fc0f7dc4SLuca Vizzarro SimpleForwardingModes 553*fc0f7dc4SLuca Vizzarro | FlowGenForwardingMode 554*fc0f7dc4SLuca Vizzarro | TXOnlyForwardingMode 555*fc0f7dc4SLuca Vizzarro | NoisyForwardingMode 556*fc0f7dc4SLuca Vizzarro | None 557*fc0f7dc4SLuca Vizzarro ) = None 558*fc0f7dc4SLuca Vizzarro hairpin_mode: HairpinMode | None = None 559*fc0f7dc4SLuca Vizzarro hairpin_queues: int | None = field(default=None, metadata=Params.long("hairpinq")) 560*fc0f7dc4SLuca Vizzarro burst: int | None = None 561*fc0f7dc4SLuca Vizzarro enable_rx_cksum: Switch = None 562*fc0f7dc4SLuca Vizzarro 563*fc0f7dc4SLuca Vizzarro rx_queues: int | None = field(default=None, metadata=Params.long("rxq")) 564*fc0f7dc4SLuca Vizzarro rx_ring: RXRingParams | None = None 565*fc0f7dc4SLuca Vizzarro no_flush_rx: Switch = None 566*fc0f7dc4SLuca Vizzarro rx_segments_offsets: list[int] | None = field( 567*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("rxoffs") | Params.convert_value(comma_separated) 568*fc0f7dc4SLuca Vizzarro ) 569*fc0f7dc4SLuca Vizzarro rx_segments_length: list[int] | None = field( 570*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("rxpkts") | Params.convert_value(comma_separated) 571*fc0f7dc4SLuca Vizzarro ) 572*fc0f7dc4SLuca Vizzarro multi_rx_mempool: Switch = None 573*fc0f7dc4SLuca Vizzarro rx_shared_queue: Switch | int = field(default=None, metadata=Params.long("rxq-share")) 574*fc0f7dc4SLuca Vizzarro rx_offloads: int | None = field(default=None, metadata=Params.convert_value(hex)) 575*fc0f7dc4SLuca Vizzarro rx_mq_mode: RXMultiQueueMode | None = None 576*fc0f7dc4SLuca Vizzarro 577*fc0f7dc4SLuca Vizzarro tx_queues: int | None = field(default=None, metadata=Params.long("txq")) 578*fc0f7dc4SLuca Vizzarro tx_ring: TXRingParams | None = None 579*fc0f7dc4SLuca Vizzarro tx_offloads: int | None = field(default=None, metadata=Params.convert_value(hex)) 580*fc0f7dc4SLuca Vizzarro 581*fc0f7dc4SLuca Vizzarro eth_link_speed: int | None = None 582*fc0f7dc4SLuca Vizzarro disable_link_check: Switch = None 583*fc0f7dc4SLuca Vizzarro disable_device_start: Switch = None 584*fc0f7dc4SLuca Vizzarro no_lsc_interrupt: Switch = None 585*fc0f7dc4SLuca Vizzarro no_rmv_interrupt: Switch = None 586*fc0f7dc4SLuca Vizzarro bitrate_stats: int | None = None 587*fc0f7dc4SLuca Vizzarro latencystats: int | None = None 588*fc0f7dc4SLuca Vizzarro print_events: list[Event] | None = field( 589*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.multiple() | Params.long("print-event") 590*fc0f7dc4SLuca Vizzarro ) 591*fc0f7dc4SLuca Vizzarro mask_events: list[Event] | None = field( 592*fc0f7dc4SLuca Vizzarro default_factory=lambda: [Event.intr_lsc], 593*fc0f7dc4SLuca Vizzarro metadata=Params.multiple() | Params.long("mask-event"), 594*fc0f7dc4SLuca Vizzarro ) 595*fc0f7dc4SLuca Vizzarro 596*fc0f7dc4SLuca Vizzarro flow_isolate_all: Switch = None 597*fc0f7dc4SLuca Vizzarro disable_flow_flush: Switch = None 598*fc0f7dc4SLuca Vizzarro 599*fc0f7dc4SLuca Vizzarro hot_plug: Switch = None 600*fc0f7dc4SLuca Vizzarro vxlan_gpe_port: int | None = None 601*fc0f7dc4SLuca Vizzarro geneve_parsed_port: int | None = None 602*fc0f7dc4SLuca Vizzarro lock_all_memory: YesNoSwitch = field(default=None, metadata=Params.long("mlockall")) 603*fc0f7dc4SLuca Vizzarro mempool_allocation_mode: SimpleMempoolAllocationMode | AnonMempoolAllocationMode | None = field( 604*fc0f7dc4SLuca Vizzarro default=None, metadata=Params.long("mp-alloc") 605*fc0f7dc4SLuca Vizzarro ) 606*fc0f7dc4SLuca Vizzarro record_core_cycles: Switch = None 607*fc0f7dc4SLuca Vizzarro record_burst_status: Switch = None 608