1cc07a42dSMatan Azrad /* SPDX-License-Identifier: BSD-3-Clause 2cc07a42dSMatan Azrad * Copyright 2019 Mellanox Technologies, Ltd 3cc07a42dSMatan Azrad */ 4cc07a42dSMatan Azrad 5cc07a42dSMatan Azrad #ifndef RTE_PMD_MLX5_VDPA_H_ 6cc07a42dSMatan Azrad #define RTE_PMD_MLX5_VDPA_H_ 7cc07a42dSMatan Azrad 82aa8444bSMatan Azrad #include <linux/virtio_net.h> 9cc07a42dSMatan Azrad #include <sys/queue.h> 10cc07a42dSMatan Azrad 11cc07a42dSMatan Azrad #ifdef PEDANTIC 12cc07a42dSMatan Azrad #pragma GCC diagnostic ignored "-Wpedantic" 13cc07a42dSMatan Azrad #endif 14cc07a42dSMatan Azrad #include <rte_vdpa.h> 1594c16e89SMaxime Coquelin #include <vdpa_driver.h> 16cc07a42dSMatan Azrad #include <rte_vhost.h> 17cc07a42dSMatan Azrad #ifdef PEDANTIC 18cc07a42dSMatan Azrad #pragma GCC diagnostic error "-Wpedantic" 19cc07a42dSMatan Azrad #endif 208395927cSMatan Azrad #include <rte_spinlock.h> 218395927cSMatan Azrad #include <rte_interrupts.h> 22a7ba40b2SThomas Monjalon #include <rte_thread.h> 23cc07a42dSMatan Azrad 24cc07a42dSMatan Azrad #include <mlx5_glue.h> 25cc07a42dSMatan Azrad #include <mlx5_devx_cmds.h> 260e41abd1SMichael Baum #include <mlx5_common_devx.h> 278395927cSMatan Azrad #include <mlx5_prm.h> 288395927cSMatan Azrad 298395927cSMatan Azrad 308395927cSMatan Azrad #define MLX5_VDPA_INTR_RETRIES 256 318395927cSMatan Azrad #define MLX5_VDPA_INTR_RETRIES_USEC 1000 328395927cSMatan Azrad 332aa8444bSMatan Azrad #ifndef VIRTIO_F_ORDER_PLATFORM 342aa8444bSMatan Azrad #define VIRTIO_F_ORDER_PLATFORM 36 352aa8444bSMatan Azrad #endif 362aa8444bSMatan Azrad 372aa8444bSMatan Azrad #ifndef VIRTIO_F_RING_PACKED 382aa8444bSMatan Azrad #define VIRTIO_F_RING_PACKED 34 392aa8444bSMatan Azrad #endif 402aa8444bSMatan Azrad 41c9a189f4SXueming Li #define MLX5_VDPA_DEFAULT_TIMER_DELAY_US 0u 42edc6391eSMatan Azrad #define MLX5_VDPA_DEFAULT_TIMER_STEP_US 1u 43edc6391eSMatan Azrad 448395927cSMatan Azrad struct mlx5_vdpa_cq { 458395927cSMatan Azrad uint16_t log_desc_n; 468395927cSMatan Azrad uint32_t cq_ci:24; 478395927cSMatan Azrad uint32_t arm_sn:2; 48a9dd7275SMatan Azrad uint32_t armed:1; 49d76a17f7SMatan Azrad int callfd; 508395927cSMatan Azrad rte_spinlock_t sl; 510e41abd1SMichael Baum struct mlx5_devx_cq cq_obj; 528395927cSMatan Azrad uint64_t errors; 538395927cSMatan Azrad }; 548395927cSMatan Azrad 558395927cSMatan Azrad struct mlx5_vdpa_event_qp { 568395927cSMatan Azrad struct mlx5_vdpa_cq cq; 578395927cSMatan Azrad struct mlx5_devx_obj *fw_qp; 58f9213ab1SRaja Zidane struct mlx5_devx_qp sw_qp; 5924969c7bSYajun Wu uint16_t qp_pi; 608395927cSMatan Azrad }; 61cc07a42dSMatan Azrad 62cc07a42dSMatan Azrad struct mlx5_vdpa_query_mr { 6304b4e4cbSMichael Baum union { 6404b4e4cbSMichael Baum struct ibv_mr *mr; 65cc07a42dSMatan Azrad struct mlx5_devx_obj *mkey; 6604b4e4cbSMichael Baum }; 67cc07a42dSMatan Azrad int is_indirect; 68cc07a42dSMatan Azrad }; 69cc07a42dSMatan Azrad 70c47d6e83SMatan Azrad enum { 71c47d6e83SMatan Azrad MLX5_VDPA_NOTIFIER_STATE_DISABLED, 72c47d6e83SMatan Azrad MLX5_VDPA_NOTIFIER_STATE_ENABLED, 73c47d6e83SMatan Azrad MLX5_VDPA_NOTIFIER_STATE_ERR 74c47d6e83SMatan Azrad }; 75c47d6e83SMatan Azrad 760d9d2897SLi Zhang #define MLX5_VDPA_USED_RING_LEN(size) \ 770d9d2897SLi Zhang ((size) * sizeof(struct vring_used_elem) + sizeof(uint16_t) * 3) 7867b07093SLi Zhang #define MLX5_VDPA_MAX_C_THRD 256 7969e07f43SLi Zhang #define MLX5_VDPA_MAX_TASKS_PER_THRD 4096 8069e07f43SLi Zhang #define MLX5_VDPA_TASKS_PER_DEV 64 8106ebaaeaSLi Zhang #define MLX5_VDPA_MAX_MRS 0xFFFF 8206ebaaeaSLi Zhang 8306ebaaeaSLi Zhang /* Vdpa task types. */ 8406ebaaeaSLi Zhang enum mlx5_vdpa_task_type { 8506ebaaeaSLi Zhang MLX5_VDPA_TASK_REG_MR = 1, 868e72e6bdSLi Zhang MLX5_VDPA_TASK_SETUP_VIRTQ, 870d9d2897SLi Zhang MLX5_VDPA_TASK_STOP_VIRTQ, 886ebb02b4SLi Zhang MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT, 89cac75b2dSLi Zhang MLX5_VDPA_TASK_PREPARE_VIRTQ, 9006ebaaeaSLi Zhang }; 9169e07f43SLi Zhang 9269e07f43SLi Zhang /* Generic task information and size must be multiple of 4B. */ 93*e7750639SAndre Muezerie struct __rte_aligned(4) __rte_packed_begin mlx5_vdpa_task { 9469e07f43SLi Zhang struct mlx5_vdpa_priv *priv; 9506ebaaeaSLi Zhang enum mlx5_vdpa_task_type type; 96e12a0166STyler Retzlaff RTE_ATOMIC(uint32_t) *remaining_cnt; 97e12a0166STyler Retzlaff RTE_ATOMIC(uint32_t) *err_cnt; 9869e07f43SLi Zhang uint32_t idx; 99*e7750639SAndre Muezerie } __rte_packed_end; 10067b07093SLi Zhang 10167b07093SLi Zhang /* Generic mlx5_vdpa_c_thread information. */ 10267b07093SLi Zhang struct mlx5_vdpa_c_thread { 103a7ba40b2SThomas Monjalon rte_thread_t tid; 10469e07f43SLi Zhang struct rte_ring *rng; 10569e07f43SLi Zhang pthread_cond_t c_cond; 10667b07093SLi Zhang }; 10767b07093SLi Zhang 10867b07093SLi Zhang struct mlx5_vdpa_conf_thread_mng { 10967b07093SLi Zhang void *initializer_priv; 110e12a0166STyler Retzlaff RTE_ATOMIC(uint32_t) refcnt; 11167b07093SLi Zhang uint32_t max_thrds; 11267b07093SLi Zhang pthread_mutex_t cthrd_lock; 11367b07093SLi Zhang struct mlx5_vdpa_c_thread cthrd[MLX5_VDPA_MAX_C_THRD]; 11467b07093SLi Zhang }; 11567b07093SLi Zhang extern struct mlx5_vdpa_conf_thread_mng conf_thread_mng; 11667b07093SLi Zhang 11706ebaaeaSLi Zhang struct mlx5_vdpa_vmem_info { 11806ebaaeaSLi Zhang struct rte_vhost_memory *vmem; 11906ebaaeaSLi Zhang uint32_t entries_num; 12006ebaaeaSLi Zhang uint64_t gcd; 12106ebaaeaSLi Zhang uint64_t size; 12206ebaaeaSLi Zhang uint8_t mode; 12306ebaaeaSLi Zhang }; 12406ebaaeaSLi Zhang 125bff73501SMatan Azrad struct mlx5_vdpa_virtq { 126bff73501SMatan Azrad SLIST_ENTRY(mlx5_vdpa_virtq) next; 127bff73501SMatan Azrad uint16_t index; 128bff73501SMatan Azrad uint16_t vq_size; 129c47d6e83SMatan Azrad uint8_t notifier_state; 1307f2de212SLi Zhang uint32_t configured:1; 1318e72e6bdSLi Zhang uint32_t enable:1; 1328e72e6bdSLi Zhang uint32_t stopped:1; 133cac75b2dSLi Zhang uint32_t rx_csum:1; 134cac75b2dSLi Zhang uint32_t virtio_version_1_0:1; 135cac75b2dSLi Zhang uint32_t event_mode:3; 1360474419bSXueming Li uint32_t version; 137057f7d20SLi Zhang pthread_mutex_t virtq_lock; 138af72fdb5SMatan Azrad struct mlx5_vdpa_priv *priv; 139bff73501SMatan Azrad struct mlx5_devx_obj *virtq; 1407de66d82SMatan Azrad struct mlx5_devx_obj *counters; 141bff73501SMatan Azrad struct mlx5_vdpa_event_qp eqp; 142bff73501SMatan Azrad struct { 143bff73501SMatan Azrad struct mlx5dv_devx_umem *obj; 144bff73501SMatan Azrad void *buf; 145bff73501SMatan Azrad uint32_t size; 146bff73501SMatan Azrad } umems[3]; 147d61138d4SHarman Kalra struct rte_intr_handle *intr_handle; 1480474419bSXueming Li uint64_t err_time[3]; /* RDTSC time of recent errors. */ 1490474419bSXueming Li uint32_t n_retry; 150476048d5SXueming Li struct mlx5_devx_virtio_q_couners_attr stats; 1517de66d82SMatan Azrad struct mlx5_devx_virtio_q_couners_attr reset; 152bff73501SMatan Azrad }; 153bff73501SMatan Azrad 154a5a1d98dSMatan Azrad struct mlx5_vdpa_steer { 155a5a1d98dSMatan Azrad struct mlx5_devx_obj *rqt; 156a5a1d98dSMatan Azrad void *domain; 157a5a1d98dSMatan Azrad void *tbl; 158a5a1d98dSMatan Azrad struct { 159a5a1d98dSMatan Azrad struct mlx5dv_flow_matcher *matcher; 160a5a1d98dSMatan Azrad struct mlx5_devx_obj *tir; 161a5a1d98dSMatan Azrad void *tir_action; 162a5a1d98dSMatan Azrad void *flow; 163a5a1d98dSMatan Azrad } rss[7]; 164a5a1d98dSMatan Azrad }; 165a5a1d98dSMatan Azrad 166edc6391eSMatan Azrad enum { 167edc6391eSMatan Azrad MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER, 168edc6391eSMatan Azrad MLX5_VDPA_EVENT_MODE_FIXED_TIMER, 169edc6391eSMatan Azrad MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT 170edc6391eSMatan Azrad }; 171edc6391eSMatan Azrad 172b19cc62cSXueming Li enum mlx5_dev_state { 173b19cc62cSXueming Li MLX5_VDPA_STATE_PROBED = 0, 174b19cc62cSXueming Li MLX5_VDPA_STATE_CONFIGURED, 175b19cc62cSXueming Li MLX5_VDPA_STATE_IN_PROGRESS /* Shutting down. */ 176b19cc62cSXueming Li }; 177b19cc62cSXueming Li 178cc07a42dSMatan Azrad struct mlx5_vdpa_priv { 179cc07a42dSMatan Azrad TAILQ_ENTRY(mlx5_vdpa_priv) next; 180d7e5d5a7SXueming Li bool connected; 18167b07093SLi Zhang bool use_c_thread; 182b19cc62cSXueming Li enum mlx5_dev_state state; 183057f7d20SLi Zhang rte_spinlock_t db_lock; 184057f7d20SLi Zhang pthread_mutex_t steer_update_lock; 18599f9d799SMatan Azrad uint64_t no_traffic_counter; 186a7ba40b2SThomas Monjalon rte_thread_t timer_tid; 187edc6391eSMatan Azrad int event_mode; 1885cf3fd3aSXueming Li int event_core; /* Event thread cpu affinity core. */ 189edc6391eSMatan Azrad uint32_t event_us; 190a9dd7275SMatan Azrad uint32_t timer_delay_us; 19199f9d799SMatan Azrad uint32_t no_traffic_max; 1921f93bee4SXueming Li uint8_t hw_latency_mode; /* Hardware CQ moderation mode. */ 1931f93bee4SXueming Li uint16_t hw_max_latency_us; /* Hardware CQ moderation period in usec. */ 1941f93bee4SXueming Li uint16_t hw_max_pending_comp; /* Hardware CQ moderation counter. */ 19542a8fc7dSYajun Wu uint16_t queue_size; /* virtq depth for pre-creating virtq resource */ 19642a8fc7dSYajun Wu uint16_t queues; /* Max virtq pair for pre-creating virtq resource */ 19781a6b7feSMaxime Coquelin struct rte_vdpa_device *vdev; /* vDPA device. */ 198662d0dc6SMichael Baum struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 199cc07a42dSMatan Azrad int vid; /* vhost device id. */ 200cc07a42dSMatan Azrad struct mlx5_hca_vdpa_attr caps; 201cc07a42dSMatan Azrad uint32_t gpa_mkey_index; 202cc07a42dSMatan Azrad struct ibv_mr *null_mr; 20306ebaaeaSLi Zhang struct mlx5_vdpa_vmem_info vmem_info; 2048395927cSMatan Azrad struct mlx5dv_devx_event_channel *eventc; 2050474419bSXueming Li struct mlx5dv_devx_event_channel *err_chnl; 2065dfa003dSMichael Baum struct mlx5_uar uar; 207d61138d4SHarman Kalra struct rte_intr_handle *err_intr_handle; 208bff73501SMatan Azrad struct mlx5_devx_obj *td; 209c783fd43SXueming Li struct mlx5_devx_obj *tiss[16]; /* TIS list for each LAG port. */ 210bff73501SMatan Azrad uint16_t nr_virtqs; 211c783fd43SXueming Li uint8_t num_lag_ports; 2122aa8444bSMatan Azrad uint64_t features; /* Negotiated features. */ 213a5a1d98dSMatan Azrad uint16_t log_max_rqt_size; 21406ebaaeaSLi Zhang uint16_t last_c_thrd_idx; 215e12a0166STyler Retzlaff RTE_ATOMIC(uint16_t) dev_close_progress; 21606ebaaeaSLi Zhang uint16_t num_mrs; /* Number of memory regions. */ 217a5a1d98dSMatan Azrad struct mlx5_vdpa_steer steer; 21862c81370SMatan Azrad struct mlx5dv_var *var; 21962c81370SMatan Azrad void *virtq_db_addr; 220398ea845SMatan Azrad struct mlx5_pmd_wrapped_mr lm_mr; 22106ebaaeaSLi Zhang struct mlx5_vdpa_query_mr **mrs; 222c2eb33aaSMatan Azrad struct mlx5_vdpa_virtq virtqs[]; 223cc07a42dSMatan Azrad }; 224cc07a42dSMatan Azrad 2257de66d82SMatan Azrad enum { 2267de66d82SMatan Azrad MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS, 2277de66d82SMatan Azrad MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS, 2287de66d82SMatan Azrad MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS, 2297de66d82SMatan Azrad MLX5_VDPA_STATS_EXCEED_MAX_CHAIN, 2307de66d82SMatan Azrad MLX5_VDPA_STATS_INVALID_BUFFER, 2317de66d82SMatan Azrad MLX5_VDPA_STATS_COMPLETION_ERRORS, 2327de66d82SMatan Azrad MLX5_VDPA_STATS_MAX 2337de66d82SMatan Azrad }; 2347de66d82SMatan Azrad 2359f09b1caSMatan Azrad /* 2369f09b1caSMatan Azrad * Check whether virtq is for traffic receive. 2379f09b1caSMatan Azrad * According to VIRTIO_NET Spec the virtqueues index identity its type by: 2389f09b1caSMatan Azrad * 0 receiveq1 2399f09b1caSMatan Azrad * 1 transmitq1 2409f09b1caSMatan Azrad * ... 2419f09b1caSMatan Azrad * 2(N-1) receiveqN 2429f09b1caSMatan Azrad * 2(N-1)+1 transmitqN 2439f09b1caSMatan Azrad * 2N controlq 2449f09b1caSMatan Azrad */ 2459f09b1caSMatan Azrad static inline uint8_t 2469f09b1caSMatan Azrad is_virtq_recvq(int virtq_index, int nr_vring) 2479f09b1caSMatan Azrad { 2489f09b1caSMatan Azrad if (virtq_index % 2 == 0 && virtq_index != nr_vring - 1) 2499f09b1caSMatan Azrad return 1; 2509f09b1caSMatan Azrad return 0; 2519f09b1caSMatan Azrad } 2529f09b1caSMatan Azrad 253cc07a42dSMatan Azrad /** 254cc07a42dSMatan Azrad * Release all the prepared memory regions and all their related resources. 255cc07a42dSMatan Azrad * 256cc07a42dSMatan Azrad * @param[in] priv 257cc07a42dSMatan Azrad * The vdpa driver private structure. 258cc07a42dSMatan Azrad */ 259cc07a42dSMatan Azrad void mlx5_vdpa_mem_dereg(struct mlx5_vdpa_priv *priv); 260cc07a42dSMatan Azrad 261cc07a42dSMatan Azrad /** 262cc07a42dSMatan Azrad * Register all the memory regions of the virtio device to the HW and allocate 263cc07a42dSMatan Azrad * all their related resources. 264cc07a42dSMatan Azrad * 265cc07a42dSMatan Azrad * @param[in] priv 266cc07a42dSMatan Azrad * The vdpa driver private structure. 267cc07a42dSMatan Azrad * 268cc07a42dSMatan Azrad * @return 269cc07a42dSMatan Azrad * 0 on success, a negative errno value otherwise and rte_errno is set. 270cc07a42dSMatan Azrad */ 271cc07a42dSMatan Azrad int mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv); 272cc07a42dSMatan Azrad 2738395927cSMatan Azrad 2748395927cSMatan Azrad /** 2758395927cSMatan Azrad * Create an event QP and all its related resources. 2768395927cSMatan Azrad * 2778395927cSMatan Azrad * @param[in] priv 2788395927cSMatan Azrad * The vdpa driver private structure. 2798395927cSMatan Azrad * @param[in] desc_n 2808395927cSMatan Azrad * Number of descriptors. 2818395927cSMatan Azrad * @param[in] callfd 2828395927cSMatan Azrad * The guest notification file descriptor. 283057f7d20SLi Zhang * @param[in/out] virtq 284057f7d20SLi Zhang * Pointer to the virt-queue structure. 28591edbbfbSLi Zhang * @param[in] reset 28691edbbfbSLi Zhang * If true, it will reset event qp. 2878395927cSMatan Azrad * 2888395927cSMatan Azrad * @return 2898395927cSMatan Azrad * 0 on success, -1 otherwise and rte_errno is set. 2908395927cSMatan Azrad */ 291057f7d20SLi Zhang int 292057f7d20SLi Zhang mlx5_vdpa_event_qp_prepare(struct mlx5_vdpa_priv *priv, uint16_t desc_n, 29391edbbfbSLi Zhang int callfd, struct mlx5_vdpa_virtq *virtq, bool reset); 2948395927cSMatan Azrad 2958395927cSMatan Azrad /** 2968395927cSMatan Azrad * Destroy an event QP and all its related resources. 2978395927cSMatan Azrad * 2988395927cSMatan Azrad * @param[in/out] eqp 2998395927cSMatan Azrad * Pointer to the event QP structure. 3008395927cSMatan Azrad */ 3018395927cSMatan Azrad void mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp); 3028395927cSMatan Azrad 3038395927cSMatan Azrad /** 3045fe068bfSXueming Li * Create all the event global resources. 3055fe068bfSXueming Li * 3065fe068bfSXueming Li * @param[in] priv 3075fe068bfSXueming Li * The vdpa driver private structure. 3085fe068bfSXueming Li */ 3095fe068bfSXueming Li int 3105fe068bfSXueming Li mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv); 3115fe068bfSXueming Li 3125fe068bfSXueming Li /** 3138395927cSMatan Azrad * Release all the event global resources. 3148395927cSMatan Azrad * 3158395927cSMatan Azrad * @param[in] priv 3168395927cSMatan Azrad * The vdpa driver private structure. 3178395927cSMatan Azrad */ 3188395927cSMatan Azrad void mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv); 3198395927cSMatan Azrad 3208395927cSMatan Azrad /** 3218395927cSMatan Azrad * Setup CQE event. 3228395927cSMatan Azrad * 3238395927cSMatan Azrad * @param[in] priv 3248395927cSMatan Azrad * The vdpa driver private structure. 3258395927cSMatan Azrad * 3268395927cSMatan Azrad * @return 3278395927cSMatan Azrad * 0 on success, a negative errno value otherwise and rte_errno is set. 3288395927cSMatan Azrad */ 3298395927cSMatan Azrad int mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv); 3308395927cSMatan Azrad 3318395927cSMatan Azrad /** 3328395927cSMatan Azrad * Unset CQE event . 3338395927cSMatan Azrad * 3348395927cSMatan Azrad * @param[in] priv 3358395927cSMatan Azrad * The vdpa driver private structure. 3368395927cSMatan Azrad */ 3378395927cSMatan Azrad void mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv); 3388395927cSMatan Azrad 339bff73501SMatan Azrad /** 3400474419bSXueming Li * Setup error interrupt handler. 3410474419bSXueming Li * 3420474419bSXueming Li * @param[in] priv 3430474419bSXueming Li * The vdpa driver private structure. 3440474419bSXueming Li * 3450474419bSXueming Li * @return 3460474419bSXueming Li * 0 on success, a negative errno value otherwise and rte_errno is set. 3470474419bSXueming Li */ 3480474419bSXueming Li int mlx5_vdpa_err_event_setup(struct mlx5_vdpa_priv *priv); 3490474419bSXueming Li 3500474419bSXueming Li /** 3510474419bSXueming Li * Unset error event handler. 3520474419bSXueming Li * 3530474419bSXueming Li * @param[in] priv 3540474419bSXueming Li * The vdpa driver private structure. 3550474419bSXueming Li */ 3560474419bSXueming Li void mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv); 3570474419bSXueming Li 3580474419bSXueming Li /** 359934ef2b6SXueming Li * Release virtqs and resources except that to be reused. 360bff73501SMatan Azrad * 361bff73501SMatan Azrad * @param[in] priv 362bff73501SMatan Azrad * The vdpa driver private structure. 363cac75b2dSLi Zhang * @param[in] release_resource 364cac75b2dSLi Zhang * The vdpa driver release resource without prepare resource. 365bff73501SMatan Azrad */ 366cac75b2dSLi Zhang void 367cac75b2dSLi Zhang mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv, 368cac75b2dSLi Zhang bool release_resource); 369bff73501SMatan Azrad 370bff73501SMatan Azrad /** 371934ef2b6SXueming Li * Cleanup cached resources of all virtqs. 372934ef2b6SXueming Li * 373934ef2b6SXueming Li * @param[in] priv 374934ef2b6SXueming Li * The vdpa driver private structure. 375934ef2b6SXueming Li */ 376934ef2b6SXueming Li void mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv); 377934ef2b6SXueming Li 378934ef2b6SXueming Li /** 379bff73501SMatan Azrad * Create all the HW virtqs resources and all their related resources. 380bff73501SMatan Azrad * 381bff73501SMatan Azrad * @param[in] priv 382bff73501SMatan Azrad * The vdpa driver private structure. 383bff73501SMatan Azrad * 384bff73501SMatan Azrad * @return 385bff73501SMatan Azrad * 0 on success, a negative errno value otherwise and rte_errno is set. 386bff73501SMatan Azrad */ 387bff73501SMatan Azrad int mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv); 388bff73501SMatan Azrad 389a5a1d98dSMatan Azrad /** 390af72fdb5SMatan Azrad * Enable\Disable virtq.. 391af72fdb5SMatan Azrad * 3929f09b1caSMatan Azrad * @param[in] priv 3939f09b1caSMatan Azrad * The vdpa driver private structure. 3949f09b1caSMatan Azrad * @param[in] index 3959f09b1caSMatan Azrad * The virtq index. 396af72fdb5SMatan Azrad * @param[in] enable 397af72fdb5SMatan Azrad * Set to enable, otherwise disable. 398af72fdb5SMatan Azrad * 399af72fdb5SMatan Azrad * @return 400af72fdb5SMatan Azrad * 0 on success, a negative value otherwise. 401af72fdb5SMatan Azrad */ 4029f09b1caSMatan Azrad int mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable); 403af72fdb5SMatan Azrad 404af72fdb5SMatan Azrad /** 405934ef2b6SXueming Li * Unset steering - stop traffic. 406a5a1d98dSMatan Azrad * 407a5a1d98dSMatan Azrad * @param[in] priv 408a5a1d98dSMatan Azrad * The vdpa driver private structure. 409a5a1d98dSMatan Azrad */ 4109f09b1caSMatan Azrad void mlx5_vdpa_steer_unset(struct mlx5_vdpa_priv *priv); 4119f09b1caSMatan Azrad 4129f09b1caSMatan Azrad /** 4139f09b1caSMatan Azrad * Update steering according to the received queues status. 4149f09b1caSMatan Azrad * 4159f09b1caSMatan Azrad * @param[in] priv 4169f09b1caSMatan Azrad * The vdpa driver private structure. 41791edbbfbSLi Zhang * @param[in] is_dummy 41891edbbfbSLi Zhang * If set, it is updated with dummy queue for prepare resource. 4199f09b1caSMatan Azrad * 4209f09b1caSMatan Azrad * @return 4219f09b1caSMatan Azrad * 0 on success, a negative value otherwise. 4229f09b1caSMatan Azrad */ 42391edbbfbSLi Zhang int mlx5_vdpa_steer_update(struct mlx5_vdpa_priv *priv, bool is_dummy); 424a5a1d98dSMatan Azrad 425a5a1d98dSMatan Azrad /** 426a5a1d98dSMatan Azrad * Setup steering and all its related resources to enable RSS traffic from the 427a5a1d98dSMatan Azrad * device to all the Rx host queues. 428a5a1d98dSMatan Azrad * 429a5a1d98dSMatan Azrad * @param[in] priv 430a5a1d98dSMatan Azrad * The vdpa driver private structure. 431a5a1d98dSMatan Azrad * 432a5a1d98dSMatan Azrad * @return 433a5a1d98dSMatan Azrad * 0 on success, a negative value otherwise. 434a5a1d98dSMatan Azrad */ 435a5a1d98dSMatan Azrad int mlx5_vdpa_steer_setup(struct mlx5_vdpa_priv *priv); 436a5a1d98dSMatan Azrad 4379d39e57fSMatan Azrad /** 4389d39e57fSMatan Azrad * Enable\Disable live migration logging. 4399d39e57fSMatan Azrad * 4409d39e57fSMatan Azrad * @param[in] priv 4419d39e57fSMatan Azrad * The vdpa driver private structure. 4429d39e57fSMatan Azrad * @param[in] enable 4439d39e57fSMatan Azrad * Set for enable, unset for disable. 4449d39e57fSMatan Azrad * 4459d39e57fSMatan Azrad * @return 4469d39e57fSMatan Azrad * 0 on success, a negative value otherwise. 4479d39e57fSMatan Azrad */ 4489d39e57fSMatan Azrad int mlx5_vdpa_logging_enable(struct mlx5_vdpa_priv *priv, int enable); 4499d39e57fSMatan Azrad 4509d39e57fSMatan Azrad /** 4519d39e57fSMatan Azrad * Set dirty bitmap logging to allow live migration. 4529d39e57fSMatan Azrad * 4539d39e57fSMatan Azrad * @param[in] priv 4549d39e57fSMatan Azrad * The vdpa driver private structure. 4559d39e57fSMatan Azrad * @param[in] log_base 4569d39e57fSMatan Azrad * Vhost log base. 4579d39e57fSMatan Azrad * @param[in] log_size 4589d39e57fSMatan Azrad * Vhost log size. 4599d39e57fSMatan Azrad * 4609d39e57fSMatan Azrad * @return 4619d39e57fSMatan Azrad * 0 on success, a negative value otherwise. 4629d39e57fSMatan Azrad */ 4639d39e57fSMatan Azrad int mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, 4649d39e57fSMatan Azrad uint64_t log_size); 4659d39e57fSMatan Azrad 4669d39e57fSMatan Azrad /** 4679d39e57fSMatan Azrad * Log all virtqs information for live migration. 4689d39e57fSMatan Azrad * 4699d39e57fSMatan Azrad * @param[in] priv 4709d39e57fSMatan Azrad * The vdpa driver private structure. 4719d39e57fSMatan Azrad * @param[in] enable 4729d39e57fSMatan Azrad * Set for enable, unset for disable. 4739d39e57fSMatan Azrad * 4749d39e57fSMatan Azrad * @return 4759d39e57fSMatan Azrad * 0 on success, a negative value otherwise. 4769d39e57fSMatan Azrad */ 4779d39e57fSMatan Azrad int mlx5_vdpa_lm_log(struct mlx5_vdpa_priv *priv); 4789d39e57fSMatan Azrad 4799d39e57fSMatan Azrad /** 4809d39e57fSMatan Azrad * Modify virtq state to be ready or suspend. 4819d39e57fSMatan Azrad * 4829d39e57fSMatan Azrad * @param[in] virtq 4839d39e57fSMatan Azrad * The vdpa driver private virtq structure. 4849d39e57fSMatan Azrad * @param[in] state 4859d39e57fSMatan Azrad * Set for ready, otherwise suspend. 4869d39e57fSMatan Azrad * 4879d39e57fSMatan Azrad * @return 4889d39e57fSMatan Azrad * 0 on success, a negative value otherwise. 4899d39e57fSMatan Azrad */ 4909d39e57fSMatan Azrad int mlx5_vdpa_virtq_modify(struct mlx5_vdpa_virtq *virtq, int state); 4919d39e57fSMatan Azrad 4927497873fSMatan Azrad /** 4937497873fSMatan Azrad * Stop virtq before destroying it. 4947497873fSMatan Azrad * 4957497873fSMatan Azrad * @param[in] priv 4967497873fSMatan Azrad * The vdpa driver private structure. 4977497873fSMatan Azrad * @param[in] index 4987497873fSMatan Azrad * The virtq index. 4997497873fSMatan Azrad * 5007497873fSMatan Azrad * @return 5017497873fSMatan Azrad * 0 on success, a negative value otherwise. 5027497873fSMatan Azrad */ 5037497873fSMatan Azrad int mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index); 5047497873fSMatan Azrad 5057de66d82SMatan Azrad /** 5060474419bSXueming Li * Query virtq information. 5070474419bSXueming Li * 5080474419bSXueming Li * @param[in] priv 5090474419bSXueming Li * The vdpa driver private structure. 5100474419bSXueming Li * @param[in] index 5110474419bSXueming Li * The virtq index. 5120474419bSXueming Li * 5130474419bSXueming Li * @return 5140474419bSXueming Li * 0 on success, a negative value otherwise. 5150474419bSXueming Li */ 5160474419bSXueming Li int mlx5_vdpa_virtq_query(struct mlx5_vdpa_priv *priv, int index); 5170474419bSXueming Li 5180474419bSXueming Li /** 5197de66d82SMatan Azrad * Get virtq statistics. 5207de66d82SMatan Azrad * 5217de66d82SMatan Azrad * @param[in] priv 5227de66d82SMatan Azrad * The vdpa driver private structure. 5237de66d82SMatan Azrad * @param[in] qid 5247de66d82SMatan Azrad * The virtq index. 5257de66d82SMatan Azrad * @param stats 5267de66d82SMatan Azrad * The virtq statistics array to fill. 5277de66d82SMatan Azrad * @param n 5287de66d82SMatan Azrad * The number of elements in @p stats array. 5297de66d82SMatan Azrad * 5307de66d82SMatan Azrad * @return 5317de66d82SMatan Azrad * A negative value on error, otherwise the number of entries filled in the 5327de66d82SMatan Azrad * @p stats array. 5337de66d82SMatan Azrad */ 5347de66d82SMatan Azrad int 5357de66d82SMatan Azrad mlx5_vdpa_virtq_stats_get(struct mlx5_vdpa_priv *priv, int qid, 5367de66d82SMatan Azrad struct rte_vdpa_stat *stats, unsigned int n); 5377de66d82SMatan Azrad 5387de66d82SMatan Azrad /** 5397de66d82SMatan Azrad * Reset virtq statistics. 5407de66d82SMatan Azrad * 5417de66d82SMatan Azrad * @param[in] priv 5427de66d82SMatan Azrad * The vdpa driver private structure. 5437de66d82SMatan Azrad * @param[in] qid 5447de66d82SMatan Azrad * The virtq index. 5457de66d82SMatan Azrad * 5467de66d82SMatan Azrad * @return 5477de66d82SMatan Azrad * A negative value on error, otherwise 0. 5487de66d82SMatan Azrad */ 5497de66d82SMatan Azrad int 5507de66d82SMatan Azrad mlx5_vdpa_virtq_stats_reset(struct mlx5_vdpa_priv *priv, int qid); 55124969c7bSYajun Wu 55224969c7bSYajun Wu /** 55324969c7bSYajun Wu * Drain virtq CQ CQE. 55424969c7bSYajun Wu * 55524969c7bSYajun Wu * @param[in] priv 55624969c7bSYajun Wu * The vdpa driver private structure. 55724969c7bSYajun Wu */ 55824969c7bSYajun Wu void 55924969c7bSYajun Wu mlx5_vdpa_drain_cq(struct mlx5_vdpa_priv *priv); 5607f2de212SLi Zhang 5617f2de212SLi Zhang bool 5627f2de212SLi Zhang mlx5_vdpa_is_modify_virtq_supported(struct mlx5_vdpa_priv *priv); 56367b07093SLi Zhang 56467b07093SLi Zhang /** 56567b07093SLi Zhang * Create configuration multi-threads resource 56667b07093SLi Zhang * 56767b07093SLi Zhang * @return 56867b07093SLi Zhang * 0 on success, a negative value otherwise. 56967b07093SLi Zhang */ 57067b07093SLi Zhang int 571a7ba40b2SThomas Monjalon mlx5_vdpa_mult_threads_create(void); 57267b07093SLi Zhang 57367b07093SLi Zhang /** 57467b07093SLi Zhang * Destroy configuration multi-threads resource 57567b07093SLi Zhang * 57667b07093SLi Zhang */ 57767b07093SLi Zhang void 57867b07093SLi Zhang mlx5_vdpa_mult_threads_destroy(bool need_unlock); 57969e07f43SLi Zhang 58069e07f43SLi Zhang bool 58169e07f43SLi Zhang mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv, 58269e07f43SLi Zhang uint32_t thrd_idx, 58306ebaaeaSLi Zhang enum mlx5_vdpa_task_type task_type, 584e12a0166STyler Retzlaff RTE_ATOMIC(uint32_t) *remaining_cnt, RTE_ATOMIC(uint32_t) *err_cnt, 58506ebaaeaSLi Zhang void **task_data, uint32_t num); 58606ebaaeaSLi Zhang int 58706ebaaeaSLi Zhang mlx5_vdpa_register_mr(struct mlx5_vdpa_priv *priv, uint32_t idx); 58806ebaaeaSLi Zhang bool 589e12a0166STyler Retzlaff mlx5_vdpa_c_thread_wait_bulk_tasks_done(RTE_ATOMIC(uint32_t) *remaining_cnt, 590e12a0166STyler Retzlaff RTE_ATOMIC(uint32_t) *err_cnt, uint32_t sleep_time); 5918e72e6bdSLi Zhang int 5928e72e6bdSLi Zhang mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index, bool reg_kick); 5936ebb02b4SLi Zhang void 5946ebb02b4SLi Zhang mlx5_vdpa_dev_cache_clean(struct mlx5_vdpa_priv *priv); 5956ebb02b4SLi Zhang void 5966ebb02b4SLi Zhang mlx5_vdpa_virtq_unreg_intr_handle_all(struct mlx5_vdpa_priv *priv); 59791edbbfbSLi Zhang bool 59891edbbfbSLi Zhang mlx5_vdpa_virtq_single_resource_prepare(struct mlx5_vdpa_priv *priv, 59991edbbfbSLi Zhang int index); 60091edbbfbSLi Zhang int 60191edbbfbSLi Zhang mlx5_vdpa_qps2rst2rts(struct mlx5_vdpa_event_qp *eqp); 60291edbbfbSLi Zhang void 60391edbbfbSLi Zhang mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq); 604cac75b2dSLi Zhang void 605cac75b2dSLi Zhang mlx5_vdpa_prepare_virtq_destroy(struct mlx5_vdpa_priv *priv); 606cc07a42dSMatan Azrad #endif /* RTE_PMD_MLX5_VDPA_H_ */ 607