15c060bf1SMatan Azrad /* SPDX-License-Identifier: BSD-3-Clause 25c060bf1SMatan Azrad * Copyright(c) 2018 Intel Corporation 35c060bf1SMatan Azrad */ 45c060bf1SMatan Azrad 55c060bf1SMatan Azrad #ifndef _IFCVF_OSDEP_H_ 65c060bf1SMatan Azrad #define _IFCVF_OSDEP_H_ 75c060bf1SMatan Azrad 85c060bf1SMatan Azrad #include <stdint.h> 95c060bf1SMatan Azrad 105c060bf1SMatan Azrad #include <rte_cycles.h> 115c060bf1SMatan Azrad #include <rte_pci.h> 121f37cb2bSDavid Marchand #include <bus_pci_driver.h> 135c060bf1SMatan Azrad #include <rte_log.h> 145c060bf1SMatan Azrad #include <rte_io.h> 155c060bf1SMatan Azrad 163178e37cSDavid Marchand extern int ifcvf_vdpa_logtype; 173178e37cSDavid Marchand #define RTE_LOGTYPE_IFCVF_VDPA ifcvf_vdpa_logtype 183178e37cSDavid Marchand 19*fd51012dSAndre Muezerie #define WARNINGOUT(S, ...) RTE_LOG(WARNING, IFCVF_VDPA, S, ##__VA_ARGS__) 20*fd51012dSAndre Muezerie #define DEBUGOUT(S, ...) RTE_LOG(DEBUG, IFCVF_VDPA, S, ##__VA_ARGS__) 215c060bf1SMatan Azrad #define STATIC static 225c060bf1SMatan Azrad 235c060bf1SMatan Azrad #define msec_delay(x) rte_delay_us_sleep(1000 * (x)) 245c060bf1SMatan Azrad 255c060bf1SMatan Azrad #define IFCVF_READ_REG8(reg) rte_read8(reg) 265c060bf1SMatan Azrad #define IFCVF_WRITE_REG8(val, reg) rte_write8((val), (reg)) 275c060bf1SMatan Azrad #define IFCVF_READ_REG16(reg) rte_read16(reg) 285c060bf1SMatan Azrad #define IFCVF_WRITE_REG16(val, reg) rte_write16((val), (reg)) 295c060bf1SMatan Azrad #define IFCVF_READ_REG32(reg) rte_read32(reg) 305c060bf1SMatan Azrad #define IFCVF_WRITE_REG32(val, reg) rte_write32((val), (reg)) 315c060bf1SMatan Azrad 325c060bf1SMatan Azrad typedef struct rte_pci_device PCI_DEV; 335c060bf1SMatan Azrad 345c060bf1SMatan Azrad #define PCI_READ_CONFIG_BYTE(dev, val, where) \ 355c060bf1SMatan Azrad rte_pci_read_config(dev, val, 1, where) 365c060bf1SMatan Azrad 375c060bf1SMatan Azrad #define PCI_READ_CONFIG_DWORD(dev, val, where) \ 385c060bf1SMatan Azrad rte_pci_read_config(dev, val, 4, where) 395c060bf1SMatan Azrad 40baa9c550SDavid Marchand #define PCI_CAPABILITY_LIST RTE_PCI_CAPABILITY_LIST 41baa9c550SDavid Marchand #define PCI_CAP_ID_VNDR RTE_PCI_CAP_ID_VNDR 42baa9c550SDavid Marchand 435c060bf1SMatan Azrad typedef uint8_t u8; 445c060bf1SMatan Azrad typedef int8_t s8; 455c060bf1SMatan Azrad typedef uint16_t u16; 465c060bf1SMatan Azrad typedef int16_t s16; 475c060bf1SMatan Azrad typedef uint32_t u32; 485c060bf1SMatan Azrad typedef int32_t s32; 495c060bf1SMatan Azrad typedef int64_t s64; 505c060bf1SMatan Azrad typedef uint64_t u64; 515c060bf1SMatan Azrad 525c060bf1SMatan Azrad static inline int 535c060bf1SMatan Azrad PCI_READ_CONFIG_RANGE(PCI_DEV *dev, uint32_t *val, int size, int where) 545c060bf1SMatan Azrad { 555c060bf1SMatan Azrad return rte_pci_read_config(dev, val, size, where); 565c060bf1SMatan Azrad } 575c060bf1SMatan Azrad 585c060bf1SMatan Azrad #endif /* _IFCVF_OSDEP_H_ */ 59