1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <strings.h> 7 #include <stdint.h> 8 #include <sys/mman.h> 9 10 #include <rte_malloc.h> 11 #include <rte_log.h> 12 #include <rte_errno.h> 13 #include <rte_bus_pci.h> 14 #include <rte_pci.h> 15 #include <rte_regexdev_driver.h> 16 #include <rte_mbuf.h> 17 18 #include <infiniband/mlx5dv.h> 19 #include <mlx5_glue.h> 20 #include <mlx5_common.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_regex_utils.h" 24 #include "mlx5_rxp.h" 25 #include "mlx5_regex.h" 26 27 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 28 #define MLX5_REGEX_METADATA_SIZE UINT32_C(64) 29 #define MLX5_REGEX_MAX_OUTPUT RTE_BIT32(11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 #define MLX5_REGEX_UMR_WQE_SIZE 192 36 /* The maximum KLMs can be added to one UMR indirect mkey. */ 37 #define MLX5_REGEX_MAX_KLM_NUM 128 38 /* The KLM array size for one job. */ 39 #define MLX5_REGEX_KLMS_SIZE \ 40 ((MLX5_REGEX_MAX_KLM_NUM) * sizeof(struct mlx5_klm)) 41 /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */ 42 #define MLX5_REGEX_UMR_SQ_PI_IDX(pi, ops) \ 43 (((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2)) 44 45 static inline uint32_t 46 sq_size_get(struct mlx5_regex_sq *sq) 47 { 48 return (1U << sq->log_nb_desc); 49 } 50 51 static inline uint32_t 52 cq_size_get(struct mlx5_regex_cq *cq) 53 { 54 return (1U << cq->log_nb_desc); 55 } 56 57 struct mlx5_regex_job { 58 uint64_t user_id; 59 volatile uint8_t *output; 60 volatile uint8_t *metadata; 61 struct mlx5_klm *imkey_array; /* Indirect mkey's KLM array. */ 62 struct mlx5_devx_obj *imkey; /* UMR WQE's indirect meky. */ 63 } __rte_cached_aligned; 64 65 static inline void 66 set_data_seg(struct mlx5_wqe_data_seg *seg, 67 uint32_t length, uint32_t lkey, 68 uintptr_t address) 69 { 70 seg->byte_count = rte_cpu_to_be_32(length); 71 seg->lkey = rte_cpu_to_be_32(lkey); 72 seg->addr = rte_cpu_to_be_64(address); 73 } 74 75 static inline void 76 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 77 uint32_t mmo_control_31_0, uint32_t lkey, 78 uintptr_t address) 79 { 80 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 81 seg->lkey = rte_cpu_to_be_32(lkey); 82 seg->addr = rte_cpu_to_be_64(address); 83 } 84 85 static inline void 86 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 87 uint16_t subset_id1, uint16_t subset_id2, 88 uint16_t subset_id3, uint8_t ctrl) 89 { 90 MLX5_SET(regexp_mmo_control, seg, le, le); 91 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 92 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 93 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 94 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 95 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 96 } 97 98 static inline void 99 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 100 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 101 uint8_t signature, uint32_t imm) 102 { 103 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 104 ((uint32_t)pi << 8) | 105 opcode); 106 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 107 seg->fm_ce_se = fm_ce_se; 108 seg->signature = signature; 109 seg->imm = imm; 110 } 111 112 static inline void 113 __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, 114 struct rte_regex_ops *op, struct mlx5_regex_job *job, 115 size_t pi, struct mlx5_klm *klm) 116 { 117 size_t wqe_offset = (pi & (sq_size_get(sq) - 1)) * 118 (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) + 119 (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0); 120 uint16_t group0 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F ? 121 op->group_id0 : 0; 122 uint16_t group1 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F ? 123 op->group_id1 : 0; 124 uint16_t group2 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F ? 125 op->group_id2 : 0; 126 uint16_t group3 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F ? 127 op->group_id3 : 0; 128 uint8_t control = op->req_flags & 129 RTE_REGEX_OPS_REQ_MATCH_HIGH_PRIORITY_F ? 1 : 0; 130 131 /* For backward compatibility. */ 132 if (!(op->req_flags & (RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F | 133 RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F | 134 RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F | 135 RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F))) 136 group0 = op->group_id0; 137 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; 138 int ds = 4; /* ctrl + meta + input + output */ 139 140 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, 141 (priv->has_umr ? (pi * 4 + 3) : pi), 142 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, 143 sq->sq_obj.sq->id, 0, ds, 0, 0); 144 set_regex_ctrl_seg(wqe + 12, 0, group0, group1, group2, group3, 145 control); 146 struct mlx5_wqe_data_seg *input_seg = 147 (struct mlx5_wqe_data_seg *)(wqe + 148 MLX5_REGEX_WQE_GATHER_OFFSET); 149 input_seg->byte_count = rte_cpu_to_be_32(klm->byte_count); 150 input_seg->addr = rte_cpu_to_be_64(klm->address); 151 input_seg->lkey = klm->mkey; 152 job->user_id = op->user_id; 153 } 154 155 static inline void 156 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 157 struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 158 struct mlx5_regex_job *job) 159 { 160 struct mlx5_klm klm; 161 162 klm.byte_count = rte_pktmbuf_data_len(op->mbuf); 163 klm.mkey = mlx5_mr_addr2mr_bh(priv->pd, 0, 164 &priv->mr_scache, &qp->mr_ctrl, 165 rte_pktmbuf_mtod(op->mbuf, uintptr_t), 166 !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); 167 klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t); 168 __prep_one(priv, sq, op, job, sq->pi, &klm); 169 sq->db_pi = sq->pi; 170 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 171 } 172 173 static inline void 174 send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq) 175 { 176 struct mlx5dv_devx_uar *uar = priv->uar; 177 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 178 (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) + 179 (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0); 180 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; 181 /* Or the fm_ce_se instead of set, avoid the fence be cleared. */ 182 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE; 183 uint64_t *doorbell_addr = 184 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 185 rte_io_wmb(); 186 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32((priv->has_umr ? 187 (sq->db_pi * 4 + 3) : sq->db_pi) & 188 MLX5_REGEX_MAX_WQE_INDEX); 189 rte_wmb(); 190 *doorbell_addr = *(volatile uint64_t *)wqe; 191 rte_wmb(); 192 } 193 194 static inline int 195 get_free(struct mlx5_regex_sq *sq, uint8_t has_umr) { 196 return (sq_size_get(sq) - ((sq->pi - sq->ci) & 197 (has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) : 198 MLX5_REGEX_MAX_WQE_INDEX))); 199 } 200 201 static inline uint32_t 202 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 203 return qid * sq_size + (index & (sq_size - 1)); 204 } 205 206 #ifdef HAVE_MLX5_UMR_IMKEY 207 static inline int 208 mkey_klm_available(struct mlx5_klm *klm, uint32_t pos, uint32_t new) 209 { 210 return (klm && ((pos + new) <= MLX5_REGEX_MAX_KLM_NUM)); 211 } 212 213 static inline void 214 complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_sq *sq, 215 struct mlx5_regex_job *mkey_job, 216 size_t umr_index, uint32_t klm_size, uint32_t total_len) 217 { 218 size_t wqe_offset = (umr_index & (sq_size_get(sq) - 1)) * 219 (MLX5_SEND_WQE_BB * 4); 220 struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *) 221 (uintptr_t)sq->sq_obj.wqes + wqe_offset); 222 struct mlx5_wqe_umr_ctrl_seg *ucseg = 223 (struct mlx5_wqe_umr_ctrl_seg *)(wqe + 1); 224 struct mlx5_wqe_mkey_context_seg *mkc = 225 (struct mlx5_wqe_mkey_context_seg *)(ucseg + 1); 226 struct mlx5_klm *iklm = (struct mlx5_klm *)(mkc + 1); 227 uint16_t klm_align = RTE_ALIGN(klm_size, 4); 228 229 memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE); 230 /* Set WQE control seg. Non-inline KLM UMR WQE size must be 9 WQE_DS. */ 231 set_wqe_ctrl_seg(wqe, (umr_index * 4), MLX5_OPCODE_UMR, 232 0, sq->sq_obj.sq->id, 0, 9, 0, 233 rte_cpu_to_be_32(mkey_job->imkey->id)); 234 /* Set UMR WQE control seg. */ 235 ucseg->mkey_mask |= rte_cpu_to_be_64(MLX5_WQE_UMR_CTRL_MKEY_MASK_LEN | 236 MLX5_WQE_UMR_CTRL_FLAG_TRNSLATION_OFFSET | 237 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_LOCAL_WRITE); 238 ucseg->klm_octowords = rte_cpu_to_be_16(klm_align); 239 /* Set mkey context seg. */ 240 mkc->len = rte_cpu_to_be_64(total_len); 241 mkc->qpn_mkey = rte_cpu_to_be_32(0xffffff00 | 242 (mkey_job->imkey->id & 0xff)); 243 /* Set UMR pointer to data seg. */ 244 iklm->address = rte_cpu_to_be_64 245 ((uintptr_t)((char *)mkey_job->imkey_array)); 246 iklm->mkey = rte_cpu_to_be_32(qp->imkey_addr->lkey); 247 iklm->byte_count = rte_cpu_to_be_32(klm_align); 248 /* Clear the padding memory. */ 249 memset((uint8_t *)&mkey_job->imkey_array[klm_size], 0, 250 sizeof(struct mlx5_klm) * (klm_align - klm_size)); 251 252 /* Add the following RegEx WQE with fence. */ 253 wqe = (struct mlx5_wqe_ctrl_seg *) 254 (((uint8_t *)wqe) + MLX5_REGEX_UMR_WQE_SIZE); 255 wqe->fm_ce_se |= MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE; 256 } 257 258 static inline void 259 prep_nop_regex_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, 260 struct rte_regex_ops *op, struct mlx5_regex_job *job, 261 size_t pi, struct mlx5_klm *klm) 262 { 263 size_t wqe_offset = (pi & (sq_size_get(sq) - 1)) * 264 (MLX5_SEND_WQE_BB << 2); 265 struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *) 266 (uintptr_t)sq->sq_obj.wqes + wqe_offset); 267 268 /* Clear the WQE memory used as UMR WQE previously. */ 269 if ((rte_be_to_cpu_32(wqe->opmod_idx_opcode) & 0xff) != MLX5_OPCODE_NOP) 270 memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE); 271 /* UMR WQE size is 9 DS, align nop WQE to 3 WQEBBS(12 DS). */ 272 set_wqe_ctrl_seg(wqe, pi * 4, MLX5_OPCODE_NOP, 0, sq->sq_obj.sq->id, 273 0, 12, 0, 0); 274 __prep_one(priv, sq, op, job, pi, klm); 275 } 276 277 static inline void 278 prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 279 struct mlx5_regex_sq *sq, struct rte_regex_ops **op, size_t nb_ops) 280 { 281 struct mlx5_regex_job *job = NULL; 282 size_t sqid = sq->sqn, mkey_job_id = 0; 283 size_t left_ops = nb_ops; 284 uint32_t klm_num = 0, len; 285 struct mlx5_klm *mkey_klm = NULL; 286 struct mlx5_klm klm; 287 288 sqid = sq->sqn; 289 while (left_ops--) 290 rte_prefetch0(op[left_ops]); 291 left_ops = nb_ops; 292 /* 293 * Build the WQE set by reverse. In case the burst may consume 294 * multiple mkeys, build the WQE set as normal will hard to 295 * address the last mkey index, since we will only know the last 296 * RegEx WQE's index when finishes building. 297 */ 298 while (left_ops--) { 299 struct rte_mbuf *mbuf = op[left_ops]->mbuf; 300 size_t pi = MLX5_REGEX_UMR_SQ_PI_IDX(sq->pi, left_ops); 301 302 if (mbuf->nb_segs > 1) { 303 size_t scatter_size = 0; 304 305 if (!mkey_klm_available(mkey_klm, klm_num, 306 mbuf->nb_segs)) { 307 /* 308 * The mkey's KLM is full, create the UMR 309 * WQE in the next WQE set. 310 */ 311 if (mkey_klm) 312 complete_umr_wqe(qp, sq, 313 &qp->jobs[mkey_job_id], 314 MLX5_REGEX_UMR_SQ_PI_IDX(pi, 1), 315 klm_num, len); 316 /* 317 * Get the indircet mkey and KLM array index 318 * from the last WQE set. 319 */ 320 mkey_job_id = job_id_get(sqid, 321 sq_size_get(sq), pi); 322 mkey_klm = qp->jobs[mkey_job_id].imkey_array; 323 klm_num = 0; 324 len = 0; 325 } 326 /* Build RegEx WQE's data segment KLM. */ 327 klm.address = len; 328 klm.mkey = rte_cpu_to_be_32 329 (qp->jobs[mkey_job_id].imkey->id); 330 while (mbuf) { 331 /* Build indirect mkey seg's KLM. */ 332 mkey_klm->mkey = mlx5_mr_addr2mr_bh(priv->pd, 333 NULL, &priv->mr_scache, &qp->mr_ctrl, 334 rte_pktmbuf_mtod(mbuf, uintptr_t), 335 !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); 336 mkey_klm->address = rte_cpu_to_be_64 337 (rte_pktmbuf_mtod(mbuf, uintptr_t)); 338 mkey_klm->byte_count = rte_cpu_to_be_32 339 (rte_pktmbuf_data_len(mbuf)); 340 /* 341 * Save the mbuf's total size for RegEx data 342 * segment. 343 */ 344 scatter_size += rte_pktmbuf_data_len(mbuf); 345 mkey_klm++; 346 klm_num++; 347 mbuf = mbuf->next; 348 } 349 len += scatter_size; 350 klm.byte_count = scatter_size; 351 } else { 352 /* The single mubf case. Build the KLM directly. */ 353 klm.mkey = mlx5_mr_addr2mr_bh(priv->pd, NULL, 354 &priv->mr_scache, &qp->mr_ctrl, 355 rte_pktmbuf_mtod(mbuf, uintptr_t), 356 !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); 357 klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t); 358 klm.byte_count = rte_pktmbuf_data_len(mbuf); 359 } 360 job = &qp->jobs[job_id_get(sqid, sq_size_get(sq), pi)]; 361 /* 362 * Build the nop + RegEx WQE set by default. The fist nop WQE 363 * will be updated later as UMR WQE if scattered mubf exist. 364 */ 365 prep_nop_regex_wqe_set(priv, sq, op[left_ops], job, pi, &klm); 366 } 367 /* 368 * Scattered mbuf have been added to the KLM array. Complete the build 369 * of UMR WQE, update the first nop WQE as UMR WQE. 370 */ 371 if (mkey_klm) 372 complete_umr_wqe(qp, sq, &qp->jobs[mkey_job_id], sq->pi, 373 klm_num, len); 374 sq->db_pi = MLX5_REGEX_UMR_SQ_PI_IDX(sq->pi, nb_ops - 1); 375 sq->pi = MLX5_REGEX_UMR_SQ_PI_IDX(sq->pi, nb_ops); 376 } 377 378 uint16_t 379 mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, 380 struct rte_regex_ops **ops, uint16_t nb_ops) 381 { 382 struct mlx5_regex_priv *priv = dev->data->dev_private; 383 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 384 struct mlx5_regex_sq *sq; 385 size_t sqid, nb_left = nb_ops, nb_desc; 386 387 while ((sqid = ffs(queue->free_sqs))) { 388 sqid--; /* ffs returns 1 for bit 0 */ 389 sq = &queue->sqs[sqid]; 390 nb_desc = get_free(sq, priv->has_umr); 391 if (nb_desc) { 392 /* The ops be handled can't exceed nb_ops. */ 393 if (nb_desc > nb_left) 394 nb_desc = nb_left; 395 else 396 queue->free_sqs &= ~(1 << sqid); 397 prep_regex_umr_wqe_set(priv, queue, sq, ops, nb_desc); 398 send_doorbell(priv, sq); 399 nb_left -= nb_desc; 400 } 401 if (!nb_left) 402 break; 403 ops += nb_desc; 404 } 405 nb_ops -= nb_left; 406 queue->pi += nb_ops; 407 return nb_ops; 408 } 409 #endif 410 411 uint16_t 412 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 413 struct rte_regex_ops **ops, uint16_t nb_ops) 414 { 415 struct mlx5_regex_priv *priv = dev->data->dev_private; 416 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 417 struct mlx5_regex_sq *sq; 418 size_t sqid, job_id, i = 0; 419 420 while ((sqid = ffs(queue->free_sqs))) { 421 sqid--; /* ffs returns 1 for bit 0 */ 422 sq = &queue->sqs[sqid]; 423 while (get_free(sq, priv->has_umr)) { 424 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 425 prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); 426 i++; 427 if (unlikely(i == nb_ops)) { 428 send_doorbell(priv, sq); 429 goto out; 430 } 431 } 432 queue->free_sqs &= ~(1 << sqid); 433 send_doorbell(priv, sq); 434 } 435 436 out: 437 queue->pi += i; 438 return i; 439 } 440 441 #define MLX5_REGEX_RESP_SZ 8 442 443 static inline void 444 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 445 { 446 size_t j; 447 size_t offset; 448 uint16_t status; 449 450 op->user_id = job->user_id; 451 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 452 MLX5_REGEX_METADATA_OFF, 453 match_count); 454 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 455 job->metadata + 456 MLX5_REGEX_METADATA_OFF, 457 detected_match_count); 458 for (j = 0; j < op->nb_matches; j++) { 459 offset = MLX5_REGEX_RESP_SZ * j; 460 op->matches[j].rule_id = 461 MLX5_GET_VOLATILE(regexp_match_tuple, 462 (job->output + offset), rule_id); 463 op->matches[j].start_offset = 464 MLX5_GET_VOLATILE(regexp_match_tuple, 465 (job->output + offset), start_ptr); 466 op->matches[j].len = 467 MLX5_GET_VOLATILE(regexp_match_tuple, 468 (job->output + offset), length); 469 } 470 status = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 471 MLX5_REGEX_METADATA_OFF, 472 status); 473 op->rsp_flags = 0; 474 if (status & MLX5_RXP_RESP_STATUS_PMI_SOJ) 475 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F; 476 if (status & MLX5_RXP_RESP_STATUS_PMI_EOJ) 477 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F; 478 if (status & MLX5_RXP_RESP_STATUS_MAX_LATENCY) 479 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F; 480 if (status & MLX5_RXP_RESP_STATUS_MAX_MATCH) 481 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F; 482 if (status & MLX5_RXP_RESP_STATUS_MAX_PREFIX) 483 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F; 484 if (status & MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS) 485 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 486 if (status & MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS) 487 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 488 } 489 490 static inline volatile struct mlx5_cqe * 491 poll_one(struct mlx5_regex_cq *cq) 492 { 493 volatile struct mlx5_cqe *cqe; 494 size_t next_cqe_offset; 495 496 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 497 cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset); 498 rte_io_wmb(); 499 500 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 501 502 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 503 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 504 return NULL; 505 } 506 507 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 508 return NULL; 509 510 return cqe; 511 } 512 513 514 /** 515 * DPDK callback for dequeue. 516 * 517 * @param dev 518 * Pointer to the regex dev structure. 519 * @param qp_id 520 * The queue to enqueue the traffic to. 521 * @param ops 522 * List of regex ops to dequeue. 523 * @param nb_ops 524 * Number of ops in ops parameter. 525 * 526 * @return 527 * Number of packets successfully dequeued (<= pkts_n). 528 */ 529 uint16_t 530 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 531 struct rte_regex_ops **ops, uint16_t nb_ops) 532 { 533 struct mlx5_regex_priv *priv = dev->data->dev_private; 534 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 535 struct mlx5_regex_cq *cq = &queue->cq; 536 volatile struct mlx5_cqe *cqe; 537 size_t i = 0; 538 539 while ((cqe = poll_one(cq))) { 540 uint16_t wq_counter 541 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 542 MLX5_REGEX_MAX_WQE_INDEX; 543 size_t sqid = cqe->rsvd3[2]; 544 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 545 546 /* UMR mode WQE counter move as WQE set(4 WQEBBS).*/ 547 if (priv->has_umr) 548 wq_counter >>= 2; 549 while (sq->ci != wq_counter) { 550 if (unlikely(i == nb_ops)) { 551 /* Return without updating cq->ci */ 552 goto out; 553 } 554 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 555 sq->ci); 556 extract_result(ops[i], &queue->jobs[job_id]); 557 sq->ci = (sq->ci + 1) & (priv->has_umr ? 558 (MLX5_REGEX_MAX_WQE_INDEX >> 2) : 559 MLX5_REGEX_MAX_WQE_INDEX); 560 i++; 561 } 562 cq->ci = (cq->ci + 1) & 0xffffff; 563 rte_wmb(); 564 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci); 565 queue->free_sqs |= (1 << sqid); 566 } 567 568 out: 569 queue->ci += i; 570 return i; 571 } 572 573 static void 574 setup_sqs(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) 575 { 576 size_t sqid, entry; 577 uint32_t job_id; 578 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 579 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 580 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes; 581 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 582 job_id = sqid * sq_size_get(sq) + entry; 583 struct mlx5_regex_job *job = &queue->jobs[job_id]; 584 585 /* Fill UMR WQE with NOP in advanced. */ 586 if (priv->has_umr) { 587 set_wqe_ctrl_seg 588 ((struct mlx5_wqe_ctrl_seg *)wqe, 589 entry * 2, MLX5_OPCODE_NOP, 0, 590 sq->sq_obj.sq->id, 0, 12, 0, 0); 591 wqe += MLX5_REGEX_UMR_WQE_SIZE; 592 } 593 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 594 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 595 0, queue->metadata->lkey, 596 (uintptr_t)job->metadata); 597 set_data_seg((struct mlx5_wqe_data_seg *) 598 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 599 MLX5_REGEX_MAX_OUTPUT, 600 queue->outputs->lkey, 601 (uintptr_t)job->output); 602 wqe += 64; 603 } 604 queue->free_sqs |= 1 << sqid; 605 } 606 } 607 608 static int 609 setup_buffers(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp) 610 { 611 struct ibv_pd *pd = priv->pd; 612 uint32_t i; 613 int err; 614 615 void *ptr = rte_calloc(__func__, qp->nb_desc, 616 MLX5_REGEX_METADATA_SIZE, 617 MLX5_REGEX_METADATA_SIZE); 618 if (!ptr) 619 return -ENOMEM; 620 621 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 622 MLX5_REGEX_METADATA_SIZE * qp->nb_desc, 623 IBV_ACCESS_LOCAL_WRITE); 624 if (!qp->metadata) { 625 DRV_LOG(ERR, "Failed to register metadata"); 626 rte_free(ptr); 627 return -EINVAL; 628 } 629 630 ptr = rte_calloc(__func__, qp->nb_desc, 631 MLX5_REGEX_MAX_OUTPUT, 632 MLX5_REGEX_MAX_OUTPUT); 633 if (!ptr) { 634 err = -ENOMEM; 635 goto err_output; 636 } 637 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 638 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 639 IBV_ACCESS_LOCAL_WRITE); 640 if (!qp->outputs) { 641 rte_free(ptr); 642 DRV_LOG(ERR, "Failed to register output"); 643 err = -EINVAL; 644 goto err_output; 645 } 646 647 if (priv->has_umr) { 648 ptr = rte_calloc(__func__, qp->nb_desc, MLX5_REGEX_KLMS_SIZE, 649 MLX5_REGEX_KLMS_SIZE); 650 if (!ptr) { 651 err = -ENOMEM; 652 goto err_imkey; 653 } 654 qp->imkey_addr = mlx5_glue->reg_mr(pd, ptr, 655 MLX5_REGEX_KLMS_SIZE * qp->nb_desc, 656 IBV_ACCESS_LOCAL_WRITE); 657 if (!qp->imkey_addr) { 658 rte_free(ptr); 659 DRV_LOG(ERR, "Failed to register output"); 660 err = -EINVAL; 661 goto err_imkey; 662 } 663 } 664 665 /* distribute buffers to jobs */ 666 for (i = 0; i < qp->nb_desc; i++) { 667 qp->jobs[i].output = 668 (uint8_t *)qp->outputs->addr + 669 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 670 qp->jobs[i].metadata = 671 (uint8_t *)qp->metadata->addr + 672 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 673 if (qp->imkey_addr) 674 qp->jobs[i].imkey_array = (struct mlx5_klm *) 675 qp->imkey_addr->addr + 676 (i % qp->nb_desc) * MLX5_REGEX_MAX_KLM_NUM; 677 } 678 679 return 0; 680 681 err_imkey: 682 ptr = qp->outputs->addr; 683 rte_free(ptr); 684 mlx5_glue->dereg_mr(qp->outputs); 685 err_output: 686 ptr = qp->metadata->addr; 687 rte_free(ptr); 688 mlx5_glue->dereg_mr(qp->metadata); 689 return err; 690 } 691 692 int 693 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 694 { 695 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 696 struct mlx5_klm klm = { 0 }; 697 struct mlx5_devx_mkey_attr attr = { 698 .klm_array = &klm, 699 .klm_num = 1, 700 .umr_en = 1, 701 }; 702 uint32_t i; 703 int err = 0; 704 705 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64); 706 if (!qp->jobs) 707 return -ENOMEM; 708 err = setup_buffers(priv, qp); 709 if (err) { 710 rte_free(qp->jobs); 711 return err; 712 } 713 714 setup_sqs(priv, qp); 715 716 if (priv->has_umr) { 717 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 718 if (regex_get_pdn(priv->pd, &attr.pd)) { 719 err = -rte_errno; 720 DRV_LOG(ERR, "Failed to get pdn."); 721 mlx5_regexdev_teardown_fastpath(priv, qp_id); 722 return err; 723 } 724 #endif 725 for (i = 0; i < qp->nb_desc; i++) { 726 attr.klm_num = MLX5_REGEX_MAX_KLM_NUM; 727 attr.klm_array = qp->jobs[i].imkey_array; 728 qp->jobs[i].imkey = mlx5_devx_cmd_mkey_create(priv->ctx, 729 &attr); 730 if (!qp->jobs[i].imkey) { 731 err = -rte_errno; 732 DRV_LOG(ERR, "Failed to allocate imkey."); 733 mlx5_regexdev_teardown_fastpath(priv, qp_id); 734 } 735 } 736 } 737 return err; 738 } 739 740 static void 741 free_buffers(struct mlx5_regex_qp *qp) 742 { 743 if (qp->imkey_addr) { 744 mlx5_glue->dereg_mr(qp->imkey_addr); 745 rte_free(qp->imkey_addr->addr); 746 } 747 if (qp->metadata) { 748 mlx5_glue->dereg_mr(qp->metadata); 749 rte_free(qp->metadata->addr); 750 } 751 if (qp->outputs) { 752 mlx5_glue->dereg_mr(qp->outputs); 753 rte_free(qp->outputs->addr); 754 } 755 } 756 757 void 758 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 759 { 760 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 761 uint32_t i; 762 763 if (qp) { 764 for (i = 0; i < qp->nb_desc; i++) { 765 if (qp->jobs[i].imkey) 766 claim_zero(mlx5_devx_cmd_destroy 767 (qp->jobs[i].imkey)); 768 } 769 free_buffers(qp); 770 if (qp->jobs) 771 rte_free(qp->jobs); 772 } 773 } 774