1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <sys/mman.h> 7 8 #include <rte_malloc.h> 9 #include <rte_log.h> 10 #include <rte_errno.h> 11 #include <rte_bus_pci.h> 12 #include <rte_pci.h> 13 #include <rte_regexdev_driver.h> 14 #include <rte_mbuf.h> 15 16 #include <infiniband/mlx5dv.h> 17 #include <mlx5_glue.h> 18 #include <mlx5_common.h> 19 #include <mlx5_prm.h> 20 #include <strings.h> 21 22 #include "mlx5_regex_utils.h" 23 #include "mlx5_rxp.h" 24 #include "mlx5_regex.h" 25 26 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 27 #define MLX5_REGEX_METADATA_SIZE 64 28 #define MLX5_REGEX_MAX_INPUT (1 << 14) 29 #define MLX5_REGEX_MAX_OUTPUT (1 << 11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 36 static inline uint32_t 37 sq_size_get(struct mlx5_regex_sq *sq) 38 { 39 return (1U << sq->log_nb_desc); 40 } 41 42 static inline uint32_t 43 cq_size_get(struct mlx5_regex_cq *cq) 44 { 45 return (1U << cq->log_nb_desc); 46 } 47 48 struct mlx5_regex_job { 49 uint64_t user_id; 50 uint8_t *input; 51 volatile uint8_t *output; 52 volatile uint8_t *metadata; 53 } __rte_cached_aligned; 54 55 static inline void 56 set_data_seg(struct mlx5_wqe_data_seg *seg, 57 uint32_t length, uint32_t lkey, 58 uintptr_t address) 59 { 60 seg->byte_count = rte_cpu_to_be_32(length); 61 seg->lkey = rte_cpu_to_be_32(lkey); 62 seg->addr = rte_cpu_to_be_64(address); 63 } 64 65 static inline void 66 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 67 uint32_t mmo_control_31_0, uint32_t lkey, 68 uintptr_t address) 69 { 70 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 71 seg->lkey = rte_cpu_to_be_32(lkey); 72 seg->addr = rte_cpu_to_be_64(address); 73 } 74 75 static inline void 76 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 77 uint16_t subset_id1, uint16_t subset_id2, 78 uint16_t subset_id3, uint8_t ctrl) 79 { 80 MLX5_SET(regexp_mmo_control, seg, le, le); 81 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 82 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 83 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 84 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 85 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 86 } 87 88 static inline void 89 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 90 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 91 uint8_t signature, uint32_t imm) 92 { 93 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 94 ((uint32_t)pi << 8) | 95 opcode); 96 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 97 seg->fm_ce_se = fm_ce_se; 98 seg->signature = signature; 99 seg->imm = imm; 100 } 101 102 static inline void 103 prep_one(struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 104 struct mlx5_regex_job *job) 105 { 106 size_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB; 107 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 108 int ds = 4; /* ctrl + meta + input + output */ 109 110 memcpy(job->input, 111 rte_pktmbuf_mtod(op->mbuf, void *), 112 rte_pktmbuf_data_len(op->mbuf)); 113 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi, 114 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, sq->obj->id, 115 0, ds, 0, 0); 116 set_regex_ctrl_seg(wqe + 12, 0, op->group_id0, op->group_id1, 117 op->group_id2, 118 op->group_id3, 0); 119 struct mlx5_wqe_data_seg *input_seg = 120 (struct mlx5_wqe_data_seg *)(wqe + 121 MLX5_REGEX_WQE_GATHER_OFFSET); 122 input_seg->byte_count = 123 rte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf)); 124 job->user_id = op->user_id; 125 sq->db_pi = sq->pi; 126 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 127 } 128 129 static inline void 130 send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq) 131 { 132 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 133 MLX5_SEND_WQE_BB; 134 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 135 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 136 uint64_t *doorbell_addr = 137 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 138 rte_cio_wmb(); 139 sq->dbr[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) & 140 MLX5_REGEX_MAX_WQE_INDEX); 141 rte_wmb(); 142 *doorbell_addr = *(volatile uint64_t *)wqe; 143 rte_wmb(); 144 } 145 146 static inline int 147 can_send(struct mlx5_regex_sq *sq) { 148 return ((uint16_t)(sq->pi - sq->ci) < sq_size_get(sq)); 149 } 150 151 static inline uint32_t 152 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 153 return qid * sq_size + (index & (sq_size - 1)); 154 } 155 156 uint16_t 157 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 158 struct rte_regex_ops **ops, uint16_t nb_ops) 159 { 160 struct mlx5_regex_priv *priv = dev->data->dev_private; 161 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 162 struct mlx5_regex_sq *sq; 163 size_t sqid, job_id, i = 0; 164 165 while ((sqid = ffs(queue->free_sqs))) { 166 sqid--; /* ffs returns 1 for bit 0 */ 167 sq = &queue->sqs[sqid]; 168 while (can_send(sq)) { 169 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 170 prep_one(sq, ops[i], &queue->jobs[job_id]); 171 i++; 172 if (unlikely(i == nb_ops)) { 173 send_doorbell(priv->uar, sq); 174 goto out; 175 } 176 } 177 queue->free_sqs &= ~(1 << sqid); 178 send_doorbell(priv->uar, sq); 179 } 180 181 out: 182 queue->pi += i; 183 return i; 184 } 185 186 #define MLX5_REGEX_RESP_SZ 8 187 188 static inline void 189 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 190 { 191 size_t j, offset; 192 op->user_id = job->user_id; 193 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 194 MLX5_REGEX_METADATA_OFF, 195 match_count); 196 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 197 job->metadata + 198 MLX5_REGEX_METADATA_OFF, 199 detected_match_count); 200 for (j = 0; j < op->nb_matches; j++) { 201 offset = MLX5_REGEX_RESP_SZ * j; 202 op->matches[j].rule_id = 203 MLX5_GET_VOLATILE(regexp_match_tuple, 204 (job->output + offset), rule_id); 205 op->matches[j].start_offset = 206 MLX5_GET_VOLATILE(regexp_match_tuple, 207 (job->output + offset), start_ptr); 208 op->matches[j].len = 209 MLX5_GET_VOLATILE(regexp_match_tuple, 210 (job->output + offset), length); 211 } 212 } 213 214 static inline volatile struct mlx5_cqe * 215 poll_one(struct mlx5_regex_cq *cq) 216 { 217 volatile struct mlx5_cqe *cqe; 218 size_t next_cqe_offset; 219 220 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 221 cqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset); 222 rte_cio_wmb(); 223 224 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 225 226 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 227 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 228 return NULL; 229 } 230 231 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 232 return NULL; 233 234 return cqe; 235 } 236 237 238 /** 239 * DPDK callback for dequeue. 240 * 241 * @param dev 242 * Pointer to the regex dev structure. 243 * @param qp_id 244 * The queue to enqueue the traffic to. 245 * @param ops 246 * List of regex ops to dequeue. 247 * @param nb_ops 248 * Number of ops in ops parameter. 249 * 250 * @return 251 * Number of packets successfully dequeued (<= pkts_n). 252 */ 253 uint16_t 254 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 255 struct rte_regex_ops **ops, uint16_t nb_ops) 256 { 257 struct mlx5_regex_priv *priv = dev->data->dev_private; 258 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 259 struct mlx5_regex_cq *cq = &queue->cq; 260 volatile struct mlx5_cqe *cqe; 261 size_t i = 0; 262 263 while ((cqe = poll_one(cq))) { 264 uint16_t wq_counter 265 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 266 MLX5_REGEX_MAX_WQE_INDEX; 267 size_t sqid = cqe->rsvd3[2]; 268 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 269 while (sq->ci != wq_counter) { 270 if (unlikely(i == nb_ops)) { 271 /* Return without updating cq->ci */ 272 goto out; 273 } 274 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 275 sq->ci); 276 extract_result(ops[i], &queue->jobs[job_id]); 277 sq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX; 278 i++; 279 } 280 cq->ci = (cq->ci + 1) & 0xffffff; 281 rte_wmb(); 282 cq->dbr[0] = rte_cpu_to_be_32(cq->ci); 283 queue->free_sqs |= (1 << sqid); 284 } 285 286 out: 287 queue->ci += i; 288 return i; 289 } 290 291 static void 292 setup_sqs(struct mlx5_regex_qp *queue) 293 { 294 size_t sqid, entry; 295 uint32_t job_id; 296 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 297 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 298 uint8_t *wqe = (uint8_t *)sq->wqe; 299 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 300 job_id = sqid * sq_size_get(sq) + entry; 301 struct mlx5_regex_job *job = &queue->jobs[job_id]; 302 303 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 304 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 305 0, queue->metadata->lkey, 306 (uintptr_t)job->metadata); 307 set_data_seg((struct mlx5_wqe_data_seg *) 308 (wqe + MLX5_REGEX_WQE_GATHER_OFFSET), 309 0, queue->inputs->lkey, 310 (uintptr_t)job->input); 311 set_data_seg((struct mlx5_wqe_data_seg *) 312 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 313 MLX5_REGEX_MAX_OUTPUT, 314 queue->outputs->lkey, 315 (uintptr_t)job->output); 316 wqe += 64; 317 } 318 queue->free_sqs |= 1 << sqid; 319 } 320 } 321 322 static int 323 setup_buffers(struct mlx5_regex_qp *qp, struct ibv_pd *pd) 324 { 325 uint32_t i; 326 int err; 327 328 void *ptr = rte_calloc(__func__, qp->nb_desc, 329 MLX5_REGEX_METADATA_SIZE, 330 MLX5_REGEX_METADATA_SIZE); 331 if (!ptr) 332 return -ENOMEM; 333 334 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 335 MLX5_REGEX_METADATA_SIZE*qp->nb_desc, 336 IBV_ACCESS_LOCAL_WRITE); 337 if (!qp->metadata) { 338 rte_free(ptr); 339 return -EINVAL; 340 } 341 ptr = rte_calloc(__func__, qp->nb_desc, 342 MLX5_REGEX_MAX_INPUT, 343 MLX5_REGEX_MAX_INPUT); 344 345 if (!ptr) { 346 err = -ENOMEM; 347 goto err_input; 348 } 349 qp->inputs = mlx5_glue->reg_mr(pd, ptr, 350 MLX5_REGEX_MAX_INPUT*qp->nb_desc, 351 IBV_ACCESS_LOCAL_WRITE); 352 if (!qp->inputs) { 353 rte_free(ptr); 354 err = -EINVAL; 355 goto err_input; 356 } 357 358 ptr = rte_calloc(__func__, qp->nb_desc, 359 MLX5_REGEX_MAX_OUTPUT, 360 MLX5_REGEX_MAX_OUTPUT); 361 if (!ptr) { 362 err = -ENOMEM; 363 goto err_output; 364 } 365 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 366 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 367 IBV_ACCESS_LOCAL_WRITE); 368 if (!qp->outputs) { 369 rte_free(ptr); 370 err = -EINVAL; 371 goto err_output; 372 } 373 374 /* distribute buffers to jobs */ 375 for (i = 0; i < qp->nb_desc; i++) { 376 qp->jobs[i].input = 377 (uint8_t *)qp->inputs->addr + 378 (i % qp->nb_desc) * MLX5_REGEX_MAX_INPUT; 379 qp->jobs[i].output = 380 (uint8_t *)qp->outputs->addr + 381 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 382 qp->jobs[i].metadata = 383 (uint8_t *)qp->metadata->addr + 384 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 385 } 386 return 0; 387 388 err_output: 389 ptr = qp->inputs->addr; 390 rte_free(ptr); 391 mlx5_glue->dereg_mr(qp->inputs); 392 err_input: 393 ptr = qp->metadata->addr; 394 rte_free(ptr); 395 mlx5_glue->dereg_mr(qp->metadata); 396 return err; 397 } 398 399 int 400 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 401 { 402 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 403 int err; 404 405 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 406 sizeof(*qp->jobs)); 407 if (!qp->jobs) 408 return -ENOMEM; 409 err = setup_buffers(qp, priv->pd); 410 if (err) 411 return err; 412 setup_sqs(qp); 413 return 0; 414 } 415