1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <strings.h> 7 #include <stdint.h> 8 #include <sys/mman.h> 9 10 #include <rte_malloc.h> 11 #include <rte_log.h> 12 #include <rte_errno.h> 13 #include <rte_bus_pci.h> 14 #include <rte_pci.h> 15 #include <rte_regexdev_driver.h> 16 #include <rte_mbuf.h> 17 18 #include <infiniband/mlx5dv.h> 19 #include <mlx5_glue.h> 20 #include <mlx5_common.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_regex_utils.h" 24 #include "mlx5_rxp.h" 25 #include "mlx5_regex.h" 26 27 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 28 #define MLX5_REGEX_METADATA_SIZE UINT32_C(64) 29 #define MLX5_REGEX_MAX_OUTPUT RTE_BIT32(11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 36 static inline uint32_t 37 sq_size_get(struct mlx5_regex_sq *sq) 38 { 39 return (1U << sq->log_nb_desc); 40 } 41 42 static inline uint32_t 43 cq_size_get(struct mlx5_regex_cq *cq) 44 { 45 return (1U << cq->log_nb_desc); 46 } 47 48 struct mlx5_regex_job { 49 uint64_t user_id; 50 volatile uint8_t *output; 51 volatile uint8_t *metadata; 52 } __rte_cached_aligned; 53 54 static inline void 55 set_data_seg(struct mlx5_wqe_data_seg *seg, 56 uint32_t length, uint32_t lkey, 57 uintptr_t address) 58 { 59 seg->byte_count = rte_cpu_to_be_32(length); 60 seg->lkey = rte_cpu_to_be_32(lkey); 61 seg->addr = rte_cpu_to_be_64(address); 62 } 63 64 static inline void 65 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 66 uint32_t mmo_control_31_0, uint32_t lkey, 67 uintptr_t address) 68 { 69 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 70 seg->lkey = rte_cpu_to_be_32(lkey); 71 seg->addr = rte_cpu_to_be_64(address); 72 } 73 74 static inline void 75 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 76 uint16_t subset_id1, uint16_t subset_id2, 77 uint16_t subset_id3, uint8_t ctrl) 78 { 79 MLX5_SET(regexp_mmo_control, seg, le, le); 80 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 81 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 82 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 83 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 84 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 85 } 86 87 static inline void 88 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 89 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 90 uint8_t signature, uint32_t imm) 91 { 92 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 93 ((uint32_t)pi << 8) | 94 opcode); 95 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 96 seg->fm_ce_se = fm_ce_se; 97 seg->signature = signature; 98 seg->imm = imm; 99 } 100 101 static inline void 102 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 103 struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 104 struct mlx5_regex_job *job) 105 { 106 size_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB; 107 uint32_t lkey; 108 109 lkey = mlx5_mr_addr2mr_bh(priv->pd, 0, 110 &priv->mr_scache, &qp->mr_ctrl, 111 rte_pktmbuf_mtod(op->mbuf, uintptr_t), 112 !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); 113 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 114 int ds = 4; /* ctrl + meta + input + output */ 115 116 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi, 117 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, sq->obj->id, 118 0, ds, 0, 0); 119 set_regex_ctrl_seg(wqe + 12, 0, op->group_id0, op->group_id1, 120 op->group_id2, 121 op->group_id3, 0); 122 struct mlx5_wqe_data_seg *input_seg = 123 (struct mlx5_wqe_data_seg *)(wqe + 124 MLX5_REGEX_WQE_GATHER_OFFSET); 125 input_seg->byte_count = 126 rte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf)); 127 input_seg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(op->mbuf, 128 uintptr_t)); 129 input_seg->lkey = lkey; 130 job->user_id = op->user_id; 131 sq->db_pi = sq->pi; 132 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 133 } 134 135 static inline void 136 send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq) 137 { 138 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 139 MLX5_SEND_WQE_BB; 140 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 141 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 142 uint64_t *doorbell_addr = 143 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 144 rte_io_wmb(); 145 sq->dbr[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) & 146 MLX5_REGEX_MAX_WQE_INDEX); 147 rte_wmb(); 148 *doorbell_addr = *(volatile uint64_t *)wqe; 149 rte_wmb(); 150 } 151 152 static inline int 153 can_send(struct mlx5_regex_sq *sq) { 154 return ((uint16_t)(sq->pi - sq->ci) < sq_size_get(sq)); 155 } 156 157 static inline uint32_t 158 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 159 return qid * sq_size + (index & (sq_size - 1)); 160 } 161 162 uint16_t 163 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 164 struct rte_regex_ops **ops, uint16_t nb_ops) 165 { 166 struct mlx5_regex_priv *priv = dev->data->dev_private; 167 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 168 struct mlx5_regex_sq *sq; 169 size_t sqid, job_id, i = 0; 170 171 while ((sqid = ffs(queue->free_sqs))) { 172 sqid--; /* ffs returns 1 for bit 0 */ 173 sq = &queue->sqs[sqid]; 174 while (can_send(sq)) { 175 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 176 prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); 177 i++; 178 if (unlikely(i == nb_ops)) { 179 send_doorbell(priv->uar, sq); 180 goto out; 181 } 182 } 183 queue->free_sqs &= ~(1 << sqid); 184 send_doorbell(priv->uar, sq); 185 } 186 187 out: 188 queue->pi += i; 189 return i; 190 } 191 192 #define MLX5_REGEX_RESP_SZ 8 193 194 static inline void 195 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 196 { 197 size_t j, offset; 198 op->user_id = job->user_id; 199 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 200 MLX5_REGEX_METADATA_OFF, 201 match_count); 202 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 203 job->metadata + 204 MLX5_REGEX_METADATA_OFF, 205 detected_match_count); 206 for (j = 0; j < op->nb_matches; j++) { 207 offset = MLX5_REGEX_RESP_SZ * j; 208 op->matches[j].rule_id = 209 MLX5_GET_VOLATILE(regexp_match_tuple, 210 (job->output + offset), rule_id); 211 op->matches[j].start_offset = 212 MLX5_GET_VOLATILE(regexp_match_tuple, 213 (job->output + offset), start_ptr); 214 op->matches[j].len = 215 MLX5_GET_VOLATILE(regexp_match_tuple, 216 (job->output + offset), length); 217 } 218 } 219 220 static inline volatile struct mlx5_cqe * 221 poll_one(struct mlx5_regex_cq *cq) 222 { 223 volatile struct mlx5_cqe *cqe; 224 size_t next_cqe_offset; 225 226 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 227 cqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset); 228 rte_io_wmb(); 229 230 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 231 232 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 233 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 234 return NULL; 235 } 236 237 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 238 return NULL; 239 240 return cqe; 241 } 242 243 244 /** 245 * DPDK callback for dequeue. 246 * 247 * @param dev 248 * Pointer to the regex dev structure. 249 * @param qp_id 250 * The queue to enqueue the traffic to. 251 * @param ops 252 * List of regex ops to dequeue. 253 * @param nb_ops 254 * Number of ops in ops parameter. 255 * 256 * @return 257 * Number of packets successfully dequeued (<= pkts_n). 258 */ 259 uint16_t 260 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 261 struct rte_regex_ops **ops, uint16_t nb_ops) 262 { 263 struct mlx5_regex_priv *priv = dev->data->dev_private; 264 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 265 struct mlx5_regex_cq *cq = &queue->cq; 266 volatile struct mlx5_cqe *cqe; 267 size_t i = 0; 268 269 while ((cqe = poll_one(cq))) { 270 uint16_t wq_counter 271 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 272 MLX5_REGEX_MAX_WQE_INDEX; 273 size_t sqid = cqe->rsvd3[2]; 274 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 275 while (sq->ci != wq_counter) { 276 if (unlikely(i == nb_ops)) { 277 /* Return without updating cq->ci */ 278 goto out; 279 } 280 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 281 sq->ci); 282 extract_result(ops[i], &queue->jobs[job_id]); 283 sq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX; 284 i++; 285 } 286 cq->ci = (cq->ci + 1) & 0xffffff; 287 rte_wmb(); 288 cq->dbr[0] = rte_cpu_to_be_32(cq->ci); 289 queue->free_sqs |= (1 << sqid); 290 } 291 292 out: 293 queue->ci += i; 294 return i; 295 } 296 297 static void 298 setup_sqs(struct mlx5_regex_qp *queue) 299 { 300 size_t sqid, entry; 301 uint32_t job_id; 302 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 303 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 304 uint8_t *wqe = (uint8_t *)sq->wqe; 305 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 306 job_id = sqid * sq_size_get(sq) + entry; 307 struct mlx5_regex_job *job = &queue->jobs[job_id]; 308 309 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 310 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 311 0, queue->metadata->lkey, 312 (uintptr_t)job->metadata); 313 set_data_seg((struct mlx5_wqe_data_seg *) 314 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 315 MLX5_REGEX_MAX_OUTPUT, 316 queue->outputs->lkey, 317 (uintptr_t)job->output); 318 wqe += 64; 319 } 320 queue->free_sqs |= 1 << sqid; 321 } 322 } 323 324 static int 325 setup_buffers(struct mlx5_regex_qp *qp, struct ibv_pd *pd) 326 { 327 uint32_t i; 328 int err; 329 330 void *ptr = rte_calloc(__func__, qp->nb_desc, 331 MLX5_REGEX_METADATA_SIZE, 332 MLX5_REGEX_METADATA_SIZE); 333 if (!ptr) 334 return -ENOMEM; 335 336 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 337 MLX5_REGEX_METADATA_SIZE*qp->nb_desc, 338 IBV_ACCESS_LOCAL_WRITE); 339 if (!qp->metadata) { 340 DRV_LOG(ERR, "Failed to register metadata"); 341 rte_free(ptr); 342 return -EINVAL; 343 } 344 345 ptr = rte_calloc(__func__, qp->nb_desc, 346 MLX5_REGEX_MAX_OUTPUT, 347 MLX5_REGEX_MAX_OUTPUT); 348 if (!ptr) { 349 err = -ENOMEM; 350 goto err_output; 351 } 352 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 353 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 354 IBV_ACCESS_LOCAL_WRITE); 355 if (!qp->outputs) { 356 rte_free(ptr); 357 DRV_LOG(ERR, "Failed to register output"); 358 err = -EINVAL; 359 goto err_output; 360 } 361 362 /* distribute buffers to jobs */ 363 for (i = 0; i < qp->nb_desc; i++) { 364 qp->jobs[i].output = 365 (uint8_t *)qp->outputs->addr + 366 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 367 qp->jobs[i].metadata = 368 (uint8_t *)qp->metadata->addr + 369 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 370 } 371 return 0; 372 373 err_output: 374 ptr = qp->metadata->addr; 375 rte_free(ptr); 376 mlx5_glue->dereg_mr(qp->metadata); 377 return err; 378 } 379 380 int 381 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 382 { 383 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 384 int err; 385 386 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64); 387 if (!qp->jobs) 388 return -ENOMEM; 389 err = setup_buffers(qp, priv->pd); 390 if (err) { 391 rte_free(qp->jobs); 392 return err; 393 } 394 setup_sqs(qp); 395 return 0; 396 } 397 398 static void 399 free_buffers(struct mlx5_regex_qp *qp) 400 { 401 if (qp->metadata) { 402 mlx5_glue->dereg_mr(qp->metadata); 403 rte_free(qp->metadata->addr); 404 } 405 if (qp->outputs) { 406 mlx5_glue->dereg_mr(qp->outputs); 407 rte_free(qp->outputs->addr); 408 } 409 } 410 411 void 412 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 413 { 414 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 415 416 if (qp) { 417 free_buffers(qp); 418 if (qp->jobs) 419 rte_free(qp->jobs); 420 } 421 } 422