1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <sys/mman.h> 7 8 #include <rte_malloc.h> 9 #include <rte_log.h> 10 #include <rte_errno.h> 11 #include <rte_bus_pci.h> 12 #include <rte_pci.h> 13 #include <rte_regexdev_driver.h> 14 #include <rte_mbuf.h> 15 16 #include <infiniband/mlx5dv.h> 17 #include <mlx5_glue.h> 18 #include <mlx5_common.h> 19 #include <mlx5_prm.h> 20 #include <strings.h> 21 22 #include "mlx5_regex_utils.h" 23 #include "mlx5_rxp.h" 24 #include "mlx5_regex.h" 25 26 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 27 #define MLX5_REGEX_METADATA_SIZE 64 28 #define MLX5_REGEX_MAX_INPUT (1 << 14) 29 #define MLX5_REGEX_MAX_OUTPUT (1 << 11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 36 static inline uint32_t 37 sq_size_get(struct mlx5_regex_sq *sq) 38 { 39 return (1U << sq->log_nb_desc); 40 } 41 42 static inline uint32_t 43 cq_size_get(struct mlx5_regex_cq *cq) 44 { 45 return (1U << cq->log_nb_desc); 46 } 47 48 struct mlx5_regex_job { 49 uint64_t user_id; 50 uint8_t *input; 51 volatile uint8_t *output; 52 volatile uint8_t *metadata; 53 } __rte_cached_aligned; 54 55 static inline void 56 set_data_seg(struct mlx5_wqe_data_seg *seg, 57 uint32_t length, uint32_t lkey, 58 uintptr_t address) 59 { 60 seg->byte_count = rte_cpu_to_be_32(length); 61 seg->lkey = rte_cpu_to_be_32(lkey); 62 seg->addr = rte_cpu_to_be_64(address); 63 } 64 65 static inline void 66 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 67 uint32_t mmo_control_31_0, uint32_t lkey, 68 uintptr_t address) 69 { 70 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 71 seg->lkey = rte_cpu_to_be_32(lkey); 72 seg->addr = rte_cpu_to_be_64(address); 73 } 74 75 static inline void 76 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 77 uint16_t subset_id1, uint16_t subset_id2, 78 uint16_t subset_id3, uint8_t ctrl) 79 { 80 MLX5_SET(regexp_mmo_control, seg, le, le); 81 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 82 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 83 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 84 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 85 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 86 } 87 88 static inline void 89 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 90 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 91 uint8_t signature, uint32_t imm) 92 { 93 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 94 ((uint32_t)pi << 8) | 95 opcode); 96 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 97 seg->fm_ce_se = fm_ce_se; 98 seg->signature = signature; 99 seg->imm = imm; 100 } 101 102 static inline void 103 prep_one(struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 104 struct mlx5_regex_job *job) 105 { 106 size_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB; 107 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 108 int ds = 4; /* ctrl + meta + input + output */ 109 110 memcpy(job->input, 111 rte_pktmbuf_mtod(op->mbuf, void *), 112 rte_pktmbuf_data_len(op->mbuf)); 113 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi, 114 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, sq->obj->id, 115 0, ds, 0, 0); 116 set_regex_ctrl_seg(wqe + 12, 0, op->group_id0, op->group_id1, 117 op->group_id2, 118 op->group_id3, 0); 119 struct mlx5_wqe_data_seg *input_seg = 120 (struct mlx5_wqe_data_seg *)(wqe + 121 MLX5_REGEX_WQE_GATHER_OFFSET); 122 input_seg->byte_count = 123 rte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf)); 124 job->user_id = op->user_id; 125 sq->db_pi = sq->pi; 126 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 127 } 128 129 static inline void 130 send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq) 131 { 132 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 133 MLX5_SEND_WQE_BB; 134 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 135 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 136 uint64_t *doorbell_addr = 137 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 138 rte_cio_wmb(); 139 sq->dbr[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) & 140 MLX5_REGEX_MAX_WQE_INDEX); 141 rte_wmb(); 142 *doorbell_addr = *(volatile uint64_t *)wqe; 143 rte_wmb(); 144 } 145 146 static inline int 147 can_send(struct mlx5_regex_sq *sq) { 148 return unlikely(sq->ci > sq->pi) ? 149 MLX5_REGEX_MAX_WQE_INDEX + sq->pi - sq->ci < 150 sq_size_get(sq) : 151 sq->pi - sq->ci < sq_size_get(sq); 152 } 153 154 static inline uint32_t 155 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 156 return qid * sq_size + (index & (sq_size - 1)); 157 } 158 159 uint16_t 160 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 161 struct rte_regex_ops **ops, uint16_t nb_ops) 162 { 163 struct mlx5_regex_priv *priv = dev->data->dev_private; 164 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 165 struct mlx5_regex_sq *sq; 166 size_t sqid, job_id, i = 0; 167 168 while ((sqid = ffs(queue->free_sqs))) { 169 sqid--; /* ffs returns 1 for bit 0 */ 170 sq = &queue->sqs[sqid]; 171 while (can_send(sq)) { 172 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 173 prep_one(sq, ops[i], &queue->jobs[job_id]); 174 i++; 175 if (unlikely(i == nb_ops)) { 176 send_doorbell(priv->uar, sq); 177 goto out; 178 } 179 } 180 queue->free_sqs &= ~(1 << sqid); 181 send_doorbell(priv->uar, sq); 182 } 183 184 out: 185 queue->pi += i; 186 return i; 187 } 188 189 #define MLX5_REGEX_RESP_SZ 8 190 191 static inline void 192 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 193 { 194 size_t j, offset; 195 op->user_id = job->user_id; 196 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 197 MLX5_REGEX_METADATA_OFF, 198 match_count); 199 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 200 job->metadata + 201 MLX5_REGEX_METADATA_OFF, 202 detected_match_count); 203 for (j = 0; j < op->nb_matches; j++) { 204 offset = MLX5_REGEX_RESP_SZ * j; 205 op->matches[j].rule_id = 206 MLX5_GET_VOLATILE(regexp_match_tuple, 207 (job->output + offset), rule_id); 208 op->matches[j].start_offset = 209 MLX5_GET_VOLATILE(regexp_match_tuple, 210 (job->output + offset), start_ptr); 211 op->matches[j].len = 212 MLX5_GET_VOLATILE(regexp_match_tuple, 213 (job->output + offset), length); 214 } 215 } 216 217 static inline volatile struct mlx5_cqe * 218 poll_one(struct mlx5_regex_cq *cq) 219 { 220 volatile struct mlx5_cqe *cqe; 221 size_t next_cqe_offset; 222 223 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 224 cqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset); 225 rte_cio_wmb(); 226 227 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 228 229 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 230 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 231 return NULL; 232 } 233 234 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 235 return NULL; 236 237 return cqe; 238 } 239 240 241 /** 242 * DPDK callback for dequeue. 243 * 244 * @param dev 245 * Pointer to the regex dev structure. 246 * @param qp_id 247 * The queue to enqueue the traffic to. 248 * @param ops 249 * List of regex ops to dequeue. 250 * @param nb_ops 251 * Number of ops in ops parameter. 252 * 253 * @return 254 * Number of packets successfully dequeued (<= pkts_n). 255 */ 256 uint16_t 257 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 258 struct rte_regex_ops **ops, uint16_t nb_ops) 259 { 260 struct mlx5_regex_priv *priv = dev->data->dev_private; 261 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 262 struct mlx5_regex_cq *cq = &queue->cq; 263 volatile struct mlx5_cqe *cqe; 264 size_t i = 0; 265 266 while ((cqe = poll_one(cq))) { 267 uint16_t wq_counter 268 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 269 MLX5_REGEX_MAX_WQE_INDEX; 270 size_t sqid = cqe->rsvd3[2]; 271 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 272 while (sq->ci != wq_counter) { 273 if (unlikely(i == nb_ops)) { 274 /* Return without updating cq->ci */ 275 goto out; 276 } 277 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 278 sq->ci); 279 extract_result(ops[i], &queue->jobs[job_id]); 280 sq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX; 281 i++; 282 } 283 cq->ci = (cq->ci + 1) & 0xffffff; 284 rte_wmb(); 285 cq->dbr[0] = rte_cpu_to_be_32(cq->ci); 286 queue->free_sqs |= (1 << sqid); 287 } 288 289 out: 290 queue->ci += i; 291 return i; 292 } 293 294 static void 295 setup_sqs(struct mlx5_regex_qp *queue) 296 { 297 size_t sqid, entry; 298 uint32_t job_id; 299 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 300 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 301 uint8_t *wqe = (uint8_t *)sq->wqe; 302 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 303 job_id = sqid * sq_size_get(sq) + entry; 304 struct mlx5_regex_job *job = &queue->jobs[job_id]; 305 306 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 307 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 308 0, queue->metadata->lkey, 309 (uintptr_t)job->metadata); 310 set_data_seg((struct mlx5_wqe_data_seg *) 311 (wqe + MLX5_REGEX_WQE_GATHER_OFFSET), 312 0, queue->inputs->lkey, 313 (uintptr_t)job->input); 314 set_data_seg((struct mlx5_wqe_data_seg *) 315 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 316 MLX5_REGEX_MAX_OUTPUT, 317 queue->outputs->lkey, 318 (uintptr_t)job->output); 319 wqe += 64; 320 } 321 queue->free_sqs |= 1 << sqid; 322 } 323 } 324 325 static int 326 setup_buffers(struct mlx5_regex_qp *qp, struct ibv_pd *pd) 327 { 328 uint32_t i; 329 int err; 330 331 void *ptr = rte_calloc(__func__, qp->nb_desc, 332 MLX5_REGEX_METADATA_SIZE, 333 MLX5_REGEX_METADATA_SIZE); 334 if (!ptr) 335 return -ENOMEM; 336 337 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 338 MLX5_REGEX_METADATA_SIZE*qp->nb_desc, 339 IBV_ACCESS_LOCAL_WRITE); 340 if (!qp->metadata) { 341 rte_free(ptr); 342 return -EINVAL; 343 } 344 ptr = rte_calloc(__func__, qp->nb_desc, 345 MLX5_REGEX_MAX_INPUT, 346 MLX5_REGEX_MAX_INPUT); 347 348 if (!ptr) { 349 err = -ENOMEM; 350 goto err_input; 351 } 352 qp->inputs = mlx5_glue->reg_mr(pd, ptr, 353 MLX5_REGEX_MAX_INPUT*qp->nb_desc, 354 IBV_ACCESS_LOCAL_WRITE); 355 if (!qp->inputs) { 356 rte_free(ptr); 357 err = -EINVAL; 358 goto err_input; 359 } 360 361 ptr = rte_calloc(__func__, qp->nb_desc, 362 MLX5_REGEX_MAX_OUTPUT, 363 MLX5_REGEX_MAX_OUTPUT); 364 if (!ptr) { 365 err = -ENOMEM; 366 goto err_output; 367 } 368 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 369 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 370 IBV_ACCESS_LOCAL_WRITE); 371 if (!qp->outputs) { 372 rte_free(ptr); 373 err = -EINVAL; 374 goto err_output; 375 } 376 377 /* distribute buffers to jobs */ 378 for (i = 0; i < qp->nb_desc; i++) { 379 qp->jobs[i].input = 380 (uint8_t *)qp->inputs->addr + 381 (i % qp->nb_desc) * MLX5_REGEX_MAX_INPUT; 382 qp->jobs[i].output = 383 (uint8_t *)qp->outputs->addr + 384 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 385 qp->jobs[i].metadata = 386 (uint8_t *)qp->metadata->addr + 387 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 388 } 389 return 0; 390 391 err_output: 392 ptr = qp->inputs->addr; 393 rte_free(ptr); 394 mlx5_glue->dereg_mr(qp->inputs); 395 err_input: 396 ptr = qp->metadata->addr; 397 rte_free(ptr); 398 mlx5_glue->dereg_mr(qp->metadata); 399 return err; 400 } 401 402 int 403 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 404 { 405 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 406 int err; 407 408 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 409 sizeof(*qp->jobs)); 410 if (!qp->jobs) 411 return -ENOMEM; 412 err = setup_buffers(qp, priv->pd); 413 if (err) 414 return err; 415 setup_sqs(qp); 416 return 0; 417 } 418